[all-commits] [llvm/llvm-project] 50efa5: Reland [llvm] Add support for llvm IR atomicrmw fm...

[Jonathan Thackray via All-commits]

  Branch: refs/heads/users/jthackray/new-atomics
  Home:   https://github.com/llvm/llvm-project
  Commit: 50efa5baf3655eff6ab2d8dd701ee5b2152001f6
      https://github.com/llvm/llvm-project/commit/50efa5baf3655eff6ab2d8dd701ee5b2152001f6
  Author: Jonathan Thackray <jonathan.thackray at arm.com>
  Date:   2025-04-28 (Mon, 28 Apr 2025)

  Changed paths:
    M llvm/docs/GlobalISel/GenericOpcode.rst
    M llvm/docs/LangRef.rst
    M llvm/docs/ReleaseNotes.md
    M llvm/include/llvm-c/Core.h
    M llvm/include/llvm/AsmParser/LLToken.h
    M llvm/include/llvm/Bitcode/LLVMBitCodes.h
    M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
    M llvm/include/llvm/CodeGen/ISDOpcodes.h
    M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
    M llvm/include/llvm/IR/Instructions.h
    M llvm/include/llvm/Support/TargetOpcodes.def
    M llvm/include/llvm/Target/GenericOpcodes.td
    M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
    M llvm/include/llvm/Target/TargetSelectionDAG.td
    M llvm/lib/AsmParser/LLLexer.cpp
    M llvm/lib/AsmParser/LLParser.cpp
    M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
    M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
    M llvm/lib/CodeGen/AtomicExpandPass.cpp
    M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
    M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
    M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
    M llvm/lib/IR/Core.cpp
    M llvm/lib/IR/Instructions.cpp
    M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
    M llvm/lib/Transforms/Utils/LowerAtomic.cpp
    M llvm/test/Assembler/atomic.ll
    M llvm/test/Bitcode/compatibility.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
    M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-cxx.td
    M llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
    M llvm/test/Transforms/AtomicExpand/AArch64/atomicrmw-fp.ll
    M llvm/test/Transforms/InstCombine/atomicrmw.ll
    M llvm/test/Transforms/LowerAtomic/atomic-load.ll

  Log Message:
  -----------
  Reland [llvm] Add support for llvm IR atomicrmw fminimum/fmaximum instructions (#136759)

This patch adds support for LLVM IR atomicrmw `fmaximum` and `fminimum`
instructions.

These mirror the `llvm.maximum.*` and `llvm.minimum.*` instructions, but
are atomic and use IEEE754 2019 handling for NaNs, which is different to
`fmax` and `fmin`. See:
     https://llvm.org/docs/LangRef.html#llvm-minimum-intrinsic
for more details.

Future changes will allow this LLVM IR to be lowered to specialised
assembler instructions on suitable targets, such as AArch64.



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