[all-commits] [llvm/llvm-project] ca2150: [Targets] Migrate from atomic_load_8/16/32/64 to a...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ca21508080031c3eda1c6085f1de9cc26be4c336
      https://github.com/llvm/llvm-project/commit/ca21508080031c3eda1c6085f1de9cc26be4c336
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-04-28 (Mon, 28 Apr 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrAtomics.td
    M llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
    M llvm/lib/Target/AMDGPU/BUFInstructions.td
    M llvm/lib/Target/AMDGPU/DSInstructions.td
    M llvm/lib/Target/AMDGPU/FLATInstructions.td
    M llvm/lib/Target/AMDGPU/SIInstrInfo.td
    M llvm/lib/Target/ARM/ARMInstrInfo.td
    M llvm/lib/Target/ARM/ARMInstrThumb.td
    M llvm/lib/Target/ARM/ARMInstrThumb2.td
    M llvm/lib/Target/AVR/AVRInstrInfo.td
    M llvm/lib/Target/BPF/BPFInstrInfo.td
    M llvm/lib/Target/Hexagon/HexagonPatterns.td
    M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
    M llvm/lib/Target/Mips/MicroMipsInstrInfo.td
    M llvm/lib/Target/Mips/Mips64InstrInfo.td
    M llvm/lib/Target/Mips/MipsInstrInfo.td
    M llvm/lib/Target/PowerPC/PPCInstr64Bit.td
    M llvm/lib/Target/PowerPC/PPCInstrInfo.td
    M llvm/lib/Target/PowerPC/PPCInstrP10.td
    M llvm/lib/Target/RISCV/RISCVGISel.td
    M llvm/lib/Target/Sparc/SparcInstr64Bit.td
    M llvm/lib/Target/Sparc/SparcInstrInfo.td
    M llvm/lib/Target/VE/VEInstrInfo.td
    M llvm/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td
    M llvm/lib/Target/X86/X86InstrCompiler.td

  Log Message:
  -----------
  [Targets] Migrate from atomic_load_8/16/32/64 to atomic_load_nonext_8/16/32/64. NFC (#137428)

This makes them more consistent with the checks performed by regular loads. We can't simply add IsNonExtLoad to the existing atomic_load_8/16/32/64 as that would affect out of tree targets.



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