[all-commits] [llvm/llvm-project] d7e631: [RISCV] Remove `AND` mask generated by `( zext ( ...

[Jan Górski via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d7e631c7cd6d9c13b9519991ec6becf08bc6b8aa
      https://github.com/llvm/llvm-project/commit/d7e631c7cd6d9c13b9519991ec6becf08bc6b8aa
  Author: Jan Górski <jan.a.gorski at wp.pl>
  Date:   2025-04-28 (Mon, 28 Apr 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
    M llvm/test/CodeGen/RISCV/atomic-load-zext.ll

  Log Message:
  -----------
  [RISCV] Remove `AND` mask generated by `( zext  ( atomic_load ) )` by replacing the load with `zextload` for orderings not stronger then monotonic. (#136502)

Extends changes from
[ff687af](https://github.com/llvm/llvm-project/commit/ff687af04f5b0e85305250587b524cb0b3849aa0).
Fixes https://github.com/llvm/llvm-project/issues/131476.

This patch adds a DAG combine to replace an `AND` of an `ATOMIC_LOAD`
with a full-bit mask (e.g. `0xFF`, `0xFFFF`, etc.) which is generated as
a result of `(zext (atomic_load))`, by a zero-extended load, provided
the atomic operation is monotonic or weaker.



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