[all-commits] [llvm/llvm-project] 6ba1a6: [RISCV] Add Andes XAndesperf (Andes Performance) e...

[Jim Lin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6ba1a62a6c512e32bf85f21b59b2c8e507d1a72e
      https://github.com/llvm/llvm-project/commit/6ba1a62a6c512e32bf85f21b59b2c8e507d1a72e
  Author: Jim Lin <jim at andestech.com>
  Date:   2025-04-28 (Mon, 28 Apr 2025)

  Changed paths:
    M clang/test/Driver/print-supported-extensions-riscv.c
    M llvm/docs/RISCVUsage.rst
    M llvm/docs/ReleaseNotes.md
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
    A llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/CodeGen/RISCV/features-info.ll
    A llvm/test/MC/RISCV/xandesperf-invalid.s
    A llvm/test/MC/RISCV/xandesperf-rv64-invalid.s
    A llvm/test/MC/RISCV/xandesperf-rv64-valid.s
    A llvm/test/MC/RISCV/xandesperf-valid.s
    M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

  Log Message:
  -----------
  [RISCV] Add Andes XAndesperf (Andes Performance) extension. (#135110)

The spec can be found at:
https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release.

This patch only supports assembler.

Relocation and fixup for the branch and gp-implied instructions will be
added in a later patch.



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