[all-commits] [llvm/llvm-project] 59fbb9: [AArch64] Add tablegen patterns for i8 and i16 vec...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 59fbb9e7751b36bbca1064abb6c21ce59c038a70
      https://github.com/llvm/llvm-project/commit/59fbb9e7751b36bbca1064abb6c21ce59c038a70
  Author: David Green <david.green at arm.com>
  Date:   2025-04-28 (Mon, 28 Apr 2025)

  Changed paths:
    M llvm/include/llvm/Target/TargetSelectionDAG.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/arm64-extract-insert-varidx.ll
    M llvm/test/CodeGen/AArch64/bitcast-extend.ll
    M llvm/test/CodeGen/AArch64/fix-shuffle-vector-be-rev.ll
    M llvm/test/CodeGen/AArch64/itofp.ll
    M llvm/test/CodeGen/AArch64/neon-bitcast.ll
    M llvm/test/CodeGen/AArch64/shuffle-extend.ll
    M llvm/test/CodeGen/AArch64/vector-fcvt.ll

  Log Message:
  -----------
  [AArch64] Add tablegen patterns for i8 and i16 vector insert/extract pairs (#136091)

An i8 and i16 vector extract/insert has to go via a i32 to make sure the
types are legal. This patch adds patterns for extract from a i8/i16
vector, inserted into a i16/i32 vector. This avoids the round trip via a
GPR which can limit performance.



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