[all-commits] [llvm/llvm-project] 576be7: [AArch64][SVE] Generate asrd instruction for posit...

[Sushant Gokhale via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 576be7b19f91ad3a3a44e66a398575b8c417bfe5
      https://github.com/llvm/llvm-project/commit/576be7b19f91ad3a3a44e66a398575b8c417bfe5
  Author: Sushant Gokhale <sgokhale at nvidia.com>
  Date:   2025-04-27 (Sun, 27 Apr 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/sve-fixed-length-sdiv-pow2.ll

  Log Message:
  -----------
  [AArch64][SVE] Generate asrd instruction for positive pow-2 divisors … (#137151)

…when SVE is available

Currently,
```
sdiv(x, y)  --> cmlt + usra + sshr                , where y is positive pow-2 integer
sdiv(x, y)  --> cmlt + usra + sshr + neg     , where y is negative pow-2 integer
```

Patch aims to transform this into
```
sdiv(x, y)  --> ptrue + asrd                 , where y is positive pow-2 integer
sdiv(x, y)  --> ptrue + asrd + subr     ,  where y is negative pow-2 integer
```



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