[all-commits] [llvm/llvm-project] 72bc05: [AMDGPU][True16][CodeGen] update wwm reg sorting c...

[Brox Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 72bc0525d88c2df4a2c370ad8a11de8d0fdd52bf
      https://github.com/llvm/llvm-project/commit/72bc0525d88c2df4a2c370ad8a11de8d0fdd52bf
  Author: Brox Chen <guochen2 at amd.com>
  Date:   2025-04-27 (Sun, 27 Apr 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
    A llvm/test/CodeGen/AMDGPU/wwm-reg-shift-down-gfx11plus.mir

  Log Message:
  -----------
  [AMDGPU][True16][CodeGen] update wwm reg sorting check condition (#135053)

We currently just need to shift down 32bit wwm registers. 

Previous check condition mistakenly select 16bit registers in true16
mode. Update check condition to skip the 16bit register in wmm reg
sorting



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