[all-commits] [llvm/llvm-project] cfc5ba: [RISCV] SiFive CLIC Support (#132481)

[Sam Elliott via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cfc5baf6e6fc083fdbb584534a3fb8ea289752d2
      https://github.com/llvm/llvm-project/commit/cfc5baf6e6fc083fdbb584534a3fb8ea289752d2
  Author: Sam Elliott <quic_aelliott at quicinc.com>
  Date:   2025-04-25 (Fri, 25 Apr 2025)

  Changed paths:
    M clang/docs/ReleaseNotes.rst
    M clang/include/clang/Basic/Attr.td
    M clang/include/clang/Basic/AttrDocs.td
    M clang/include/clang/Basic/DiagnosticSemaKinds.td
    M clang/lib/CodeGen/Targets/RISCV.cpp
    M clang/lib/Sema/SemaRISCV.cpp
    M clang/test/Driver/print-supported-extensions-riscv.c
    M clang/test/Sema/riscv-interrupt-attr-qci.c
    A clang/test/Sema/riscv-interrupt-attr-sifive.c
    M clang/test/Sema/riscv-interrupt-attr.c
    M llvm/docs/ReleaseNotes.md
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp
    M llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
    M llvm/lib/Target/RISCV/RISCVSystemOperands.td
    M llvm/test/CodeGen/RISCV/features-info.ll
    A llvm/test/CodeGen/RISCV/sifive-interrupt-attr-err.ll
    A llvm/test/CodeGen/RISCV/sifive-interrupt-attr.ll
    A llvm/test/MC/RISCV/xsfmclic-invalid.s
    A llvm/test/MC/RISCV/xsfmclic-valid.s
    A llvm/test/MC/RISCV/xsfsclic-invalid.s
    A llvm/test/MC/RISCV/xsfsclic-valid.s
    M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

  Log Message:
  -----------
  [RISCV] SiFive CLIC Support (#132481)

This Change adds support for two SiFive vendor attributes in clang:
- "SiFive-CLIC-preemptible"
- "SiFive-CLIC-stack-swap"

These can be given together, and can be combined with "machine", but
cannot be combined with any other interrupt attribute values.

These are handled primarily in RISCVFrameLowering:
- "SiFive-CLIC-stack-swap" entails swapping `sp` with `sf.mscratchcsw`
  at function entry and exit, which holds the trap stack pointer.
- "SiFive-CLIC-preemptible" entails saving `mcause` and `mepc` before
  re-enabling interrupts using `mstatus`. To save these, `s0` and `s1`
  are first spilled to the stack, and then the values are read into
  these registers. If these registers are used in the function, their
  values will be spilled a second time onto the stack with the generic
  callee-saved-register handling. At the end of the function interrupts
  are disabled again before `mepc` and `mcause` are restored.

This Change also adds support for the following two experimental
extensions, which only contain CSRs:
- XSfsclic - for SiFive's CLIC Supervisor-Mode CSRs
- XSfmclic - for SiFive's CLIC Machine-Mode CSRs

The latter is needed for interrupt support.

The CFI information for this implementation is not correct, but I'd
prefer to correct this in a follow-up. While it's unlikely anyone wants
to unwind through a handler, the CFI information is also used by
debuggers so it would be good to get it right.

Co-authored-by: Ana Pazos <apazos at quicinc.com>



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