[all-commits] [llvm/llvm-project] 5dc2d6: [SelectionDAG][Targets] Replace atomic_load_8/atom...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5dc2d668e68613e8898c5c42960d792129453e9d
      https://github.com/llvm/llvm-project/commit/5dc2d668e68613e8898c5c42960d792129453e9d
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-04-25 (Fri, 25 Apr 2025)

  Changed paths:
    M llvm/include/llvm/Target/TargetSelectionDAG.td
    M llvm/lib/Target/AArch64/AArch64InstrAtomics.td
    M llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
    M llvm/lib/Target/AMDGPU/BUFInstructions.td
    M llvm/lib/Target/AMDGPU/DSInstructions.td
    M llvm/lib/Target/AMDGPU/FLATInstructions.td
    M llvm/lib/Target/AMDGPU/SIInstrInfo.td
    M llvm/lib/Target/ARM/ARMInstrInfo.td
    M llvm/lib/Target/ARM/ARMInstrThumb.td
    M llvm/lib/Target/ARM/ARMInstrThumb2.td
    M llvm/lib/Target/Hexagon/HexagonPatterns.td
    M llvm/lib/Target/Lanai/LanaiInstrInfo.td
    M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
    M llvm/lib/Target/Mips/MicroMipsInstrInfo.td
    M llvm/lib/Target/Mips/Mips64InstrInfo.td
    M llvm/lib/Target/Mips/MipsInstrInfo.td
    M llvm/lib/Target/PowerPC/PPCInstrInfo.td
    M llvm/lib/Target/PowerPC/PPCInstrP10.td
    M llvm/lib/Target/RISCV/RISCVGISel.td
    M llvm/lib/Target/Sparc/SparcInstrInfo.td
    M llvm/lib/Target/VE/VEInstrInfo.td
    M llvm/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td

  Log Message:
  -----------
  [SelectionDAG][Targets] Replace atomic_load_8/atomic_load_16 with atomic_load_*ext_8/atomic_load_*ext_16 where possible. (#137279)

isAnyExtLoad/isZExtLoad/isSignExtLoad are able to emit predicate checks
from tablegen now so we should use them.

The next step would be to add isNonExtLoad versions and migrate all
remaining uses of atomic_load_8/16/32/64 to that.



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