[all-commits] [llvm/llvm-project] 9062a3: [RISCV] Add codegen support for ri.vinsert.v.x and...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9062a38d5d15d74f8019a30b8a0012747dfad6a8
      https://github.com/llvm/llvm-project/commit/9062a38d5d15d74f8019a30b8a0012747dfad6a8
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2025-04-25 (Fri, 25 Apr 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll

  Log Message:
  -----------
  [RISCV] Add codegen support for ri.vinsert.v.x and ri.vextract.x.v (#136708)

These instructions are included in XRivosVisni. They perform a scalar
insert into a vector (with a potentially non-zero index) and a scalar
extract from a vector (with a potentially non-zero index) respectively.
They're very analogous to vmv.s.x and vmv.x.s respectively.

The instructions do have a couple restrictions:
1) Only constant indices are supported w/a uimm5 format.
2) There are no FP variants.

One important property of these instructions is that their throughput
and latency are expected to be LMUL independent.



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