[all-commits] [llvm/llvm-project] 02b55d: [AST] Call hash_combine_range with a range (NFC) (...
Amir Ayupov via All-commits
all-commits at lists.llvm.org
Thu Apr 24 14:22:01 PDT 2025
Branch: refs/heads/users/aaupov/spr/boltnfci-switch-heatmap-to-using-parsed-basicbranch-events
Home: https://github.com/llvm/llvm-project
Commit: 02b55d2b78d318dad331a66ddac81c7318b0b87a
https://github.com/llvm/llvm-project/commit/02b55d2b78d318dad331a66ddac81c7318b0b87a
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-20 (Sun, 20 Apr 2025)
Changed paths:
M clang/lib/AST/ItaniumCXXABI.cpp
Log Message:
-----------
[AST] Call hash_combine_range with a range (NFC) (#136525)
Commit: 6274442f8c657597233b9691298df7b5cd743e66
https://github.com/llvm/llvm-project/commit/6274442f8c657597233b9691298df7b5cd743e66
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-20 (Sun, 20 Apr 2025)
Changed paths:
M clang-tools-extra/clangd/SystemIncludeExtractor.cpp
Log Message:
-----------
[clangd] Call hash_combine_range with a range (NFC) (#136526)
Commit: 2ba20c52e43ae881dc54037fff94d7e2f217c99d
https://github.com/llvm/llvm-project/commit/2ba20c52e43ae881dc54037fff94d7e2f217c99d
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-20 (Sun, 20 Apr 2025)
Changed paths:
M lldb/source/Symbol/Symtab.cpp
M lldb/source/Target/Target.cpp
M lldb/tools/lldb-dap/Handler/BreakpointLocationsHandler.cpp
Log Message:
-----------
[lldb] Use llvm::unique (NFC) (#136527)
Commit: f024aab844ab89ab6455ddf1e2232a957c72328e
https://github.com/llvm/llvm-project/commit/f024aab844ab89ab6455ddf1e2232a957c72328e
Author: Jim Lin <jim at andestech.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
Log Message:
-----------
[RISCV] Remove the TODO that lbu and lhu should be selected to avoid the unnecessary masking. NFC.
RISCVTargetLowering::isZExtFree has been implemented in
https://github.com/llvm/llvm-project/commit/15e894baeeb96612ae471fa83d1729a2d3388fc8.
Commit: e183459b8b341ec787b2856be7e86a9e6200e2f8
https://github.com/llvm/llvm-project/commit/e183459b8b341ec787b2856be7e86a9e6200e2f8
Author: David Green <david.green at arm.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[CostModel] Make sure getCmpSelInstrCost is passed a CondTy (#135535)
It is already required along certain code paths that the CondTy is
valid. Fix some of the uses to make sure it is passed.
Commit: 2ba455ff3dd192ff814514647d485491510a6342
https://github.com/llvm/llvm-project/commit/2ba455ff3dd192ff814514647d485491510a6342
Author: David Green <david.green at arm.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
Log Message:
-----------
[AArch64] Add CostKind to getSpliceCost (#135537)
This likely does not alter much yet with how the costs are used. Like
other cost functions the CostKind should be passed into and through the
function.
Commit: 8435de0916d9df5a3a9dd9eeb44d5bf4aba87ba3
https://github.com/llvm/llvm-project/commit/8435de0916d9df5a3a9dd9eeb44d5bf4aba87ba3
Author: Tongsheng Wu <tongshengwu0 at gmail.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M clang-tools-extra/clangd/IncludeCleaner.cpp
Log Message:
-----------
[clangd] Print include spelling in IncludeCleaner error message (#136237)
Commit: 050ca5e27082055f41ad7e3dd2dea2f39364b3ab
https://github.com/llvm/llvm-project/commit/050ca5e27082055f41ad7e3dd2dea2f39364b3ab
Author: Henrich Lauko <xlauko at mail.muni.cz>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenStmt.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
Log Message:
-----------
[CIR][NFC] Simplify BoolAttr builders (#136366)
This mirrors incubator changes from https://github.com/llvm/clangir/pull/1572
Commit: b6820c35c59a4da3e59c11f657093ffbd79ae1db
https://github.com/llvm/llvm-project/commit/b6820c35c59a4da3e59c11f657093ffbd79ae1db
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/test/CodeGen/Hexagon/swp-epilog-phi11.ll
M llvm/test/CodeGen/Hexagon/swp-epilog-phi12.ll
M llvm/test/CodeGen/Hexagon/swp-epilog-phi13.ll
M llvm/test/CodeGen/Hexagon/swp-epilog-phi6.ll
M llvm/test/CodeGen/Hexagon/swp-epilog-phi9.ll
Log Message:
-----------
[MachinePipeliner] Remove UB from tests (NFC) (#123169)
This patch removes UB from some tests for MachinePipeliner. This patch
fixes following cases.
- Branching on an `undef` value.
- Using `undef`/`null` as a pointer operand of a load/store.
There are other tests of pipeliner that contain the same UB, but for
now, this patch fixes particularly unstable cases when I developed
pipeliner.
Commit: 4853bf0956058f4433fb81e880a2087da4487f26
https://github.com/llvm/llvm-project/commit/4853bf0956058f4433fb81e880a2087da4487f26
Author: tangaac <tangyan01 at loongson.cn>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
M llvm/test/CodeGen/LoongArch/lasx/broadcast-load.ll
M llvm/test/CodeGen/LoongArch/lsx/broadcast-load.ll
Log Message:
-----------
[LoongArch] Lower build_vector to broadcast load if possible (#135896)
Commit: 053451cb3502144564b4d0b30a9046045d1820d4
https://github.com/llvm/llvm-project/commit/053451cb3502144564b4d0b30a9046045d1820d4
Author: Luke Lau <luke at igalia.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/reduce-fadd.ll
Log Message:
-----------
[RISCV] Handle scalarized reductions in getArithmeticReductionCost
This fixes a crash reported at
https://github.com/llvm/llvm-project/pull/114250#issuecomment-2813686061
If the vector type isn't legal at all, e.g. bfloat with +zvfbfmin,
then the legalized type will be scalarized. So use getScalarType()
instead of getVectorElement() when checking for f16/bf16.
Commit: 6423c901fd5a5a8370a5326c5fbe16eb5a837374
https://github.com/llvm/llvm-project/commit/6423c901fd5a5a8370a5326c5fbe16eb5a837374
Author: Matthias Springer <me at m-sp.org>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M mlir/lib/Conversion/FuncToLLVM/FuncToLLVM.cpp
Log Message:
-----------
[mlir][LLVM][NFC] Avoid rollback in FuncOp --> LLVM lowering (#136477)
This pattern used to create an `llvm.func` op, then check additional
requirements and return "failure". This commit moves the checks before
the creation of the replacement op, so that no rollback is necessary
when one of the checks fails.
Note: This is in preparation of the One-Shot Dialect Conversion
refactoring, which removes the rollback functionality.
Commit: 47ca7f1cce56332ee8ac0d525a0172d3bce8508e
https://github.com/llvm/llvm-project/commit/47ca7f1cce56332ee8ac0d525a0172d3bce8508e
Author: AZero13 <gfunni234 at gmail.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/Target/X86/X86LowerTileCopy.cpp
Log Message:
-----------
[X86] Remove unused BitVector TILERegs (NFC) (#136508)
It is not used.
Commit: c347ad21ab55fc28cbc1366e86de3ad073dd693a
https://github.com/llvm/llvm-project/commit/c347ad21ab55fc28cbc1366e86de3ad073dd693a
Author: Liao Chunyu <chunyu at iscas.ac.cn>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
Log Message:
-----------
[RISCV][NFC] Delete RISCVAsmParser::parsePseudoQCJumpSymbol (#136552)
fix, warning:
RISCVAsmParser::parsePseudoQCJumpSymbol(llvm::OperandVector&)’ defined
but not used [-Wunused-function]
Commit: 940108b24d1d7cb25b06dd66c6529bddc7daefab
https://github.com/llvm/llvm-project/commit/940108b24d1d7cb25b06dd66c6529bddc7daefab
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
Log Message:
-----------
[AMDGPU][NewPM] Make the pass flow consistent with the legacy pipeline. (#136551)
Commit: 788b50a4384985f2c221cfd8d290cabc6f59e646
https://github.com/llvm/llvm-project/commit/788b50a4384985f2c221cfd8d290cabc6f59e646
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/test/CodeGen/X86/combine-fcopysign.ll
Log Message:
-----------
[X86] Add test coverage for #136368
Commit: f12078e72601e7c03e5d66afab034313caf8f791
https://github.com/llvm/llvm-project/commit/f12078e72601e7c03e5d66afab034313caf8f791
Author: zhijian lin <zhijian at ca.ibm.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll
M llvm/test/CodeGen/AArch64/optimize-cond-branch.ll
M llvm/test/CodeGen/AArch64/sve-extract-element.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/dead-machine-elim-after-dead-lane.ll
M llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll
M llvm/test/CodeGen/PowerPC/undef-args.ll
M llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
Log Message:
-----------
[SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode (#122741)
The PR will fix the issue
https://github.com/llvm/llvm-project/issues/122728
This patch addresses the signed/zero extension of poison by using a
poison value of the extended type instead of a constant zero of the
extended type.
Commit: 111af76bd74708929a048f94ef5c52af646f1c64
https://github.com/llvm/llvm-project/commit/111af76bd74708929a048f94ef5c52af646f1c64
Author: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
A clang/test/CodeGenDirectX/unsupported_intrinsic.hlsl
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/test/CodeGen/DirectX/unsupported_intrinsic.ll
Log Message:
-----------
[DirectX] add Function name to DiagnosticInfoUnsupported Msg in DXILOpLowering (#136234)
fixes #135654
In #128613 we added safe guards to prevent the lowering of just any
intrinsic in the backend. We used `DiagnosticInfoUnsupported` to do
this.
What we found was when using `opt` the diagnostic print function was
called but when using clang the diagnostic message was used.
Printing message in the clang version means we miss valuable debugging
information like function name and function type when LLVMContext was
only needed to call `getBestLocationFromDebugLoc`.
There are a few potential fixes
1. Write a custom DiagnosticInfoUnsupported so we can change the Message
just for DirectX. Too heavy handed so rejected.
2. Add the function name to the Message in DirectX code. Very simple one
line change. Downside is when using opt you see the function name twice.
But makes the clang-dxc bugs more actionable.
3. change CodeGenAction.cpp to always use the print function and not the
message directly. Downside is a bunch of innacurate information shows up
in the message if you don't specify `-debug-info-kind=standalone`.
4. add some book keeping to know which function called the intrinsic
keep a map of these so we can pass the calling function to
`DiagnosticInfoUnsupported` instead of the intrinsic. This would only be
useful if we had debug info so we could distinguish different uses of
the intrinsic by line\col number. We would also need to change from
iterating on every function to doing something like a LazyCallGraph
which is a nonstarter.
5. pick a different means of doing a Diagnostic error, because other
uses of `DiagnosticInfoUnsupported` error when we are in the body of a
function not when we see one being used like in the intrinsic case.
This PR went with a combo of option 2 & 5. Its low code change that also
only impacts the DirectX backend.
Commit: e18a77cfbe7549720d1a2584ab160edeb60963a6
https://github.com/llvm/llvm-project/commit/e18a77cfbe7549720d1a2584ab160edeb60963a6
Author: Nico Weber <thakis at chromium.org>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll
M llvm/test/CodeGen/AArch64/optimize-cond-branch.ll
M llvm/test/CodeGen/AArch64/sve-extract-element.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/dead-machine-elim-after-dead-lane.ll
M llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll
M llvm/test/CodeGen/PowerPC/undef-args.ll
M llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
Log Message:
-----------
Revert "[SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode (#122741)"
This reverts commit f12078e72601e7c03e5d66afab034313caf8f791.
Breaks `check-llvm`, see comments on https://github.com/llvm/llvm-project/pull/122741
Commit: 1cb82ff9cd95c216f6d8da18637ee47a15bd41f6
https://github.com/llvm/llvm-project/commit/1cb82ff9cd95c216f6d8da18637ee47a15bd41f6
Author: Michael Liao <michael.hliao at gmail.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRTypesDetails.h
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
Log Message:
-----------
[clang][CIR] Fix various warnings. NFC
- Fix various warnings including '-Wparentheses', '-Wunused-variable',
and '-Wreturn-type'.
Commit: 08b0c2517eb859667d59873bf04b6aa78a7583a7
https://github.com/llvm/llvm-project/commit/08b0c2517eb859667d59873bf04b6aa78a7583a7
Author: Oleksandr T. <oleksandr.tarasiuk at outlook.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Parse/Parser.cpp
A clang/test/Parser/extern-template-attributes.cpp
Log Message:
-----------
[Clang] disallow use of attributes before extern template declarations (#136328)
Fixes #79893
---
This PR addresses the issue of _attributes_ being incorrectly allowed on
`extern template` declarations
```cpp
[[deprecated]] extern template struct S<int>;
```
Commit: cfc2b0d094f705aa0995eff0dc5f1faf1440a769
https://github.com/llvm/llvm-project/commit/cfc2b0d094f705aa0995eff0dc5f1faf1440a769
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
M llvm/lib/CodeGen/SplitKit.cpp
M llvm/lib/Support/SuffixTree.cpp
Log Message:
-----------
[llvm] Use llvm::SmallVector::pop_back_val (NFC) (#136533)
Commit: e1bb7f6ddec37567230d3e46719aee5bcd268d5a
https://github.com/llvm/llvm-project/commit/e1bb7f6ddec37567230d3e46719aee5bcd268d5a
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/Target/AArch64/CMakeLists.txt
M llvm/test/TableGen/VarLenDecoder.td
M llvm/test/TableGen/trydecode-emission.td
M llvm/test/TableGen/trydecode-emission2.td
M llvm/test/TableGen/trydecode-emission3.td
M llvm/test/TableGen/trydecode-emission4.td
M llvm/utils/TableGen/DecoderEmitter.cpp
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[LLVM][TableGen] Parameterize NumToSkip in DecoderEmitter (#136456)
- Add command line option `num-to-skip-size` to parameterize the size of
`NumToSkip` bytes in the decoder table. Default value will be 2, and
targets that need larger size can use 3.
- Keep all existing targets, except AArch64, to use size 2, and change
AArch64 to use size 3 since it run into the "disassembler decoding table
too large" error with size 2.
- Additional fixes on top of earlier revert: mark `decodeNumToSkip` as
static (not necessary anymore as the generated code is now in anonymous
namespace, but doing it for consistency) and incorporate Bazel build
changes from https://github.com/llvm/llvm-project/pull/136212
- Following is a rough reduction in size for the decoder tables by
switching to size 2.
```
Target Old Size New Size % Reduction
================================================
AArch64 153254 153254 0.00
AMDGPU 471566 412805 12.46
ARC 5724 5061 11.58
ARM 84936 73831 13.07
AVR 1497 1306 12.76
BPF 2172 1927 11.28
CSKY 10064 8692 13.63
Hexagon 47967 41965 12.51
Lanai 1108 982 11.37
LoongArch 24446 21621 11.56
MSP430 4200 3716 11.52
Mips 36330 31415 13.53
PPC 31897 28098 11.91
RISCV 37979 32790 13.66
Sparc 8331 7252 12.95
SystemZ 36722 32248 12.18
VE 48296 42873 11.23
XCore 2590 2316 10.58
Xtensa 3827 3316 13.35
```
Commit: 52a5332a710d4db22327c3777ebf6873ff20732f
https://github.com/llvm/llvm-project/commit/52a5332a710d4db22327c3777ebf6873ff20732f
Author: Sarah Spall <sarahspall at microsoft.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/test/CodeGenHLSL/ArrayAssignable.hlsl
Log Message:
-----------
[HLSL] Make it possible to assign an array from a cbuffer (#134174)
Update Sema Checking to always do an HLSL Array RValue cast in the case
we are dealing with hlsl constant array types
Instead of comparing canonical types, compare canonical unqualified
types
Add a test to show it is possible to assign an array from a cbuffer.
Closes #133767
Commit: 93b74f7178e510a12f0eae700a25f7d3eb226265
https://github.com/llvm/llvm-project/commit/93b74f7178e510a12f0eae700a25f7d3eb226265
Author: Mircea Trofin <mtrofin at google.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/Analysis/CtxProfAnalysis.cpp
M llvm/test/Analysis/CtxProfAnalysis/flatten-and-annotate.ll
M llvm/test/Analysis/CtxProfAnalysis/flatten-check-path.ll
M llvm/test/Analysis/CtxProfAnalysis/flatten-insert-icp-mdprof.ll
M llvm/test/Analysis/CtxProfAnalysis/flatten-zero-path.ll
M llvm/test/Analysis/CtxProfAnalysis/full-cycle.ll
M llvm/test/Analysis/CtxProfAnalysis/inline.ll
M llvm/test/Analysis/CtxProfAnalysis/load.ll
Log Message:
-----------
[ctxprof] Scale up everything under a root by its `TotalRootEntryCount` (#136015)
`TotalRootEntryCount` captures how many times that root was entered - regardless if a profile was also collected or not (profile collection for a given root happens on only one thread at a time).
We don't do this in compiler_rt because the goal there is to flush out the data as fast as possible, so traversing and multiplying vectors is punted to the profile user.
We really just need to do this when flattening the profile so that the values across roots and flat profiles match. We could do it earlier, too - like when loading the profile - but it seems beneficial (at least for debugging) to keep the counter values the same as the loaded ones. We can revisit this later.
Commit: 86a03367bf62375cf0cc299a56f09bed5f0c4875
https://github.com/llvm/llvm-project/commit/86a03367bf62375cf0cc299a56f09bed5f0c4875
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
A flang/test/Analysis/AliasAnalysis/alias-analysis-pack-array.fir
Log Message:
-----------
[flang] Support fir.pack_array in FIR alias analysis. (#131946)
`fir.pack_array` is just a pass-through op for the process
of finding the source in FIR alias analysis (as defined in #127147).
Commit: 5133b432bc89f66547f6aab9a935f0a29f3b4572
https://github.com/llvm/llvm-project/commit/5133b432bc89f66547f6aab9a935f0a29f3b4572
Author: Daniel Chen <cdchen at ca.ibm.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/lib/Driver/Driver.cpp
A flang/test/Driver/m32-option.f90
Log Message:
-----------
Enable `-m32`, `-maix32` and `-maix64` for Flang on AIX. (#136202)
This PR enables `-m32`, -`maix32` and `-maix64` for AIX only. For other
platforms, the driver will issue an error that `-m32` is not supported.
Commit: 76ced7fa782f0d7db9efea871fa6de74706dd9cc
https://github.com/llvm/llvm-project/commit/76ced7fa782f0d7db9efea871fa6de74706dd9cc
Author: Pankaj Dwivedi <pankajkumar.divedi at amd.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/add64-low-32-bits-known-zero.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/constrained-shift.ll
M llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll
M llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/ptrmask.ll
M llvm/test/CodeGen/AMDGPU/sdag-print-divergence.ll
M llvm/test/CodeGen/AMDGPU/sub64-low-32-bits-known-zero.ll
A llvm/test/CodeGen/AMDGPU/uniform-vgpr-to-sgpr-return.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
Log Message:
-----------
[AMDGPU] Insert readfirstlane in the function returns in sgpr. (#135326)
insert `readfirstlane` in the function returns in sgpr.
Commit: f0a59c49aaa951a25bea57cf753a8eb1735fd810
https://github.com/llvm/llvm-project/commit/f0a59c49aaa951a25bea57cf753a8eb1735fd810
Author: Sarah Spall <sarahspall at microsoft.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/test/CodeGenHLSL/ArrayAssignable.hlsl
Log Message:
-----------
Revert "[HLSL] Make it possible to assign an array from a cbuffer" (#136576)
Reverts llvm/llvm-project#134174
Revert due to test error in hlsl/ArrayAssignable.hlsl breaking a lot of bots.
Commit: b95ec24ff08c6ffc300bd85c8b0e53dfda4bceef
https://github.com/llvm/llvm-project/commit/b95ec24ff08c6ffc300bd85c8b0e53dfda4bceef
Author: Jim Lin <jim at andestech.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
Log Message:
-----------
[SDAG] Handle insert_subvector in isKnownNeverNaN (#131989)
Propagate nnan across insert_subvector.
Commit: c17984711343c6cd16454431000b55627fc338eb
https://github.com/llvm/llvm-project/commit/c17984711343c6cd16454431000b55627fc338eb
Author: Bruno Cardoso Lopes <bruno.cardoso at gmail.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Dialect/LLVMIR/blockaddress-canonicalize.mlir
A mlir/test/Dialect/LLVMIR/indirectbr.mlir
M mlir/test/Target/LLVMIR/Import/import-failure.ll
A mlir/test/Target/LLVMIR/Import/indirectbr.ll
A mlir/test/Target/LLVMIR/indirectbr.mlir
M mlir/test/mlir-translate/import-diagnostics.ll
Log Message:
-----------
Reapply [MLIR][LLVM] Support for indirectbr (#136378)
Fix msan issue that caused revert in
https://github.com/llvm/llvm-project/pull/135695
### Original message
Now that LLVM dialect has `blockaddress` support, introduce
import/translation for `indirectbr` instruction.
Commit: f02b285dbd284057d5f1dd5fb599d1c2155670f5
https://github.com/llvm/llvm-project/commit/f02b285dbd284057d5f1dd5fb599d1c2155670f5
Author: Sarah Spall <sarahspall at microsoft.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/test/CodeGenHLSL/ArrayAssignable.hlsl
Log Message:
-----------
[HLSL] Reland; Make it possible to assign an array from a cbuffer (#136580)
Reland #134174
Update Sema Checking to always do an HLSL Array RValue cast in the case
we are dealing with hlsl constant array types
Instead of comparing canonical types, compare canonical unqualified
types
Add a test to show it is possible to assign an array from a cbuffer.
Closes https://github.com/llvm/llvm-project/issues/133767
Commit: 5739a22fbb593eb44490d23e0c8cc12386e4b5b6
https://github.com/llvm/llvm-project/commit/5739a22fbb593eb44490d23e0c8cc12386e4b5b6
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/blend-costs.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/debugloc.ll
M llvm/test/Transforms/LoopVectorize/dereferenceable-info-from-assumption-constant-size.ll
M llvm/test/Transforms/LoopVectorize/float-induction.ll
M llvm/test/Transforms/LoopVectorize/if-pred-stores.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/load-deref-pred-align.ll
M llvm/test/Transforms/LoopVectorize/load-of-struct-deref-pred.ll
M llvm/test/Transforms/LoopVectorize/loop-form.ll
M llvm/test/Transforms/LoopVectorize/select-cmp-multiuse.ll
M llvm/test/Transforms/LoopVectorize/select-cmp-predicated.ll
M llvm/test/Transforms/LoopVectorize/struct-return.ll
M llvm/test/Transforms/LoopVectorize/trip-count-expansion-may-introduce-ub.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing.ll
M llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll
Log Message:
-----------
[VPlan] Also duplicated scalar-steps when it enables sinking scalars. (#136021)
Extend sinking logic to duplicate scalar steps recipe if it enables
sinking, that is if all users in a destination block require all lanes.
This should be the last step before removing legacy sinkScalarOperands.
PR: https://github.com/llvm/llvm-project/pull/136021
Commit: d08e9800650b78fdd9cbed1375faa0f55e4ac09c
https://github.com/llvm/llvm-project/commit/d08e9800650b78fdd9cbed1375faa0f55e4ac09c
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M flang/lib/Optimizer/Transforms/CUFGPUToLLVMConversion.cpp
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/test/Fir/CUDA/cuda-gpu-launch-func.mlir
M flang/test/Fir/CUDA/cuda-launch.fir
Log Message:
-----------
[flang][cuda] Only convert launch from CUDA Fortran kernels (#136221)
Make sure `gpu.launch_func` has a CUDA proc attribute and update the
conversion pattern to only convert those with the attribute.
Commit: 3e5a9d9aa04e2c99601ffb6f65032a299a56069c
https://github.com/llvm/llvm-project/commit/3e5a9d9aa04e2c99601ffb6f65032a299a56069c
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Rename setFlags -> applyFlags (NFC).
Update name to apply flags to instructions, as suggested in
https://github.com/llvm/llvm-project/pull/135272.
Also changes the arg to a reference.
Commit: 1ab9e53e4910557f2a4c0f00c7a7f8b5ac493b48
https://github.com/llvm/llvm-project/commit/1ab9e53e4910557f2a4c0f00c7a7f8b5ac493b48
Author: Jason Molenda <jmolenda at apple.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp
Log Message:
-----------
[lldb][Mach-O corefiles] Don't init Target arch to corefile (#136065)
This patch is making three changes, when loading a Mach-O corefile:
1. At the start of `DoLoadCore`, if a binary was provided in addition to
the corefile, initialize the Target's ArchSpec.
2. Before ProcessMachCore does its "exhaustive search" fallback, looking
through the corefile contents for a userland dyld or mach kernel, we
must make sure the Target has an ArchSpec, or methods that check the
address word size, or initialize a DataExtractor based on the Target
arch will not succeed.
3. Add logging when setting the Target's arch listing exactly what that
setting was based on -- the corefile itself, or the main binary.
Jonas landed a change last August (started with a patch from me) which
removed the Target ArchSpec initialization at the start of DoLoadCore,
in a scenario where the corefile had arch armv7 and the main binary had
arch armv7em (Cortex-M), and there was python code in the main binary's
dSYM which sets the operating system threads provider based on the
Target arch. It did different things for armv7 or armv7em, and so it
would fail.
Jonas' patch removed any ArchSpec setting at the start of DoLoadCore, so
we wouldn't have an incorrect arch value, but that broke the exhaustive
search for kernel binaries, because we didn't have an address word size
or endianness.
This patch should navigate the needs of both use cases.
I spent a good bit of time trying to construct a test to capture all of
these requirements -- but it turns out to be a good bit difficult,
encompassing both a genuine kernel corefiles and a microcontroller
firmware corefiles.
rdar://146821929
Commit: 846986f35b5a7baa498db7c61ae15dd9b2dee797
https://github.com/llvm/llvm-project/commit/846986f35b5a7baa498db7c61ae15dd9b2dee797
Author: Petr Hosek <phosek at google.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M clang/cmake/caches/Fuchsia-stage2.cmake
Log Message:
-----------
[Fuchsia] Disable PIC (#136376)
We aren't distributing any shared libraries so we don't need PIC and
using PIE instead of PIC can improve performance.
Commit: 3d14596ccfa3aa6b0735a630e3efb575a2085a06
https://github.com/llvm/llvm-project/commit/3d14596ccfa3aa6b0735a630e3efb575a2085a06
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
Log Message:
-----------
[CIR][NFC] Fix an unused variable warning (#136431)
This fixes a warning where a variable assigned in 'if' statement wasn't
referenced again.
Commit: 09006611151c7f85862a9da8da34872c456c2c37
https://github.com/llvm/llvm-project/commit/09006611151c7f85862a9da8da34872c456c2c37
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M clang/include/clang/Frontend/CompilerInstance.h
M clang/lib/Frontend/CompilerInstance.cpp
Log Message:
-----------
[clang] Enable making `CompilerInstance` VFS thread-safe (#135737)
The `llvm::vfs::FileSystem` interface makes no promises around
thread-safety. To enable making `CompilerInstance` thread-safe, this PR
allows passing an explicit VFS to `cloneForModuleCompile()`. This will
be used from the dependency scanner.
Commit: 4c0ea476c40f7e426c84c37aaf5787aa80fb5e3b
https://github.com/llvm/llvm-project/commit/4c0ea476c40f7e426c84c37aaf5787aa80fb5e3b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Report error if Zilsd is used on RV64. (#136577)
Fixes #136564.
Commit: 9968ba8652b8a2936858a1a307207a9c8690ee5c
https://github.com/llvm/llvm-project/commit/9968ba8652b8a2936858a1a307207a9c8690ee5c
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/add64-low-32-bits-known-zero.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/constrained-shift.ll
M llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll
M llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/ptrmask.ll
M llvm/test/CodeGen/AMDGPU/sdag-print-divergence.ll
M llvm/test/CodeGen/AMDGPU/sub64-low-32-bits-known-zero.ll
R llvm/test/CodeGen/AMDGPU/uniform-vgpr-to-sgpr-return.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
Log Message:
-----------
Revert "[AMDGPU] Insert readfirstlane in the function returns in sgpr. (#135326)"
This reverts commit 76ced7fa782f0d7db9efea871fa6de74706dd9cc since it breaks a
lot of bots.
Commit: c873ca25976d81f54421d9f4e24c5f700824d0d1
https://github.com/llvm/llvm-project/commit/c873ca25976d81f54421d9f4e24c5f700824d0d1
Author: royitaqi <royitaqi at users.noreply.github.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M lldb/include/lldb/Target/Statistics.h
M lldb/source/Target/Statistics.cpp
M lldb/test/API/commands/statistics/basic/TestStats.py
Log Message:
-----------
[lldb] Add symbol/table count into statistics (#136226)
# New stats
The following stats are added and are available in both "statistics
dump" command and in python API.
1. In summary:
1. Add `totalSymbolsLoaded`. The total number of symbols loaded in all
modules.
2. Add `totalSymbolTablesLoaded `. The total number symbol tables loaded
in all modules.
2. In each module's stats:
1. Add `symbolsLoaded`. The number of symbols loaded in the current
module.
# Example
Example `statistics dump` output:
```
(lldb) statistics dump
{
...,
"modules": [
{
"path": "/Users/<username>/demo/simple/a.out",
"symbolsLoaded": 6,
...
},
...
],
...
"totalSymbolTablesLoaded": 42,
"totalSymbolsLoaded": 32198
}
```
# Tests
**Manual test**: Built and ran lldb on a helloworld program. Ran
`statistics dump`. Verified the above stats.
**Unit test**: Ran the following tests:
```
$ bin/lldb-dotest -p TestStats.py ~/llvm-sand/external/llvm-project/lldb/test/API/commands/statistics/basic/
...
Ran 18 tests in 192.676s
OK (skipped=3)
```
Commit: e0c1e23b99e9719d0a01ab7dfc0807d891004bd4
https://github.com/llvm/llvm-project/commit/e0c1e23b99e9719d0a01ab7dfc0807d891004bd4
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
M llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/BPF/BPFTargetTransformInfo.h
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
M llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
Log Message:
-----------
[TTI] Constify BasicTTIImplBase::thisT() (NFCI) (#136575)
The main change is making `thisT` method `const`, the rest of the
changes is fixing compilation errors (*).
(*) There are two tricky methods, `getVectorInstrCost()` and
`getIntImmCost()`.
They have several overloads; some of these overloads are typically
pulled in to derived classes using the `using` directive, and then
hidden by methods in the derived class.
The compiler does not complain if the hiding methods are not marked as
`const`, which means that clients will use the methods from the base
class. If after this change your target fails cost model tests, this
must be the reason. To resolve the issue you need to make all hiding
overloads `const`. See the second commit in this PR.
Pull Request: https://github.com/llvm/llvm-project/pull/136575
Commit: 0ae9dac262afccea1e1a2e02520f737ab38b286c
https://github.com/llvm/llvm-project/commit/0ae9dac262afccea1e1a2e02520f737ab38b286c
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M clang/test/CIR/CodeGenOpenACC/kernels.c
M clang/test/CIR/CodeGenOpenACC/parallel.c
Log Message:
-----------
[OpenACC][CIR] Lower 'num_workers' for parallel/kernels (#136578)
This patch also includes the first one to handle 'device_type' properly,
which is where most of the 'challenge' here comes from.
>From the best I can tell: we must keep two lists of the same size, 1 of
all of the 'num_workers' items, and 1 of the 'device_type' value for
that 'num_workers'. Additionally, the 'device_type' list can only handle
single 'device_type' values, so we have to duplicate the 'num_workers'
items in cases where there are multiple applicable 'device_type' values.
This patch accomplishes this by keeping the two in sync, and saving the
current 'device_type' in the visitor.
Commit: 4b98955680e0aad33cad0e810f1daaa8bc7c0a23
https://github.com/llvm/llvm-project/commit/4b98955680e0aad33cad0e810f1daaa8bc7c0a23
Author: erichkeane <ekeane at nvidia.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
Log Message:
-----------
Fix capitalization re review from 0ae9dac
Commit: 99e4b3927c5b8700b818ca2436f3c8394245e97c
https://github.com/llvm/llvm-project/commit/99e4b3927c5b8700b818ca2436f3c8394245e97c
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/include/llvm/Analysis/LazyBlockFrequencyInfo.h
M llvm/include/llvm/InitializePasses.h
M llvm/lib/Analysis/AliasAnalysis.cpp
M llvm/lib/Analysis/Analysis.cpp
M llvm/lib/Analysis/AssumptionCache.cpp
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/BlockFrequencyInfo.cpp
M llvm/lib/Analysis/BranchProbabilityInfo.cpp
M llvm/lib/Analysis/CallGraph.cpp
M llvm/lib/Analysis/CycleAnalysis.cpp
M llvm/lib/Analysis/DXILMetadataAnalysis.cpp
M llvm/lib/Analysis/DXILResource.cpp
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/lib/Analysis/DomPrinter.cpp
M llvm/lib/Analysis/DominanceFrontier.cpp
M llvm/lib/Analysis/GlobalsModRef.cpp
M llvm/lib/Analysis/IRSimilarityIdentifier.cpp
M llvm/lib/Analysis/IVUsers.cpp
M llvm/lib/Analysis/LazyBlockFrequencyInfo.cpp
M llvm/lib/Analysis/LazyValueInfo.cpp
M llvm/lib/Analysis/LoopInfo.cpp
M llvm/lib/Analysis/LoopPass.cpp
M llvm/lib/Analysis/MemoryDependenceAnalysis.cpp
M llvm/lib/Analysis/MemorySSA.cpp
M llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
M llvm/lib/Analysis/OptimizationRemarkEmitter.cpp
M llvm/lib/Analysis/PhiValues.cpp
M llvm/lib/Analysis/PostDominators.cpp
M llvm/lib/Analysis/ProfileSummaryInfo.cpp
M llvm/lib/Analysis/RegionInfo.cpp
M llvm/lib/Analysis/RegionPrinter.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp
M llvm/lib/Analysis/ScopedNoAliasAA.cpp
M llvm/lib/Analysis/StackSafetyAnalysis.cpp
M llvm/lib/Analysis/StaticDataProfileInfo.cpp
M llvm/lib/Analysis/TargetLibraryInfo.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/TypeBasedAliasAnalysis.cpp
M llvm/lib/Analysis/UniformityAnalysis.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
Log Message:
-----------
[LLVM] Cleanup pass initialization for Analysis passes (#135858)
- Do not call pass initialization from pass constructors.
- Instead, pass initialization should happen in the `initializeAnalysis`
function.
- https://github.com/llvm/llvm-project/issues/111767
Commit: b7c521b922f8b81544ecb0ccff2847644cac3107
https://github.com/llvm/llvm-project/commit/b7c521b922f8b81544ecb0ccff2847644cac3107
Author: erichkeane <ekeane at nvidia.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M clang/test/CIR/CodeGenOpenACC/kernels.c
M clang/test/CIR/CodeGenOpenACC/parallel.c
Log Message:
-----------
[OpenACC][CIR] Lowering for 'vector_length' on compute constructs
This is the same as the 'num_workers', with slightly different names in
places, so we just do the same exact implementation. This extracts the
implementation as well, which should make it easier to reuse.
Commit: 1b4919d0824411ab1a4fb055b22532fd466541f7
https://github.com/llvm/llvm-project/commit/1b4919d0824411ab1a4fb055b22532fd466541f7
Author: Nico Weber <thakis at chromium.org>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/AArch64/Disassembler/BUILD.gn
Log Message:
-----------
[gn] port e1bb7f6ddec375
Commit: 8c83355d5baa6ecbb5884240df195826380ed952
https://github.com/llvm/llvm-project/commit/8c83355d5baa6ecbb5884240df195826380ed952
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Handle VPIRPhi in VPRecipeBase::isPhi (NFC).
Also handle VPIRPhi in VPRecipeBase::isPhi, to simplify existing code
dealing with VPIRPhis.
Suggested as part of https://github.com/llvm/llvm-project/pull/136455.
Commit: c1049e42a1beab9b240cec80418b3ce32c9da03e
https://github.com/llvm/llvm-project/commit/c1049e42a1beab9b240cec80418b3ce32c9da03e
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
Log Message:
-----------
[AMDGPU] Correct VOP3P encoding. NFC. (#136005)
VOP3P encoding field was defined as 9 bit in GFX8/GFX9 and opcode
was 7 bit, while it is 8 and 8 since GFX10. There are no changes
to instructions, but it fixes difference with SP3 in terms of
fields breakdown.
Commit: 56bf0e720288ae6ba6e8635c7ec12f1e7d6f783b
https://github.com/llvm/llvm-project/commit/56bf0e720288ae6ba6e8635c7ec12f1e7d6f783b
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M offload/DeviceRTL/CMakeLists.txt
M offload/DeviceRTL/src/Kernel.cpp
M offload/DeviceRTL/src/Mapping.cpp
M offload/include/Shared/Environment.h
Log Message:
-----------
[OpenMP] Remove dependency on LLVM include directory from DeviceRTL (#136359)
Summary:
Currently we depend on a single LLVM include directory. This is actually
only required to define one enum, which is highly unlikely to change.
THis patch makes the `Environment.h` include directory more hermetic so
we no long depend on other libraries. In exchange, we get a simpler
dependency list for the price of hard-coding `1` somewhere. I think it's
a valid trade considering that this flag is highly unlikely to change at
this point.
@ronlieb AMD version
https://gist.github.com/jhuber6/3313e6f957be14dc79fe85e5126d2cb3
Commit: 863ead29e92de800fe50e56958b6eba6ede023e9
https://github.com/llvm/llvm-project/commit/863ead29e92de800fe50e56958b6eba6ede023e9
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
A utils/bazel/llvm-project-overlay/libc/test/include/BUILD.bazel
Log Message:
-----------
[libc][bazel] Add a helper library with all deps of generated headers. (#136582)
Create "public_header_deps" that is a convenient way to express
dependencies of a generated headers as a single (and same) target. It's
also convenient to use it in unit tests - which is also demonstrated in
this PR by adding the BUILD.bazel placeholder for test/include unit
tests, and creating a libc_test target for one of these tests.
See issue #134780.
Commit: 704fc6542cf171c603bd387663a2de3a3fa9c4ff
https://github.com/llvm/llvm-project/commit/704fc6542cf171c603bd387663a2de3a3fa9c4ff
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Log Message:
-----------
[SelectionDAG] Prefer to use ATOMIC_LOAD extension type over getExtendForAtomicOps() in computeKnownBits/ComputeNumSignBits. (#136600)
If an ATOMIC_LOAD has ZEXTLOAD/SEXTLOAD extension type we should trust
that over getExtendForAtomicOps().
SystemZ is the only target that uses setAtomicLoadExtAction and they
return ANY_EXTEND from getExtendForAtomicOps(). So I'm not sure there's
a way to get a contradiction currently.
Note, type legalization uses getExtendForAtomicOps() when promoting
ATOMIC_LOAD so we may not need to check getExtendForAtomicOps() for
ATOMIC_LOAD. I have not done much investigating of this.
Commit: aa5cdc0600ac8157a80f54fa2555ae7dfd5fc520
https://github.com/llvm/llvm-project/commit/aa5cdc0600ac8157a80f54fa2555ae7dfd5fc520
Author: Thurston Dang <thurston at google.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
A llvm/test/Instrumentation/MemorySanitizer/X86/avx512fp16-arith-intrinsics.ll
A llvm/test/Instrumentation/MemorySanitizer/X86/avx512fp16-arith-vl-intrinsics.ll
A llvm/test/Instrumentation/MemorySanitizer/X86/avx512fp16-intrinsics.ll
Log Message:
-----------
[msan][NFCI] Add avx512fp16-{arith-intrinsics, arith-vl-intrinsics, intrinsics} tests (#136260)
Forked from llvm/test/CodeGen/X86/avx512fp16-{arith-intrinsics,
arith-vl-intrinsics, intrinsics}.ll
The tests show that many instructions are handled suboptimally or
heuristically, but this commit message is too narrow to contain them.
Commit: 1e803770a5a0d7e5a12511f6d505b779a1931724
https://github.com/llvm/llvm-project/commit/1e803770a5a0d7e5a12511f6d505b779a1931724
Author: lexi-nadia <me at lexibromfield.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/python/BUILD.bazel
Log Message:
-----------
[mlir][SMT] update Bazel configuration to match 697aa99 (#136616)
Update Bazel configuration to match
697aa9995c24a977425e672d76a4a434384b16e3.
Commit: a27f7ac5c4e44b495f52e8d77b68a164dd833fda
https://github.com/llvm/llvm-project/commit/a27f7ac5c4e44b495f52e8d77b68a164dd833fda
Author: gulfemsavrun <gulfem at google.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M clang/cmake/caches/Fuchsia-stage2.cmake
Log Message:
-----------
Revert "[Fuchsia] Disable PIC" (#136617)
Reverts llvm/llvm-project#136376 because it broke Fuchsia Clang
toolchain builders.
Commit: a945f5917cb01350487999b24b068e18111bfbfe
https://github.com/llvm/llvm-project/commit/a945f5917cb01350487999b24b068e18111bfbfe
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
R llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.fpmath.ll
A llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.path.ll
Log Message:
-----------
AMDGPU: Add global-isel checks and rename fptrunc.v2f16.fpmath.ll (#136609)
Also remove the checks with -enable-unsafe-fp-math (already in fptrunc.f16.ll)
Commit: 3ceb3d96ff166305f015f1f00b2740e148347532
https://github.com/llvm/llvm-project/commit/3ceb3d96ff166305f015f1f00b2740e148347532
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M flang/lib/Semantics/check-acc-structure.cpp
M flang/test/Semantics/OpenACC/acc-kernels.f90
M flang/test/Semantics/OpenACC/acc-parallel.f90
M flang/test/Semantics/OpenACC/acc-serial.f90
M llvm/include/llvm/Frontend/OpenACC/ACC.td
Log Message:
-----------
[flang][openacc] Make async clause behavior homogenous (#136610)
The `async` clause was not handed in a similar way on `serial`,
`parallel` and `kernels` directive. This patches updates the `ACC.td`
file and the flang semantic to make it homogenous.
Commit: 515564aa6ebeadc06eea03ff92aeda64727f1da5
https://github.com/llvm/llvm-project/commit/515564aa6ebeadc06eea03ff92aeda64727f1da5
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
Log Message:
-----------
[AMDGPU] Partially revert my llvm::less_second patch (#136615)
This patch partially reverts:
commit 5e1b0f97735083b6762834b83fdbb35e76002e03
Author: Kazu Hirata <kazu at google.com>
Date: Fri Apr 18 10:05:55 2025 -0700
to fix:
LLVM :: CodeGen/AMDGPU/sched-group-barrier-pipeline-solver.mir
LLVM :: CodeGen/AMDGPU/sched-group-barrier-pre-RA.mir
under LLVM_ENABLE_EXPENSIVE_CHECKS.
Commit: de0153da325b21340747d8a064906a8c1c2f95ea
https://github.com/llvm/llvm-project/commit/de0153da325b21340747d8a064906a8c1c2f95ea
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinHeaders.def
M clang/include/clang/Basic/BuiltinsAArch64.def
M clang/include/clang/Basic/BuiltinsARM.def
M clang/lib/Headers/arm_acle.h
M clang/lib/Sema/SemaARM.cpp
A clang/test/CodeGen/arm-former-microsoft-intrinsics-header-warning.c
A clang/test/CodeGen/arm-former-microsoft-intrinsics.c
M clang/test/CodeGen/arm-microsoft-intrinsics.c
A clang/test/CodeGen/arm64-former-microsoft-intrinsics-header-warning.c
A clang/test/CodeGen/arm64-former-microsoft-intrinsics.c
M clang/test/CodeGen/arm64-microsoft-intrinsics.c
M clang/test/CodeGen/builtins-arm-microsoft.c
M clang/test/Headers/Inputs/include/stdint.h
M clang/test/Headers/ms-intrin.cpp
Log Message:
-----------
[clang][ARM][AArch64] Define intrinsics guarded by __has_builtin on all platforms (#128222)
Instead of defining ARM ACLE intrinsics only on MSVC and guarding
wrapper functions in headers with `__has_builtin`, universally define
the intrinsics as target header builtins.
---------
Signed-off-by: Sarnie, Nick <nick.sarnie at intel.com>
Commit: 7810d8484413ae64029c93f8dfc43f77b0ba98c3
https://github.com/llvm/llvm-project/commit/7810d8484413ae64029c93f8dfc43f77b0ba98c3
Author: Sarah Spall <sarahspall at microsoft.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M clang/lib/CodeGen/Targets/DirectX.cpp
M clang/test/CodeGenHLSL/builtins/AppendStructuredBuffer-elementtype.hlsl
M clang/test/CodeGenHLSL/builtins/ConsumeStructuredBuffer-elementtype.hlsl
M clang/test/CodeGenHLSL/builtins/RWStructuredBuffer-elementtype.hlsl
M clang/test/CodeGenHLSL/builtins/StructuredBuffer-elementtype.hlsl
Log Message:
-----------
[HLSL] Boolean in a RawBuffer should be i32 and Boolean vector in a RawBuffer should be <N x i32> (#135848)
Instead of converting the type in a RawBuffer to its HLSL type using
'ConvertType', use 'ConvertTypeForMem'.
ConvertTypeForMem handles booleans being i32 and boolean vectors being <
N x i32 >.
Add tests to show booleans and boolean vectors in RawBuffers now have
the correct type of i32, and <N x i32> respectively.
Closes #135635
Commit: 8389d6fad76bd880f02bddce7f0f2612ff0afc40
https://github.com/llvm/llvm-project/commit/8389d6fad76bd880f02bddce7f0f2612ff0afc40
Author: Pranav Kant <prka at google.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M lld/ELF/ICF.cpp
M lld/ELF/SymbolTable.cpp
M lld/ELF/SymbolTable.h
A lld/test/ELF/aarch64-got-merging-icf.s
M lld/test/ELF/icf-preemptible.s
Log Message:
-----------
[lld] Merge equivalent symbols found during ICF (#134342)
Fixes a correctness issue for AArch64 when ADRP and LDR instructions are
outlined in separate sections and sections are fed to ICF for
deduplication.
See test case (based on
https://github.com/llvm/llvm-project/issues/129122) for details. All
rodata.* sections are folded into a single section with ICF. This leads
to all f2_* function sections getting folded into one (as their
relocation target symbols g* belong to .rodata.g* sections that have
already been folded into one). Since relocations still refer original g*
symbols, we end up creating duplicate GOT entry for all such symbols.
This PR addresses that by tracking such folded symbols and create one
GOT entry for all such symbols.
Fixes https://github.com/llvm/llvm-project/issues/129122
Co-authored by: @jyknight
Commit: 92c0b425ad4ca7f4c9b8f7f663e6e64d1e070353
https://github.com/llvm/llvm-project/commit/92c0b425ad4ca7f4c9b8f7f663e6e64d1e070353
Author: Princeton Ferro <pferro at nvidia.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
A llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
Log Message:
-----------
[NVPTX] add test case for vector reduction intrinsics (#136381)
Test how these intrinsics are handled by the NVPTX backend. Currently, these intrinsics are lowered to sequential reductions by the ExpandReductions pass.
Commit: 6d765e1c916aba7a038f5ace963001fca4fc9314
https://github.com/llvm/llvm-project/commit/6d765e1c916aba7a038f5ace963001fca4fc9314
Author: Owen Anderson <resistor at mac.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang-tools-extra/clangd/unittests/InlayHintTests.cpp
M clang/lib/AST/Decl.cpp
M clang/unittests/AST/AttrTest.cpp
Log Message:
-----------
Reapply 19c708c "FunctionDecl::getFunctionTypeLoc: ignore function type attributes (#118420)" (#136484)
Avoid using PreservesMost in the testcase as it is not supported on all
targets.
Original PR #118290.
Co-authored-by: Robert Dazi <14996868+v01dXYZ at users.noreply.github.com>
Co-authored-by: v01dxyz <v01dxyz at v01d.xyz>
Commit: 3ca2fa704e149ca22bd9739101ee7d5c498eb1a6
https://github.com/llvm/llvm-project/commit/3ca2fa704e149ca22bd9739101ee7d5c498eb1a6
Author: Theo de Magalhaes <theodemagalhaes at icloud.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M clang/lib/AST/RecordLayoutBuilder.cpp
M clang/test/SemaCXX/windows-Wpadded-bitfield.cpp
Log Message:
-----------
[CLANG][MS-STRUCT] bitfield padding warning presents padding to exact bit count (#136062)
Aims to fix #131647.
Commit: c40d3a411ce3f0a35ae4f3d2f0e1e7df45673856
https://github.com/llvm/llvm-project/commit/c40d3a411ce3f0a35ae4f3d2f0e1e7df45673856
Author: Maryam Moghadas <maryammo at ca.ibm.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsPowerPC.td
M llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
M llvm/test/CodeGen/PowerPC/dmf-outer-product.ll
M llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
M llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
M llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
Log Message:
-----------
[PowerPC] Add dense math bfloat16 floating-point outer-product accumulate to DMR instructions (#133109)
This patch adds the following Dense Math Facility bfloat16
floating-point calculation instructions: dmxvbf16gerx2,
dmxvbf16gerx2pp,dmxvbf16gerx2pn, dmxvbf16gerx2np, dmxvbf16gerx2nn,
pmdmxvbf16gerx2, pmdmxvbf16gerx2pp, pmdmxvbf16gerx2pn,
pmdmxvbf16gerx2np, pmdmxvbf16gerx2nn, along with their corresponding
intrinsics and tests.
Commit: 56910a8b1b302ebf37e9d30bd200091fd23dc232
https://github.com/llvm/llvm-project/commit/56910a8b1b302ebf37e9d30bd200091fd23dc232
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.h
M llvm/test/CodeGen/NVPTX/bug21465.ll
M llvm/test/CodeGen/NVPTX/forward-ld-param.ll
M llvm/test/CodeGen/NVPTX/lower-args-gridconstant.ll
M llvm/test/CodeGen/NVPTX/lower-args.ll
M llvm/test/CodeGen/NVPTX/lower-byval-args.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/nvptx-basic.ll.expected
Log Message:
-----------
[NVPTX] Improve kernel byval parameter lowering (#136008)
This change introduces a new pattern for lowering kernel byval
parameters in `NVPTXLowerArgs`. Each byval argument is wrapped in a call
to a new intrinsic, `@llvm.nvvm.internal.addrspace.wrap`. This intrinsic
explicitly equates to no instructions and is removed during operation
legalization in SDAG. However, it allows us to change the addrspace of
the arguments to 101 to reflect the fact that they will occupy this
space when lowered by `LowerFormalArgs` in `NVPTXISelLowering`.
Optionally, if a generic pointer to a param is needed, a standard
`addrspacecast` is used. This approach offers several advantages:
- Exposes addrspace optimizations: By using a standard `addrspacecast`
back to generic space we allow InferAS to optimize this instruction,
potentially sinking it through control flow or in other ways unsupported
by `NVPTXLowerArgs`. This is demonstrated in several existing tests.
- Clearer, more consistent semantics: Previously an `addrspacecast` from
generic to param space was implicitly a no-op. This is problematic
because it's not reciprocal with the inverse cast, violating LLVM
semantics. Further it is very confusing given the existence of
`cvta.to.param`. After this change the cast equates to this instruction.
- Allow for the removal of all nvvm.ptr.* intrinsics: In a follow-up
change the nvvm.ptr.gen.to.param and nvvm.ptr.param.to.gen intrinsics
may be removed.
Commit: e79d8f6892aa138bfef65334817c24d3d9881855
https://github.com/llvm/llvm-project/commit/e79d8f6892aa138bfef65334817c24d3d9881855
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M flang/include/flang/Lower/DirectivesCommon.h
M flang/include/flang/Optimizer/Builder/DirectivesCommon.h
M flang/lib/Lower/OpenACC.cpp
M flang/test/Lower/OpenACC/acc-bounds.f90
M flang/test/Lower/OpenACC/acc-enter-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-enter-data.f90
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
Log Message:
-----------
[flang][acc] Update stride calculation to include inner-dimensions (#136613)
The acc.bounds operation allows specifying stride - but it did not
clarify what it meant. The dialect was updated to specifically note that
stride must capture inner dimension sizes when specified for outer
dimensions.
Flang lowering was also updated for OpenACC to adhere to this. This was
already the case for descriptor-based arrays - but now this is also
being done for all arrays.
Commit: 53e62c654a3fe181686f1ccd960d2e2b981e4313
https://github.com/llvm/llvm-project/commit/53e62c654a3fe181686f1ccd960d2e2b981e4313
Author: Hubert Tong <hubert.reinterpretcast at gmail.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M compiler-rt/test/profile/AIX/pgo-lto-bcdtor-function-section.test
Log Message:
-----------
[compiler-rt][profile][tests][NFC] Avoid using a.out from PATH (#136465)
Fix use of `a.out` from the PATH by specifying `./a.out`.
Commit: d2fedd67debf011cec7465e0c7ac330dfb548b72
https://github.com/llvm/llvm-project/commit/d2fedd67debf011cec7465e0c7ac330dfb548b72
Author: Augie Fackler <augie at google.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp
Log Message:
-----------
[NVPTX] mark unused variable introduced by 56910a8b1b302ebf37e9d30bd200091fd23dc232 [NFC]
Commit: d1f4f52aa6f2276da8880b5003f220ce6211ad44
https://github.com/llvm/llvm-project/commit/d1f4f52aa6f2276da8880b5003f220ce6211ad44
Author: Thurston Dang <thurston at google.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512fp16-arith-intrinsics.ll
Log Message:
-----------
[msan] Handle x86.avx512fp16.{add,sub.mul,div,min,max}.ph.512 (#136619)
These are handled similarly to x86_avx512_(min|max)_p[sd]_512 intrinsics
(https://github.com/llvm/llvm-project/pull/124421) i.e., using
maybeHandleSimpleNomemIntrinsic, with the last parameter being the
rounding method.
Updates the test from https://github.com/llvm/llvm-project/pull/136260
Commit: d5b40c71f6be972f677de5d9886f91866df007b5
https://github.com/llvm/llvm-project/commit/d5b40c71f6be972f677de5d9886f91866df007b5
Author: royitaqi <royitaqi at users.noreply.github.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M lldb/include/lldb/Symbol/ObjectFile.h
M lldb/include/lldb/Symbol/SymbolFile.h
M lldb/include/lldb/Symbol/SymbolFileOnDemand.h
M lldb/source/Core/Module.cpp
M lldb/source/Symbol/ObjectFile.cpp
M lldb/source/Symbol/SymbolFile.cpp
M lldb/test/API/commands/statistics/basic/TestStats.py
M lldb/unittests/Symbol/LineTableTest.cpp
M lldb/unittests/Symbol/SymtabTest.cpp
Log Message:
-----------
[lldb] Avoid force loading symbols in statistics collection (#136236)
Currently, `DebuggerStats::ReportStatistics()` calls
`Module::GetSymtab(/*can_create=*/false)`, but then the latter calls
`SymbolFile::GetSymtab()`. This will load symbols if haven't yet. See
stacktrace below.
The problem is that `DebuggerStats::ReportStatistics` should be
read-only. This is especially important because it reports stats for
symtab parsing/indexing time, which could be affected by the reporting
itself if it's not read-only.
This patch fixes this problem by adding an optional parameter
`SymbolFile::GetSymtab(bool can_create = true)` and receive the `false`
value passed down from `Module::GetSymtab(/*can_create=*/false)` when
the call was initiated from `DebuggerStats::ReportStatistics()`.
Commit: a1db2c64918efa3d74dfdb402b8cff30bc555521
https://github.com/llvm/llvm-project/commit/a1db2c64918efa3d74dfdb402b8cff30bc555521
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
Log Message:
-----------
[RISCV] Remove duplicate call to MFI.getStackID(FI). NFC
Reuse existing local variable.
Commit: 2cdf474f12090919e5b14c6ef922e5d5df407418
https://github.com/llvm/llvm-project/commit/2cdf474f12090919e5b14c6ef922e5d5df407418
Author: Teresa Johnson <tejohnson at google.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
A llvm/test/Transforms/MemProfContextDisambiguation/mergenodes.ll
A llvm/test/Transforms/MemProfContextDisambiguation/mergenodes2.ll
M llvm/test/Transforms/MemProfContextDisambiguation/overlapping-contexts.ll
Log Message:
-----------
[MemProf] Merge callee clones as needed before assigning functions (#135702)
We perform cloning for each allocation node separately. However, this
sometimes results in a situation where the same node calls multiple
clones of the same callee, created for different allocations. This
causes issues when assigning functions to these clones, as each node can
in reality only call a single callee clone.
To address this, before assigning functions, merge callee clone nodes as
needed using a post order traversal from the allocations. We attempt to
use existing clones as the merge node when legal, and to share them
among callers with the same properties (callers calling the same set of
callee clone nodes for the same allocations).
Without this fix, in some cases incorrect function assignment will lead
to calling the wrong allocation clone. In fact, this showed up in an
existing test, that I didn't notice as it existed to test earlier parts
of the cloning process.
Commit: 08b4c52540727455194b0cf0f6310f391e87c2a5
https://github.com/llvm/llvm-project/commit/08b4c52540727455194b0cf0f6310f391e87c2a5
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M lldb/include/lldb/Symbol/ObjectFile.h
M lldb/include/lldb/Symbol/SymbolFile.h
M lldb/include/lldb/Symbol/SymbolFileOnDemand.h
M lldb/source/Core/Module.cpp
M lldb/source/Symbol/ObjectFile.cpp
M lldb/source/Symbol/SymbolFile.cpp
M lldb/test/API/commands/statistics/basic/TestStats.py
M lldb/unittests/Symbol/LineTableTest.cpp
M lldb/unittests/Symbol/SymtabTest.cpp
Log Message:
-----------
Revert "[lldb] Avoid force loading symbols in statistics collection (#136236)"
This reverts commit d5b40c71f6be972f677de5d9886f91866df007b5.
This change broke greendragon lldb test:
lldb-api :: commands/statistics/basic/TestStats.py
And is therefore being reverted.
Commit: 2b44eb9f56a51a25391319541de750bb9b5c1fc9
https://github.com/llvm/llvm-project/commit/2b44eb9f56a51a25391319541de750bb9b5c1fc9
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/test/TableGen/VarLenDecoder.td
Log Message:
-----------
[LLVM][TableGen] Fix VarlenDecoder.td to not used fixed opcode values (#136632)
Commit: c7ea01b8a0382c21da1f64a9bf077c951096db8e
https://github.com/llvm/llvm-project/commit/c7ea01b8a0382c21da1f64a9bf077c951096db8e
Author: Peter Collingbourne <peter at pcc.me.uk>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
M llvm/test/Transforms/LowerTypeTests/aarch64-jumptable.ll
M llvm/test/Transforms/LowerTypeTests/cfi-direct-call1.ll
M llvm/test/Transforms/LowerTypeTests/function-arm-thumb.ll
M llvm/test/Transforms/LowerTypeTests/function-thumb-bti.ll
M llvm/test/Transforms/LowerTypeTests/function.ll
M llvm/test/Transforms/LowerTypeTests/x86-jumptable.ll
M llvm/test/Transforms/MergeFunc/cfi-thunk-merging.ll
Log Message:
-----------
LowerTypeTests: Switch to emitting one inline asm call per jump table entry.
With the previous approach of emitting one inline asm call for all jump
table entries we would encounter SelectionDAG's limit on the number
of operands per node (65536) when the number of jump table entries
exceeded that number. Fix the problem by switching to one inline asm
per jump table entry so that each DAG node only needs one operand.
Reviewers: fmayer, vitalybuka
Reviewed By: fmayer
Pull Request: https://github.com/llvm/llvm-project/pull/136265
Commit: 698cd48db9c2058442e5e6355a77e91e3456ec2c
https://github.com/llvm/llvm-project/commit/698cd48db9c2058442e5e6355a77e91e3456ec2c
Author: Jim Lin <jim at andestech.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
Log Message:
-----------
[RISCV] Fix Lsb > Msb case in (sra (sext_inreg X, _), C) for th.ext (#136287)
According the
[spec](https://github.com/XUANTIE-RV/thead-extension-spec/releases/tag/2.3.0),
the operation of `th.ext rd, rs1, msb, lsb` is
reg[rd] := sign_extend(reg[rs1][msb:lsb])
The spec doesn't specify if lsb is greater than msb.
I don't think lsb can be greater than msb. So that If the shift-right
amount is greater than msb, we can set lsb equal to msb to extract the
bit rs1[msb] and sign-extend it.
Commit: ddb8870a5f396f2f17462f878fb7c0cffc879ce4
https://github.com/llvm/llvm-project/commit/ddb8870a5f396f2f17462f878fb7c0cffc879ce4
Author: Jim Lin <jim at andestech.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
Log Message:
-----------
[RISCV] Remove the FIXME for using sraiw+and. NFC.
https://github.com/llvm/llvm-project/pull/102034 has implemented it.
Commit: 46e734746db7176f6e32b3c98beacf1e94fced37
https://github.com/llvm/llvm-project/commit/46e734746db7176f6e32b3c98beacf1e94fced37
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M flang/include/flang/Optimizer/Dialect/CUF/CUFOps.td
M flang/lib/Lower/Bridge.cpp
M flang/lib/Optimizer/Dialect/CUF/CUFOps.cpp
M flang/test/Lower/CUDA/cuda-kernel-loop-directive.cuf
Log Message:
-----------
[flang][cuda] Update stream type for cuf kernel op (#136627)
Update the type of the stream operand to be similar to KernelLaunchOp.
Commit: b144258b0c0cc63dffba00a911d6539f00ed07bb
https://github.com/llvm/llvm-project/commit/b144258b0c0cc63dffba00a911d6539f00ed07bb
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Parse/Parser.h
M clang/lib/Parse/ParseExpr.cpp
M clang/test/AST/ast-dump-recovery.cpp
M clang/test/AST/new-unknown-type.cpp
M clang/test/Parser/cxx-concepts-requires-clause.cpp
Log Message:
-----------
[Clang] Improve error recovery for invalid calls (#136295)
It doesn't make sense that we only build a RecoveryExpr for expressions
with invalid trailing commas. This patch extends it so that we now
always build up a RecoveryExpr whenever the call contains anything
invalid. As a result, we can back out HasTrailingComma.
There is only one diagnostic change as to concepts, where a RecoveryExpr
than an ExprError is now used to model an invalid requires clause, for
which we suggest adding parentheses around it. (This looks like what GCC
diagnoses)
Commit: 0014b49482c0862c140149c650d653b4e41fa9b4
https://github.com/llvm/llvm-project/commit/0014b49482c0862c140149c650d653b4e41fa9b4
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
M llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/BPF/BPFTargetTransformInfo.h
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.h
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
M llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h
M llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.cpp
M llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h
M llvm/lib/Target/Mips/MipsTargetTransformInfo.cpp
M llvm/lib/Target/Mips/MipsTargetTransformInfo.h
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SPIRV/SPIRVTargetTransformInfo.h
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
M llvm/lib/Target/VE/VETargetTransformInfo.h
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
Log Message:
-----------
[TTI] Make all interface methods const (NFCI) (#136598)
Making `TargetTransformInfo::Model::Impl` `const` makes sure all
interface methods are `const`, in `BasicTTIImpl`, its bases, and in all
derived classes.
Pull Request: https://github.com/llvm/llvm-project/pull/136598
Commit: 9e26c797ae9699fba8bd62af99ab3ad6f9b16462
https://github.com/llvm/llvm-project/commit/9e26c797ae9699fba8bd62af99ab3ad6f9b16462
Author: Liao Chunyu <chunyu at iscas.ac.cn>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.rst
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVSystemOperands.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/features-info.ll
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/test/MC/RISCV/machine-csr-names.s
M llvm/test/MC/RISCV/rv32-machine-csr-names.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Add smcntrpmf extension (#136556)
spec: https://github.com/riscvarchive/riscv-smcntrpmf
Commit: 497382ee07100f3698621fc48b66a0bd50a1ca2a
https://github.com/llvm/llvm-project/commit/497382ee07100f3698621fc48b66a0bd50a1ca2a
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Log Message:
-----------
[SelectionDAG] Make the FoldingSet profile in getAtomic match AddNodeIDCustom. (#136651)
In theory, the mismatch would have made CSE of AtomicSDNodes not work,
but I don't know how to test it.
Commit: 784dc16088885ebb28437ae2dbb90dcfd5df0457
https://github.com/llvm/llvm-project/commit/784dc16088885ebb28437ae2dbb90dcfd5df0457
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef][IR] Fix default AS documentation for allocas without explicit AS (#135942)
So far, the Language Reference said that the alloca address space from
the datalayout is used if no explicit address space is provided, which
is not what the LLParser and the AsmWriter implement. This patch adjusts
the documentation to match the implementation: The default AS 0 is used
if none is explicitly specified.
This is an alternative to PR #135786, which would change the parser's
behavior to match the Language Reference instead.
Commit: 53927ab726e6d0dfb3255498b6d0b130adeafb8c
https://github.com/llvm/llvm-project/commit/53927ab726e6d0dfb3255498b6d0b130adeafb8c
Author: Henrich Lauko <xlauko at mail.muni.cz>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
Log Message:
-----------
[CIR] Make ZeroAttr use AttrBuilderWithInferredContext (#136604)
This mirrors incubator changes from https://github.com/llvm/clangir/pull/1576
Commit: 0ca2d4d10451874b1d107e89c32eb7fd95e1a608
https://github.com/llvm/llvm-project/commit/0ca2d4d10451874b1d107e89c32eb7fd95e1a608
Author: Kirill Chibisov <contact at kchibisov.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/test/Dialect/EmitC/transforms.mlir
M mlir/test/Target/Cpp/expressions.mlir
Log Message:
-----------
[mlir][emitc] mark `emitc.load` with `CExpression` (#130802)
Follow the `call` and `call_opaque` operations, as well as `apply`,
which already are marked as `CExpression` even though they have side
effects.
Even though `emitc.load` can be included inside the `emitc.expression`,
the inlining and `--form-expression` pass won't actually inline them
inside other expression due to it having a side effect, thus unless the
user manually writes the `emitc.load` inside the `emitc.expression` it
won't appear there.
--
It was brought
https://github.com/llvm/llvm-project/pull/91475#issuecomment-2302529428
and while there was some opposition due to `load` having a side effect,
`emitc` already allows all the rest operations that have it, so for
consistency reasons, enabling it doesn't really hurt from my point of
view. Especially given that `--form-expression` doesn't allow
it to really inline inside other expressions, which makes sense, since
if the users want such behavior, they should explicitly opt-in.
Commit: 8639b365a5988932973a82ffe5e620a9c8ef9039
https://github.com/llvm/llvm-project/commit/8639b365a5988932973a82ffe5e620a9c8ef9039
Author: Henrich Lauko <xlauko at mail.muni.cz>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/lib/CIR/Dialect/IR/CIRMemorySlot.cpp
Log Message:
-----------
[CIR] Make UndefAttr use AttrBuilderWithInferredContext (#136605)
This mirrors incubator changes from https://github.com/llvm/clangir/pull/1577
Commit: 2d3bbb6aafbc74ef6fc51286f09def0f0e35fe14
https://github.com/llvm/llvm-project/commit/2d3bbb6aafbc74ef6fc51286f09def0f0e35fe14
Author: Matthias Springer <me at m-sp.org>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M mlir/include/mlir/IR/Builders.h
M mlir/lib/IR/Builders.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
Log Message:
-----------
[mlir][Transforms] Dialect conversion: Erase materialized constants instead of rollback (#136489)
When illegal (and not legalizable) constant operations are materialized
during a dialect conversion as part of op folding, these operations must
be deleted again. This used to be implemented via the rollback
mechanism. This commit switches the implementation to regular rewriter
API usage: simply delete the materialized constants with `eraseOp`.
This commit is in preparation of the One-Shot Dialect Conversion
refactoring, which will disallow IR rollbacks.
This commit also adds a new optional parameter to `OpBuilder::tryFold`
to get hold of the materialized constant ops.
Commit: 56f5bcb0350b8af44aa5f65ccf865a464df2cc4a
https://github.com/llvm/llvm-project/commit/56f5bcb0350b8af44aa5f65ccf865a464df2cc4a
Author: Henrich Lauko <xlauko at mail.muni.cz>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/Dialect/IR/CIRMemorySlot.cpp
Log Message:
-----------
[CIR] Let ConstantOp builder infer its type automatically (#136606)
This mirrors incubator changes from https://github.com/llvm/clangir/pull/1578
Commit: 8bc0d4d1ccb708d20413876258885a48d3ca6b3d
https://github.com/llvm/llvm-project/commit/8bc0d4d1ccb708d20413876258885a48d3ca6b3d
Author: Matthias Springer <me at m-sp.org>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/Transforms/Utils/DialectConversion.cpp
Log Message:
-----------
[mlir][Transforms] Dialect conversion: Add flag to disable rollback (#136490)
This commit adds a new flag to `ConversionConfig` to disallow the
rollback of IR modification. This commit is in preparation of the
One-Shot Dialect Conversion refactoring, which will remove the ability
to roll back IR modifications from the conversion driver.
RFC:
https://discourse.llvm.org/t/rfc-a-new-one-shot-dialect-conversion-driver/79083/46
By default, this flag is set to "true". I.e., the rollback of IR
modifications is allowed. When set to "false", the conversion driver
will report a fatal LLVM error when an IR rollback is requested. The
name of the rolled back pattern is included in the error message.
Moreover, the original IR is no longer restored after a failed
conversion.
Example:
```
within split at llvm-project/mlir/test/Conversion/ArithToSPIRV/fast-math.mlir:1 offset :11:8: error: pattern '(anonymous namespace)::CmpFOpNanKernelPattern' produced IR that could not be legalized
%0 = arith.cmpf ord, %arg0, %arg1 fastmath<fast> : f32
^
within split at llvm-project/mlir/test/Conversion/ArithToSPIRV/fast-math.mlir:1 offset :11:8: note: see current operation: %1 = "arith.cmpf"(%arg0, %arg1) <{fastmath = #arith.fastmath<fast>, predicate = 7 : i64}> : (f32, f32) -> i1
pattern '(anonymous namespace)::CmpFOpNanKernelPattern' rollback of IR modifications requested
UNREACHABLE executed at llvm-project/mlir/lib/Transforms/Utils/DialectConversion.cpp:1231!
```
The majority of patterns in MLIR have already been updated such that
they do not trigger any rollbacks, but a few SPIRV patterns remain. More
information in the RFC.
Commit: a22ad659cd0665669d89fae174f9e6a83d1a446d
https://github.com/llvm/llvm-project/commit/a22ad659cd0665669d89fae174f9e6a83d1a446d
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M lldb/include/lldb/Host/Config.h.cmake
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.h
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
Log Message:
-----------
[lldb/cmake] Normalize use of HAVE_LIBCOMPRESSION (#135528)
I *think* this was the reason behind the failures in
2fd860c1f559c0b0be66cc000e38270a04d0a1a3: the clang include tool showed
the Config.h headers as unused, and because the macro was referenced
through an `#ifdef`, its removal didn't cause build failures. Switching
to `#cmakedefine01` + `#if` should make sure this does not happen again.
According to D48977, the `#ifndef`+`#cmakedefine` patterns is due to
some files redefining the macro themselves. I no longer see any such
files in the source tree (there also were no files like that in the
source tree at the revision mentioned, but the macro *was* defined in
the hand-maintained XCode project we had at the time).
Commit: f541a3aad8e70b613ea411bf2d3e64a220f98e82
https://github.com/llvm/llvm-project/commit/f541a3aad8e70b613ea411bf2d3e64a220f98e82
Author: Frederik Harwath <frederik.harwath at amd.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
A llvm/test/CodeGen/AMDGPU/si-instr-info-vopc-exec.mir
Log Message:
-----------
[AMDGPU] SIInstrInfo: Fix resultDependsOnExec for VOPC instructions (#134629)
SIInstrInfo::resultDependsOnExec assumes that operand 0 of a comparison
is always the destination of the instruction. This is not true for
instructions in VOPC form where it is "src0". This led to a crash in
machine-cse.
---------
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
Commit: ef72b936262bc712d65756df1ad3ee095c794e0e
https://github.com/llvm/llvm-project/commit/ef72b936262bc712d65756df1ad3ee095c794e0e
Author: David Sherwood <david.sherwood at arm.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-intrinsic-calls.ll
Log Message:
-----------
[LV] Use requested calling convention for vector math routines (#136122)
Some vector math routines, e.g. ArmPL, specify a particular
calling convention on the routines which can help improve
performance by specifying what registers have to be preserved
across the call.
Commit: 3334c3597dd51f5a102e5005738e3bf4ef7530e2
https://github.com/llvm/llvm-project/commit/3334c3597dd51f5a102e5005738e3bf4ef7530e2
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
M llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/BPF/BPFTargetTransformInfo.h
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
M llvm/lib/Target/VE/VETargetTransformInfo.h
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
Log Message:
-----------
[TTI] Fix discrepancies in prototypes between interface and implementations (NFCI) (#136655)
These are not diagnosed because implementations hide the methods of the base class rather than overriding them.
This works as long as a hiding function is callable with the same arguments as the same function from the base class.
Pull Request: https://github.com/llvm/llvm-project/pull/136655
Commit: a35f940b876a09211f3e68dd25d00271b7195145
https://github.com/llvm/llvm-project/commit/a35f940b876a09211f3e68dd25d00271b7195145
Author: Christian Kandeler <christian.kandeler at qt.io>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang-tools-extra/clangd/unittests/XRefsTests.cpp
M clang/lib/Index/IndexBody.cpp
Log Message:
-----------
[clangd] Support operators new and delete in textDocument/references (#135620)
Commit: c3f815ba82defc84244a9688fd2578da513340fb
https://github.com/llvm/llvm-project/commit/c3f815ba82defc84244a9688fd2578da513340fb
Author: anjenner <161845516+anjenner at users.noreply.github.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M lldb/source/Core/DataFileCache.cpp
M llvm/include/llvm/Support/Caching.h
M llvm/lib/CGData/CodeGenData.cpp
M llvm/lib/Debuginfod/Debuginfod.cpp
M llvm/lib/LTO/LTOBackend.cpp
M llvm/lib/Support/Caching.cpp
M llvm/tools/gold/gold-plugin.cpp
M llvm/tools/llvm-lto2/llvm-lto2.cpp
M llvm/unittests/Support/CMakeLists.txt
A llvm/unittests/Support/Caching.cpp
Log Message:
-----------
Modify the localCache API to require an explicit commit on CachedFile… (#136121)
…Stream.
CachedFileStream has previously performed the commit step in its
destructor, but this means its only recourse for error handling is
report_fatal_error. Modify this to add an explicit commit() method, and
call this in the appropriate places with appropriate error handling for
the location.
Currently the destructor of CacheStream gives an assert failure in Debug
builds if commit() was not called. This will help track down any
remaining uses of the API that assume the old destructior behaviour. In
Release builds we fall back to the previous behaviour and call
report_fatal_error if the commit fails.
This is version 2 of this PR, superseding reverted PR
https://github.com/llvm/llvm-project/pull/115331 . I have incorporated a
change to the testcase to make it more reliable on Windows, as well as
two follow-up changes
(https://github.com/llvm/llvm-project/commit/df79000896101acc9b8d7435e59f767b36c00ac8
and
https://github.com/llvm/llvm-project/commit/b0baa1d8bd68a2ce2f7c5f2b62333e410e9122a1)
that were also reverted when 115331 was reverted.
---------
Co-authored-by: Augie Fackler <augie at google.com>
Co-authored-by: Vitaly Buka <vitalybuka at google.com>
Commit: 382263376fcfed967f5bc17400d9e4542b37801c
https://github.com/llvm/llvm-project/commit/382263376fcfed967f5bc17400d9e4542b37801c
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M lldb/docs/resources/build.rst
Log Message:
-----------
[lldb][docs] Repeat required Python version number
We do say it in the table below but if you didn't
want any optional stuff you'd miss it.
Commit: 278c429d11e63bc709ea8c537b23c4e350ce2a07
https://github.com/llvm/llvm-project/commit/278c429d11e63bc709ea8c537b23c4e350ce2a07
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
Log Message:
-----------
[ValueTracking] Drop ucmp/scmp from getIntrinsicRange() (NFCI)
After #135642 we have a range attribute on the intrinsic declaration,
so we should not need the special handling here.
Commit: 4bcc414af3782c333f3d535c0e0a92e6120868f5
https://github.com/llvm/llvm-project/commit/4bcc414af3782c333f3d535c0e0a92e6120868f5
Author: Robert Konicar <rkonicar at mail.muni.cz>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/SMT/IR/SMTAttributes.td
M mlir/include/mlir/IR/BuiltinAttributes.td
M mlir/include/mlir/TableGen/AttrOrTypeDef.h
M mlir/lib/Dialect/SMT/IR/SMTAttributes.cpp
M mlir/lib/TableGen/AttrOrTypeDef.cpp
A mlir/test/mlir-tblgen/apint-param-error.td
M mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp
Log Message:
-----------
[MLIR][TableGen] Error on APInt parameter without custom comparator (#135970)
The error is triggered when an attribute or type uses an APInt typed
parameter with the generated equality operator. If the compared APInts
have different bit widths the equality operator triggers an assert. This
is dangerous, since `StorageUniquer` for types and attributes uses the
equality operator when a hash collision appears. As such, it is
necessary to use custom provided comarator or `APIntParameter` that
already has it.
This commit also replaces uses of the raw `APInt` parameter with the
`APIntParameter` and removes the no longer necessary custom StorageClass
for the `BitVectorAttr` from the SMT dialect that was a workaround for
the described issue.
---------
Co-authored-by: Tobias Gysi <tobias.gysi at nextsilicon.com>
Commit: d8b0e616b746a6c7bdd0492f2f349105028684b0
https://github.com/llvm/llvm-project/commit/d8b0e616b746a6c7bdd0492f2f349105028684b0
Author: Nathan Gauër <brioche at google.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
M llvm/test/CodeGen/SPIRV/pointers/getelementptr-downcast-vector.ll
Log Message:
-----------
[SPIR-V] Fix OpVectorShuffle operands on load (#135954)
The generated OpVectorShuffle was wrong, as the indices we pass are not
to select the vector to sample from, but the position in the vector.
Commit: e12681ae733e8341c161534d4d4de2611573b616
https://github.com/llvm/llvm-project/commit/e12681ae733e8341c161534d4d4de2611573b616
Author: Hans Wennborg <hans at chromium.org>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/test/Driver/cl-options.c
Log Message:
-----------
[clang-cl] Parse the /dynamicdeopt option
which was mentioned in
https://devblogs.microsoft.com/cppblog/cpp-dynamic-debugging-full-debuggability-for-optimized-builds/
(That post also mentions /d2DDTrimInlines, which we already parse via
a /d2 catch-all.)
Commit: adb671ea23af72c0fa1acd42103a5e9ca413d729
https://github.com/llvm/llvm-project/commit/adb671ea23af72c0fa1acd42103a5e9ca413d729
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.h
Log Message:
-----------
[lldb] Clean up StartDebugserverProcess before I start refactoring it (#135342)
- use early exits where possible
- avoid the listen thread by using Socket APIs which allow separate
"listen" and "accept" steps
- use formatv-like log statements
There "should" be no functional changes from this patch.
Commit: a86f4ee774e6d2eb9f38502ddda65842179a246a
https://github.com/llvm/llvm-project/commit/a86f4ee774e6d2eb9f38502ddda65842179a246a
Author: Yuval Deutscher <yuvald at sweet.security>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M lldb/test/API/commands/platform/launchgdbserver/TestPlatformLaunchGDBServer.py
M lldb/tools/lldb-server/SystemInitializerLLGS.h
Log Message:
-----------
[lldb] Use correct path for debugserver (#131609)
This solves an issue that arises when running lldb-server through a
symlink which is not named exactly `lldb-server`. For example, in many
distros lldb-server is packaged as e.g.
`/usr/lib/llvm-19/bin/lldb-server` which is then accessed through a
symlink such as `/usr/bin/lldb-server-19`.
It turns out that there is a cascade of bugs here:
* `GetShlibDir` attempts to locate the LLVM library directory by calling
`GetModuleFileSpecForHostAddress` on the address of the function
`ComputeSharedLibraryDirectory`, assuming that it is inside
`liblldb.so`. However, in every packaging I've seen of lldb-server the
function `ComputeSharedLibraryDirectory` is statically linked into the
`lldb-server` binary and is not in `liblldb.so`.
* When run through a symlink, `GetModuleFileSpecForHostAddress` on an
address that is in `lldb-server` returns the path of the symlink, not
the path of the binary itself. So we get e.g. `/usr/bin/` and not
`/usr/lib/llvm-19/bin/`.
* `GetDebugserverPath` attempts to concat `"lldb-server"` to the
directory we obtained, and thus fails when the symlink is not named
exactly `lldb-server`.
* Ironically, the reason that this works in the first place is precisely
because `GetModuleFileSpecForHostAddress` returns an incorrect path -
when the server is run as `lldb-server-19 ...` it returns
`"lldb-server-19"` which then causes `ComputePathRelativeToLibrary` to
fail and then `ComputeSupportExeDirectory` falls back to just using
`GetProgramFileSpec` instead (which is the only option that actually
yields a correct path).
Commit: 9efd798a278a7ddda3b88365558ceb655c329d11
https://github.com/llvm/llvm-project/commit/9efd798a278a7ddda3b88365558ceb655c329d11
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
Log Message:
-----------
[TTI] Make the rest of TTI::Concept/TTI::Model methods const (NFC) (#136668)
This will simplify future changes.
Commit: 112ffe7c621e8bf145c5c5926e36f3af9e0fd045
https://github.com/llvm/llvm-project/commit/112ffe7c621e8bf145c5c5926e36f3af9e0fd045
Author: Sylvestre Ledru <sylvestre at debian.org>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/include/clang/Driver/Distro.h
M clang/lib/Driver/Distro.cpp
Log Message:
-----------
Add support of the next Ubuntu (Ubuntu 25.10 - Questing Quokka)
Commit: 97eb416c65863cdf25ec3fa19ed056aac38d1013
https://github.com/llvm/llvm-project/commit/97eb416c65863cdf25ec3fa19ed056aac38d1013
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M flang/lib/Parser/unparse.cpp
A flang/test/Parser/OpenMP/cancel.f90
M llvm/include/llvm/Frontend/Directive/DirectiveBase.td
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/TableGen/DirectiveEmitter.h
M llvm/utils/TableGen/Basic/DirectiveEmitter.cpp
Log Message:
-----------
[flang][Parser][OpenMP] Fix unparser for cancellation_construct_type (#136001)
Previously the unparser would print like
```
!$OMP CANCEL CANCELLATION_CONSTRUCT_TYPE(SECTIONS)
```
This is not valid Fortran. I have fixed it to print without the clause
name.
Commit: c1940cd0deef84c9cbbf6966d956b8fef4519efa
https://github.com/llvm/llvm-project/commit/c1940cd0deef84c9cbbf6966d956b8fef4519efa
Author: Nathan Gauër <brioche at google.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
M llvm/test/CodeGen/SPIRV/pointers/getelementptr-downcast-struct.ll
M llvm/test/CodeGen/SPIRV/pointers/getelementptr-downcast-vector.ll
A llvm/test/CodeGen/SPIRV/pointers/store-struct.ll
Log Message:
-----------
[SPIR-V] Add store legalization for ptrcast (#135369)
This commits adds handling for spv.ptrcast result being used in a store
instruction, modifying the store to operate on the source type.
Commit: 8f8853a5743fe204b390f0276cb6d0266e4b9a9b
https://github.com/llvm/llvm-project/commit/8f8853a5743fe204b390f0276cb6d0266e4b9a9b
Author: quic_hchandel <quic_hchandel at quicinc.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
A llvm/test/CodeGen/RISCV/xqcia.ll
Log Message:
-----------
[RISCV] Add ISel patterns for Xqcia instructions (#136548)
This patch adds instruction selection patterns for generating the
integer arithmetic instructions.
Commit: a095ebc58c9f7cd0d39796ed0aabc63b23ed88ce
https://github.com/llvm/llvm-project/commit/a095ebc58c9f7cd0d39796ed0aabc63b23ed88ce
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/vector-select.ll
Log Message:
-----------
[LLVM][CostModel][AArch64] Remove magic numbers from f16 vector compares. (#135795)
The PR also extends the code to cover bfloat vector compares that are
also promoted to float.
NOTE: There is a bail out for the compares that are scalarised that will
be removed by https://github.com/llvm/llvm-project/pull/135398.
Commit: d7d170656404e1cb29a51689fd66a12bc060c630
https://github.com/llvm/llvm-project/commit/d7d170656404e1cb29a51689fd66a12bc060c630
Author: Ebuka Ezike <yerimyah1 at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M lldb/include/lldb/Core/IOHandler.h
M lldb/include/lldb/Host/Editline.h
M lldb/include/lldb/Interpreter/CommandInterpreter.h
M lldb/source/Core/Debugger.cpp
M lldb/source/Core/IOHandler.cpp
M lldb/source/Host/common/Editline.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/test/API/terminal/TestEditline.py
Log Message:
-----------
[lldb] Fix use-color settings not persistent (#135626)
Fixes https://github.com/llvm/llvm-project/issues/22981
If `settings set use-color` is changed when lldb is running it does not take effect.
This is fixes that.
---------
Signed-off-by: Ebuka Ezike <yerimyah1 at gmail.com>
Co-authored-by: Jonas Devlieghere <jonas at devlieghere.com>
Commit: 1a48e1df4541ccccdaf14a6ea379be004e319a09
https://github.com/llvm/llvm-project/commit/1a48e1df4541ccccdaf14a6ea379be004e319a09
Author: Mariusz Sikora <mariusz.sikora at amd.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
A llvm/test/CodeGen/AMDGPU/do-not-fold-copy.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
Log Message:
-----------
[AMDGPU] Do not fold COPY with implicit operands (#136003)
Folding may remove COPY from inside of the divergent loop.
Commit: ef926e7e49cab2d8087ed4ebdbdc686ac99e1c8f
https://github.com/llvm/llvm-project/commit/ef926e7e49cab2d8087ed4ebdbdc686ac99e1c8f
Author: Christian Sigg <csigg at google.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
Log Message:
-----------
[lldb][mlir] Port a22ad659cd0665669d89fae174f9e6a83d1a446d
Commit: c60f24dca96dad44afc60df3fcb80997737b6306
https://github.com/llvm/llvm-project/commit/c60f24dca96dad44afc60df3fcb80997737b6306
Author: Christian Sigg <csigg at google.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
Log Message:
-----------
[lldb][mlir] Fix port of a22ad65
Sorry, typo!
Commit: 7851b1bcf1f0966883d5598268f95d355718f9f5
https://github.com/llvm/llvm-project/commit/7851b1bcf1f0966883d5598268f95d355718f9f5
Author: Christian Sigg <csigg at google.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M mlir/lib/ExecutionEngine/CudaRuntimeWrappers.cpp
M mlir/lib/Target/LLVMIR/Dialect/GPU/SelectObjectAttr.cpp
A mlir/test/Integration/GPU/CUDA/concurrent-kernels.mlir
M mlir/test/Target/LLVMIR/gpu.mlir
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][gpu] Change GPU modules to globals (#135478)
Load/unload GPU modules in global ctors/dtors instead of each time when
launching a kernel.
Loading GPU modules is a heavy-weight operation and synchronizes the GPU
context. Now that the modules are loaded ahead of time, asynchronously
launched kernels can run concurrently, see
https://discourse.llvm.org/t/how-to-lower-the-combination-of-async-gpu-ops-in-gpu-dialect.
The implementations of `embedBinary()` and `launchKernel()` use slightly
different mechanics at the moment but I prefer to not change the latter
more than necessary as part of this PR. I will prepare a follow-up NFC
for `launchKernel()` to align them again.
Commit: 84cd0d3c38e40e4cb5e416684ecd84df914e19aa
https://github.com/llvm/llvm-project/commit/84cd0d3c38e40e4cb5e416684ecd84df914e19aa
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M lldb/source/Plugins/UnwindAssembly/x86/UnwindAssembly-x86.cpp
M lldb/source/Symbol/DWARFCallFrameInfo.cpp
M lldb/source/Symbol/UnwindPlan.cpp
M lldb/test/Shell/Unwind/Inputs/eh-frame-small-fde.s
M lldb/test/Shell/Unwind/eh-frame-small-fde.test
M lldb/unittests/Symbol/UnwindPlanTest.cpp
Log Message:
-----------
[lldb] Slide eh_frame unwind plan if it doesn't begin at function boundary (#135333)
This is mainly useful for discontinuous functions because individual
parts of the function will have separate FDE entries, which can begin
many megabytes from the start of the function. However, I'm separating
it out, because it turns out we already have a test case for the
situation where the FDE does not begin exactly at the function boundary.
The test works mostly by accident because the FDE starts only one byte
after the beginning of the function so it doesn't really matter whether
one looks up the unwind row using the function or fde offset. In this
patch, I beef up the test to catch this problem more reliably.
To make this work I've also needed to change a couple of places which
that an unwind plan always has a row at offset zero.
Commit: 3d91a71223801bb73ab3e4ff8ab3f883639ed79f
https://github.com/llvm/llvm-project/commit/3d91a71223801bb73ab3e4ff8ab3f883639ed79f
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticGroups.td
A clang/test/SemaCXX/cxx20-c99-designator.cpp
M clang/test/SemaCXX/decltype.cpp
Log Message:
-----------
Reorganize -Winitializer-overrides and -Wreorder-init-list (#136586)
These are both now grouped under -Wc99-designator as they both relate to
the C99 feature as it was introduced into C++20.
Fixes #47037
Commit: a25fdd7aca240c5e1a1051ee0509c9c6a4440009
https://github.com/llvm/llvm-project/commit/a25fdd7aca240c5e1a1051ee0509c9c6a4440009
Author: Pankaj Dwivedi <pankajkumar.divedi at amd.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/add64-low-32-bits-known-zero.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/constrained-shift.ll
M llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll
M llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/ptrmask.ll
M llvm/test/CodeGen/AMDGPU/sdag-print-divergence.ll
M llvm/test/CodeGen/AMDGPU/sub64-low-32-bits-known-zero.ll
A llvm/test/CodeGen/AMDGPU/uniform-vgpr-to-sgpr-return.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
Log Message:
-----------
Reapply "[AMDGPU] Insert readfirstlane in the function returns in sgpr." (#136678)
Reapply #135326 and fix the target-dependent constant check.
---------
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
Commit: 7f684c9fca76a166efe4e03c6e2bc969e8aed81b
https://github.com/llvm/llvm-project/commit/7f684c9fca76a166efe4e03c6e2bc969e8aed81b
Author: Jacques Pienaar <jpienaar at google.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M mlir/lib/Interfaces/ControlFlowInterfaces.cpp
M mlir/test/Dialect/SCF/invalid.mlir
Log Message:
-----------
[mlir] Avoid doublespace in error (NFC). (#136560)
This was resulting in 2 spaces in the error message.
Commit: e428afdfcf56ccadbbcff16e8fe52e51622baed7
https://github.com/llvm/llvm-project/commit/e428afdfcf56ccadbbcff16e8fe52e51622baed7
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/Support/BUILD.gn
Log Message:
-----------
[gn build] Port c3f815ba82de
Commit: 587206a442ebb656f9d72e7e0cc5845ef3a2f7ed
https://github.com/llvm/llvm-project/commit/587206a442ebb656f9d72e7e0cc5845ef3a2f7ed
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M lldb/test/API/commands/platform/launchgdbserver/TestPlatformLaunchGDBServer.py
Log Message:
-----------
[lldb] Avoid modifying the source tree in TestPlatformLaunchGDBServer
The test binary gets uploaded to the "remote" platform's working
directory which, by default is in the source tree. Change that.
Commit: 47903e3372b8ab942f0d36f135edba5a8de07cf9
https://github.com/llvm/llvm-project/commit/47903e3372b8ab942f0d36f135edba5a8de07cf9
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
A llvm/test/CodeGen/AMDGPU/insert-waitcnts-gfx12-wbinv.mir
Log Message:
-----------
[AMDGPU][InsertWaitCnts] Add test for global_wb/inv/wbinv tracking (#135339)
Commit: ec3a90509d7db3b32d6102351c86470d9799dc9b
https://github.com/llvm/llvm-project/commit/ec3a90509d7db3b32d6102351c86470d9799dc9b
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx942.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-store.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-gfx12-wbinv.mir
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-global-inv-wb.mir
Log Message:
-----------
[AMDGPU][InsertWaitCnts] Track global_wb/inv/wbinv (#135340)
wb/wbinv use storecnt, inv uses loadcnt.
Track them as VMEM_WRITE_ACCESS and VMEM_READ_ACCESS to avoid
InsertWaitCnt incorrectly eliminating the waitcnts after these instructions.
Solves SWDEV-526604
Commit: 2b712693886a2a8339c0452f12f06b676e946d49
https://github.com/llvm/llvm-project/commit/2b712693886a2a8339c0452f12f06b676e946d49
Author: Iris <0.0 at owo.li>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
Log Message:
-----------
[SelectionDAG][X86] Fold `sub(x, mul(divrem(x,y)[0], y))` to `divrem(x, y)[1]` (#136565)
Closes #51823.
Commit: 2e145f11c0bcfa2052416d96d682c75f33971a8c
https://github.com/llvm/llvm-project/commit/2e145f11c0bcfa2052416d96d682c75f33971a8c
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M flang-rt/CMakeLists.txt
M flang-rt/README.md
M flang-rt/cmake/modules/AddFlangRT.cmake
M flang-rt/lib/runtime/CMakeLists.txt
M libc/cmake/modules/LLVMLibCArchitectures.cmake
M libc/docs/gpu/building.rst
Log Message:
-----------
[LLVM] Replace use of `LLVM_RUNTIMES_TARGET` with `LLVM_DEFAULT_TARGET_TRIPLE` (#136208)
Summary:
For purposes of determining the triple, it's more correct to use
`LLVM_DEFAULT_TARGET_TRIPLE`.
Commit: 974a8ccb2b9f5b930ce47f65122b5a86481e57fe
https://github.com/llvm/llvm-project/commit/974a8ccb2b9f5b930ce47f65122b5a86481e57fe
Author: Muhammad Omair Javaid <omair.javaid at linaro.org>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M lldb/test/API/commands/statistics/basic/TestStats.py
Log Message:
-----------
[LLDB] Silence Windows buildbot failure caused by #136226
This patch temporarily silences a LLDB test failure caused by PR 136226.
The PR added symbol/table count statistics but caused failures in the
lldb-aarch64-windows buildbot where the reported number of symbols and
symbol tables were incorrectly showing as 0.
https://lab.llvm.org/buildbot/#/builders/141/builds/8084
Commit: a5cdbef5f06904fab27219955604a2759e4dd482
https://github.com/llvm/llvm-project/commit/a5cdbef5f06904fab27219955604a2759e4dd482
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M flang-rt/CMakeLists.txt
M flang-rt/README.md
M flang-rt/cmake/modules/AddFlangRT.cmake
M flang-rt/lib/runtime/CMakeLists.txt
M libc/cmake/modules/LLVMLibCArchitectures.cmake
M libc/docs/gpu/building.rst
Log Message:
-----------
Revert "[LLVM] Replace use of `LLVM_RUNTIMES_TARGET` with `LLVM_DEFAULT_TARGET_TRIPLE` (#136208)"
This reverts commit 2e145f11c0bcfa2052416d96d682c75f33971a8c.
Somehow causes some static assertions to fail?
Commit: dba8acde6d6a320dad42cdbfe7c8261938348e23
https://github.com/llvm/llvm-project/commit/dba8acde6d6a320dad42cdbfe7c8261938348e23
Author: Hans Wennborg <hans at chromium.org>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
Log Message:
-----------
Revert "[ValueTracking] Drop ucmp/scmp from getIntrinsicRange() (NFCI)"
This does seem to cause some functionality to change, see comment on
https://github.com/llvm/llvm-project/commit/278c429d11e63bc709ea8c537b23c4e350ce2a07
This reverts commit 278c429d11e63bc709ea8c537b23c4e350ce2a07.
Commit: 616e8cc1fa0319819aa6978af0af9a3e4896103a
https://github.com/llvm/llvm-project/commit/616e8cc1fa0319819aa6978af0af9a3e4896103a
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M lldb/test/API/commands/platform/launchgdbserver/TestPlatformLaunchGDBServer.py
M lldb/tools/lldb-server/SystemInitializerLLGS.h
Log Message:
-----------
Revert "[lldb] Use correct path for debugserver (#131609)"
This reverts commit a86f4ee774e6d2eb9f38502ddda65842179a246a and the fixup in
587206a442ebb656f9d72e7e0cc5845ef3a2f7ed because brakage on macos
(TestAutoInstallMainExecutable.py).
Commit: c9eb1ffcfe7cf8c9751afe436a6fcab9cb5b9c9b
https://github.com/llvm/llvm-project/commit/c9eb1ffcfe7cf8c9751afe436a6fcab9cb5b9c9b
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M clang/lib/Sema/SemaOpenACCClause.cpp
M clang/test/CIR/CodeGenOpenACC/kernels.c
M clang/test/CIR/CodeGenOpenACC/parallel.c
M clang/test/CIR/CodeGenOpenACC/serial.c
M clang/test/SemaOpenACC/compute-construct-async-clause.c
Log Message:
-----------
[OpenACC][CIR] Implement 'async' lowering. (#136626)
Async acts just like num_workers/vector_length in that it gets a new
variant per device_type and is lowered as an operand.
However, it has one additional complication, in that it can have a
variant that has no argument, which produces an attribute with the
correct devicetype.
Additionally, this syncronizes us with the implementation of flang,
which prohibits multiple 'async' clauses per-device_type.
Commit: cfeaa395970b7a2a2f0389d06a20d0970d591807
https://github.com/llvm/llvm-project/commit/cfeaa395970b7a2a2f0389d06a20d0970d591807
Author: Koakuma <koachan at protonmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/Sparc/SparcInstrVIS.td
A llvm/test/CodeGen/SPARC/multiply-extension.ll
M llvm/test/CodeGen/SPARC/smulo-128-legalisation-lowering.ll
M llvm/test/CodeGen/SPARC/umulo-128-legalisation-lowering.ll
Log Message:
-----------
Reapply "[SPARC] Use umulxhi to do extending 64x64->128 multiply when we have VIS3" (#135897) (#136475)
Update the tests to reflect the change in instruction ordering.
Otherwise there are no changes from the previous commit.
This reverts commit 5e9650ec2deb2f2bb6d5ad28e83bb6cd3c4189e4.
Commit: d20604e5b6792bd010dd4dfd36f3e836ae0fe7b2
https://github.com/llvm/llvm-project/commit/d20604e5b6792bd010dd4dfd36f3e836ae0fe7b2
Author: David Green <david.green at arm.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[CostModel] Plumb CostKind into getExtractWithExtendCost (#135523)
This will likely not affect much with the current uses of the function,
but if we have getExtractWithExtendCost we can plumb CostKind through it
in the same way as other costmodel functions.
Commit: e87aa0c6ab7b9d1abbf86e8df84053cd4de92656
https://github.com/llvm/llvm-project/commit/e87aa0c6ab7b9d1abbf86e8df84053cd4de92656
Author: Ivan Butygin <ivan.butygin at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/Arith/Utils/Utils.h
M mlir/include/mlir/Dialect/Vector/TransformOps/VectorTransformOps.td
M mlir/include/mlir/Dialect/Vector/Transforms/VectorRewritePatterns.h
M mlir/lib/Dialect/Arith/Utils/Utils.cpp
M mlir/lib/Dialect/Vector/TransformOps/VectorTransformOps.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp
M mlir/test/Dialect/Vector/vector-sink-transform.mlir
M mlir/test/Dialect/Vector/vector-sink.mlir
M mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
Log Message:
-----------
[mlir][vector] Sink vector.extract/splat into load/store ops (#134389)
```
vector.load %arg0[%arg1] : memref<?xf32>, vector<4xf32>
vector.extract %0[1] : f32 from vector<4xf32>
```
Gets converted to:
```
%c1 = arith.constant 1 : index
%0 = arith.addi %arg1, %c1 overflow<nsw> : index
%1 = memref.load %arg0[%0] : memref<?xf32>
```
```
%0 = vector.splat %arg2 : vector<1xf32>
vector.store %0, %arg0[%arg1] : memref<?xf32>, vector<1xf32>
```
Gets converted to:
```
memref.store %arg2, %arg0[%arg1] : memref<?xf32>
```
Commit: 278062f119795373c5e43a62280b4b6f2bffbd48
https://github.com/llvm/llvm-project/commit/278062f119795373c5e43a62280b4b6f2bffbd48
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/test/Transforms/CorrelatedValuePropagation/uscmp.ll
Log Message:
-----------
[CVP] Add test showing how a call-site range can pessimize opt (NFC)
Commit: d51b2785abf77978d9218a7b6fb5b8ec6c770c31
https://github.com/llvm/llvm-project/commit/d51b2785abf77978d9218a7b6fb5b8ec6c770c31
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/IR/Instructions.cpp
M llvm/test/Transforms/CorrelatedValuePropagation/uscmp.ll
Log Message:
-----------
[IR] Intersect call and fn range in CallBase::getRange()
To make sure that a larger range on the call-site does not suppress
information from a smaller range at the declaration.
Commit: 980531cac0988e509425e64fbd279ee98e25307c
https://github.com/llvm/llvm-project/commit/980531cac0988e509425e64fbd279ee98e25307c
Author: Luke Lau <luke at igalia.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
Log Message:
-----------
[VPlan] Fix MayReadFromMemory/MayWriteToMemory on VPWidenIntrinsicRecipe (#136684)
These seem to be the wrong way round, e.g. see the definition at
Instruction::mayReadFromMemory().
If an instruction only writes to memory then it's known to not read
memory, and so on.
Only noticed this when using VPWidenIntrinsicRecipe in a local patch and
wondered why it kept on getting DCEd despite the intrinsic writing to
memory.
Commit: c2ae5723b5418fa0f5901f2c21c2c905fa48a498
https://github.com/llvm/llvm-project/commit/c2ae5723b5418fa0f5901f2c21c2c905fa48a498
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/cxx11.cpp
Log Message:
-----------
[clang][bytecode] Allow reinterpret casts from/to the same pointer type (#136692)
Commit: c5a5f4330a0014b9beafef1c75cc66dba917fa09
https://github.com/llvm/llvm-project/commit/c5a5f4330a0014b9beafef1c75cc66dba917fa09
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
Log Message:
-----------
Reapply [ValueTracking] Drop ucmp/scmp from getIntrinsicRange() (NFCI)
Reapply after d51b2785abf77978d9218a7b6fb5b8ec6c770c31, which should
fix optimization regressions.
After #135642 we have a range attribute on the intrinsic declaration,
so we should not need the special handling here.
Commit: 901ac60db7d864c79aa34d93fc46f2635e3afd50
https://github.com/llvm/llvm-project/commit/901ac60db7d864c79aa34d93fc46f2635e3afd50
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
Log Message:
-----------
[RISCV] Use ri.vzip2{a,b} for interleave2 if available (#136364)
If XRivosVizip is available, the ri.vzip2a and ri.vzip2b instructions
can be used perform a interleave shuffle. This patch only effects the
intrinsic lowering (and thus scalable vectors). Fixed vectors go through
shuffle lowering and the zip2a (but not zip2b) case is already handled
there..
Commit: f010725e392c50700dec0dfe7ef3ff1ecfc517bd
https://github.com/llvm/llvm-project/commit/f010725e392c50700dec0dfe7ef3ff1ecfc517bd
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td
M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
M mlir/test/Dialect/Linalg/canonicalize.mlir
M mlir/test/Dialect/Linalg/vectorize-tensor-extract.mlir
Log Message:
-----------
[mlir][linalg] Add folder for `linalg.index` (#136640)
We know that the index of unit dims is always 0.
Commit: 0252d338fa9f4f2f1262b5f7d8158e3f5857fcaf
https://github.com/llvm/llvm-project/commit/0252d338fa9f4f2f1262b5f7d8158e3f5857fcaf
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/reused-scalar-repeated-in-node.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vectorizable-selects-uniform-cmps.ll
M llvm/test/Transforms/SLPVectorizer/X86/full-match-with-poison-scalar.ll
M llvm/test/Transforms/SLPVectorizer/X86/full-matched-bv-with-subvectors.ll
M llvm/test/Transforms/SLPVectorizer/X86/matched-nodes-updated.ll
M llvm/test/Transforms/SLPVectorizer/X86/memory-runtime-checks.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi-extracts-bv-combined.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduced-val-vectorized-in-transform.ll
M llvm/test/Transforms/SLPVectorizer/icmp-altopcode-after-reordering.ll
M llvm/test/Transforms/SLPVectorizer/reordering-single-phi.ll
Log Message:
-----------
[SLP]Model single unique value insert + shuffle as splat + select, where profitable
When we have the remaining unique scalar, that should be inserted into
non-poison vector and into non-zero position:
```
%vec1 = insertelement %vec, %v, pos1
%res = shuffle %vec1, poison, <0, 1, 2,..., pos1, pos1 + 1, ..., pos1,
...>
```
better to estimate if it is profitable to model it as is or model it as:
```
%bv = insertelement poison, %v, 0
%splat = shuffle %bv, poison, <poison, ..., 0, ..., 0, ...>
%res = shuffle %vec, %splat, <0, 1, 2,..., pos1 + VF, pos1 + 1, ...>
```
Reviewers: preames, hiraditya, RKSimon
Reviewed By: preames
Pull Request: https://github.com/llvm/llvm-project/pull/136590
Commit: 212f14fbc26e71b26d3345b272b97f22c9df4725
https://github.com/llvm/llvm-project/commit/212f14fbc26e71b26d3345b272b97f22c9df4725
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
Log Message:
-----------
[CIR] Change 'CIR-int' to use a 'APIntParameter' argument (#136713)
After 4bcc414af3782c333 an APInt parameter diagnoses, so this switches
us to APIntParameter.
I don't believe we need to put this in the incubator, as it'll get this
in the same
pulldown as the diagnostic.
Commit: c6071805d4750f7c3fb6cede2169adf02ed67b66
https://github.com/llvm/llvm-project/commit/c6071805d4750f7c3fb6cede2169adf02ed67b66
Author: Iris <0.0 at owo.li>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/docs/GitHub.rst
Log Message:
-----------
[docs] Fix typo in GitHub.rst
Commit: b53db8913b1b0adf2236bca8ee68a6a971f9c708
https://github.com/llvm/llvm-project/commit/b53db8913b1b0adf2236bca8ee68a6a971f9c708
Author: Morris Hafner <mmha at users.noreply.github.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
M clang/test/CIR/CodeGen/binop.cpp
A clang/test/CIR/Lowering/select.cir
Log Message:
-----------
[CIR] Upstream SelectOp and ShiftOp (#133405)
Since SelectOp will only generated by a future pass that transforms a
TernaryOp this only includes the lowering bits.
This patch also improves the testing of the existing binary operators.
---------
Co-authored-by: Morris Hafner <mhafner at nvidia.com>
Commit: a5a6ae12a4f3e7b22e1273465b64e632b49cdd2e
https://github.com/llvm/llvm-project/commit/a5a6ae12a4f3e7b22e1273465b64e632b49cdd2e
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/docs/ResponseGuide.rst
Log Message:
-----------
[docs][CoC] Update verbiage about appeal process (#136715)
Often, when the CoC investigates incidents, most members are available
to discuss & come to a unanimous decision. In the event of an appeal, we
agreed that the effective way to investigate would be for the committee
to consider evidence that was missed in the initial decision-making.
Update the Response guide to reflect this.
Commit: 9c388f1f05f4f5fd661eb67a32cf3c5843b86c02
https://github.com/llvm/llvm-project/commit/9c388f1f05f4f5fd661eb67a32cf3c5843b86c02
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/segmented-loads-simple.ll
M llvm/test/Transforms/SLPVectorizer/X86/reorder-reused-masked-gather.ll
Log Message:
-----------
[SLP]Prefer segmented/deinterleaved loads to strided and fix codegen
Need to estimate, which one is preferable, deinterleaved/segmented
loads or strided. Segmented loads can be combined, improving
the overall performance.
Reviewers: RKSimon, hiraditya
Reviewed By: hiraditya, RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/135058
Commit: f6178cdad03468a9801a23f8f7e80927614fdb7e
https://github.com/llvm/llvm-project/commit/f6178cdad03468a9801a23f8f7e80927614fdb7e
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
Log Message:
-----------
[SelectionDAG] Pass LoadExtType when ATOMIC_LOAD is created. (#136653)
Rename one signature of getAtomic to getAtomicLoad and pass LoadExtType.
Previously we had to set the extension type after the node was created,
but we don't usually modify SDNodes once they are created. It's possible
the node already existed and has been CSEd. If that happens, modifying
the node may affect the other users. It's therefore safer to add the
extension type at creation so that it is part of the CSE information.
I don't know of any failures related to the current implementation. I
only noticed that it doesn't match how we usually do things.
Commit: 928c33354ee88b98bcf785d8866171857a92dd82
https://github.com/llvm/llvm-project/commit/928c33354ee88b98bcf785d8866171857a92dd82
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp
M llvm/lib/IR/Verifier.cpp
A llvm/test/CodeGen/RISCV/di-assignment-tracking-vector.ll
A llvm/test/Verifier/diassignid-vector-stores.ll
Log Message:
-----------
[DebugInfo] Handle additional types of stores in assignment tracking (#129070)
Fixes #126417.
Currently, assignment tracking recognizes allocas, stores, and mem
intrinsics as valid instructions to tag with DIAssignID, with allocas
representing the allocation for a variable and the others representing
instructions that may assign to the variable. There are other intrinsics
that can perform these assignments however, and if we transform a store
instruction into one of these intrinsics and correctly transfer the
DIAssignID over, this results in a verifier error. The
AssignmentTrackingAnalysis pass also does not know how to handle these
intrinsics if they are untagged, as it does not know how to extract
assignment information (base address, offset, size) from them.
This patch adds _some_ support for some intrinsics that may perform
assignments: masked store/scatter, and vp store/strided store/scatter.
This patch does not add support for extracting assignment information
from these, as they may store with either non-constant size or to
non-contiguous blocks of memory; instead it adds support for recognizing
untagged stores with "unknown" assignment info, for which we assume that
the memory location of the associated variable should not be used, as we
can't determine which fragments of it should or should not be used.
In principle, it should be possible to handle the more complex cases
mentioned above, but it would require more substantial changes to
AssignmentTrackingAnalysis, and it is mostly only needed as a fallback
if the DIAssignID is not preserved on these alternative stores.
Commit: 4dbf67de4050cad3371706b991eb9e3cd9d39482
https://github.com/llvm/llvm-project/commit/4dbf67de4050cad3371706b991eb9e3cd9d39482
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
Log Message:
-----------
[RISCV] Lower SEW<=32 vector_deinterleave(2) via vunzip2{a,b} (#136463)
This is a continuation from 22d5890c and adds the neccessary logic to
handle SEW!=64 profitably. The interesting case is needing to handle
e.g. a single m1 which is split via extract_subvector into two operands,
and form that back into a single m1 operation - instead of letting the
vslidedown by vlenb/Constant sequence be generated. This is analogous to
the getSingleShuffleSrc for vnsrl, and we can share a bunch of code.
Commit: b20e063a90cc9277a3f2dc1f4bac39bce812c7ff
https://github.com/llvm/llvm-project/commit/b20e063a90cc9277a3f2dc1f4bac39bce812c7ff
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M flang/lib/Optimizer/OpenACC/FIROpenACCTypeInterfaces.cpp
M flang/test/Fir/OpenACC/openacc-mappable.fir
Log Message:
-----------
[flang][acc] Generate acc.bounds operation from FIR shape (#136637)
This PR adds support to be able to generate `acc.bounds` operation
through `MappableType`'s `generateAccBounds` when there is no fir.box
entity. This is especially useful because the FIR type does not capture
size information for explicit-shape arrays and current implementation
relied on finding the box entity.
This scenario is possible because during HLFIRtoFIR, `fir.array_coor`
and `fir.box_addr` operations are often optimized to use raw address. If
one tries to map the ssa value that represents such a variable, correct
dimensions need extracted from the shape information held in the fir
declare operation.
Commit: 0eba8cbef6a196d5373de17d8844487daf27656a
https://github.com/llvm/llvm-project/commit/0eba8cbef6a196d5373de17d8844487daf27656a
Author: Deric C. <cheung.deric at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
A llvm/test/CodeGen/DirectX/ShaderFlags/max-64-uavs-array-sm6_5.ll
A llvm/test/CodeGen/DirectX/ShaderFlags/max-64-uavs-array-sm6_6.ll
A llvm/test/CodeGen/DirectX/ShaderFlags/max-64-uavs.ll
Log Message:
-----------
[DirectX] Implement Max64UAVs shader flag analysis (#136229)
Fixes [#114553](https://github.com/llvm/llvm-project/issues/114553)
This implementation replicates the behavior of DXC in setting the
`m_b64UAVs` flag: the `Max64UAVs` DXIL module flag is set in the
presence of more than 8 UAVs in a DXIL module.
The behavior of how UAV (resource) arrays are counted differs based on
Shader Model version:
- If Shader Model < 6.6, then a UAV array counts as a single UAV
regardless of its range size
- if Shader Model >= 6.6, then a UAV array contributes its range size to
the total number of UAVs
I initially thought the complete implementation of this analysis may be
blocked by the resource arrays implementation, but it seems that it is
not the case, as the `@llvm.dx.resource.handle*` already includes a
range size argument.
Commit: ab4e181ea8a1b11546328cb71c330772b8720db7
https://github.com/llvm/llvm-project/commit/ab4e181ea8a1b11546328cb71c330772b8720db7
Author: erichkeane <ekeane at nvidia.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M clang/test/CIR/CodeGenOpenACC/init.c
M clang/test/CIR/CodeGenOpenACC/shutdown.c
Log Message:
-----------
[OpenACC][CIR] Implement 'if' and 'device_num' lowering for
init/shutdown
These are pretty simple, the 'if' implementation is the same as compute
constructs, and the 'device_num' is identical to a bunch of others, in
that it is just emitting an integral value.
Commit: c04958381e90c32381ddabf1552d17c63cdd060b
https://github.com/llvm/llvm-project/commit/c04958381e90c32381ddabf1552d17c63cdd060b
Author: Andrew Rogers <andrurogerz at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/docs/InterfaceExportAnnotations.rst
M llvm/include/llvm/Support/Compiler.h
Log Message:
-----------
[llvm] add LLVM_ABI_FRIEND macro for friend function decls (#136595)
## Purpose
Introduce a new `LLVM_ABI_FRIEND` macro to `llvm/Support/Compiler.h` for
annotating `friend` function declarations for DLL export.
## Overview
1. Add a new `LLVM_ABI_FRIEND` macro, which behaves identically to the
existing `LLVM_ABI` macro on Windows and compiles to nothing on other
platforms.
2. Update existing documentation to describe proper usage of the
`LLVM_ABI_FRIEND` annotation.
## Background
* MSVC issues a warning when it encounters a `friend` function
declaration that does not match the DLL import/export annotation of the
original function.
* When compiling ELF and Mach-O shared libraries, `friend` function
declarations with visibility annotations produce compilation errors
(GCC) and warnings (Clang).
* Additional context on the effort to annotate LLVM's public interface
is in [this
discourse](https://discourse.llvm.org/t/psa-annotating-llvm-public-interface/85307).
Commit: f52b01b6cfcfffcd93523c9e1b56a695f626f74b
https://github.com/llvm/llvm-project/commit/f52b01b6cfcfffcd93523c9e1b56a695f626f74b
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC]Rename functions/variables, limit visibility to meet the coding standards, NFC
Commit: c05da6e8611e4da7b16729cc2b8d2dc6c77ba4be
https://github.com/llvm/llvm-project/commit/c05da6e8611e4da7b16729cc2b8d2dc6c77ba4be
Author: erichkeane <ekeane at nvidia.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M clang/test/CIR/CodeGenOpenACC/set.c
Log Message:
-----------
[OpenACC][CIR] Implement lowering for 'set' clauses
The 'set' clauses are default_async, device_num, and if. The latter two
are implemented identically to other constructs by that name.
default_async works exactly like device_num, (and others) that take an
int-expression.
Commit: 5e101de13671a525d30ed7f546c1a8611db1da19
https://github.com/llvm/llvm-project/commit/5e101de13671a525d30ed7f546c1a8611db1da19
Author: Ivan Butygin <ivan.butygin at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M mlir/include/mlir/IR/BuiltinAttributes.h
M mlir/include/mlir/IR/BuiltinAttributes.td
M mlir/lib/IR/BuiltinAttributes.cpp
Log Message:
-----------
[mlir][nfc] Replace some `std::vector`s with `SmallVector` (#136703)
`SmallVector` is preferable to `std::vector`
https://llvm.org/docs/ProgrammersManual.html#llvm-adt-smallvector-h
Commit: c073c228654e907a619edc03ff87158da772704c
https://github.com/llvm/llvm-project/commit/c073c228654e907a619edc03ff87158da772704c
Author: Steven Perron <stevenperron at google.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/include/clang/Basic/AddressSpaces.h
M clang/lib/AST/Type.cpp
M clang/lib/AST/TypePrinter.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/DirectX.h
M clang/lib/Basic/Targets/NVPTX.h
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/Basic/Targets/SystemZ.h
M clang/lib/Basic/Targets/TCE.h
M clang/lib/Basic/Targets/WebAssembly.h
M clang/lib/Basic/Targets/X86.h
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/AST/HLSL/OutArgExpr.hlsl
M clang/test/AST/HLSL/StructuredBuffers-AST.hlsl
M clang/test/AST/HLSL/TypedBuffers-AST.hlsl
M clang/test/CodeGenHLSL/builtins/RWBuffer-subscript.hlsl
M clang/test/CodeGenHLSL/builtins/StructuredBuffers-subscripts.hlsl
M clang/test/SemaTemplate/address_space-dependent.cpp
Log Message:
-----------
[HLSL] Use hlsl_device address space for getpointer. (#127675)
We add the hlsl_device address space to represent the device memory
space as defined in section 1.7.1.3 of the [HLSL
spec](https://microsoft.github.io/hlsl-specs/specs/hlsl.pdf).
Fixes https://github.com/llvm/llvm-project/issues/127075
Commit: 68bfb17f1dd15f3b0b2754c8bce1d1c395e553c1
https://github.com/llvm/llvm-project/commit/68bfb17f1dd15f3b0b2754c8bce1d1c395e553c1
Author: Bob Wilson <bob.wilson at apple.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/lib/Frontend/HeaderIncludeGen.cpp
A clang/test/Preprocessor/print-header-crash.modulemap
Log Message:
-----------
[Clang] Fix crash when building a module with CC_PRINT_HEADERS_FORMAT=json (#136227)
There is no main file when building a module, so the code in
HeaderIncludesJSONCallback::EndOfMainFile() needs to check for that to
avoid crashing.
Commit: 55678dcbd5e4a4e096a2c856ac2f5dbfa57acc00
https://github.com/llvm/llvm-project/commit/55678dcbd5e4a4e096a2c856ac2f5dbfa57acc00
Author: Davide Italiano <davidino at meta.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M .github/CODEOWNERS
Log Message:
-----------
Remove myself from CODEOWNERS.
Commit: 1c722fc8f5671ab1bbb7965b3b5fbba0645884b0
https://github.com/llvm/llvm-project/commit/1c722fc8f5671ab1bbb7965b3b5fbba0645884b0
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/shuffle-exact-vlen.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-permute.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reductions.ll
Log Message:
-----------
[RISCV][TTI] Use processShuffleMask for shuffle legalization estimate (#136191)
We had some code which tried to estimate legalization costs for
illegally typed shuffles, but it only handled the case of a widening
shuffle, and used a somewhat adhoc heuristic. We can reuse the
processShuffleMask utility (which we already use for individual vector
register splitting when exact VLEN is known) to perform the same
splitting given the legal vector type as the unit of split instead. This
makes the costing both simpler and more robust.
Note that this swings costs for illegal shuffles pretty wildly as we
were previously sometimes hitting the adhoc code, and sometimes falling
through into generic scalarization costing. I don't know that any of the
costs for the individual tests in tree are significant, but the test
which which triggered me finding this was reported to me by Alexey
reduced from something triggering a bad choice in SLP for x264. So this
has the potential to be somewhat high impact.
Commit: 7c4cb0e8368583bdd48a59b5dd0e9d881cffa3a6
https://github.com/llvm/llvm-project/commit/7c4cb0e8368583bdd48a59b5dd0e9d881cffa3a6
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
Log Message:
-----------
Fix build error introduced by 1c722fc
The change built before merge, but apparently a constness change landed
since I posted this for review.
Commit: 710ffb69bfdc9281eaaad267ad85ca60ddbb94f0
https://github.com/llvm/llvm-project/commit/710ffb69bfdc9281eaaad267ad85ca60ddbb94f0
Author: Daniel Thornburgh <dthorn at google.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M libc/fuzzing/__support/CMakeLists.txt
R libc/fuzzing/__support/fake_heap.s
M libc/fuzzing/__support/freelist_heap_fuzz.cpp
M libc/test/src/__support/CMakeLists.txt
R libc/test/src/__support/fake_heap.s
M libc/test/src/__support/freelist_heap_test.cpp
Log Message:
-----------
[libc] Fix warnings for freelist_heap_test/fuzz (#136634)
Fixes #122367
Commit: 5ebf08cd9a1d4b2697a0d3ad588ddbdc553362dc
https://github.com/llvm/llvm-project/commit/5ebf08cd9a1d4b2697a0d3ad588ddbdc553362dc
Author: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
A llvm/test/CodeGen/DirectX/legalize-lifetimes.ll
Log Message:
-----------
[DirectX] Allow llvm lifetime intrinsics to pass on to the DirectX backend (#136622)
fixes #136620
It was determined that the lifetime intrinsics generated by clang are
likely more correct than the ones in DXC hence explaining the missing
lifetimes between the IR diffs.
As such we are legalizing lllvm lifetime intrinsics by letting them all
pass on through.
Commit: fcb309715e4bd46d96dda7bdf99291ebf394d130
https://github.com/llvm/llvm-project/commit/fcb309715e4bd46d96dda7bdf99291ebf394d130
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/test/TableGen/trydecode-emission.td
M llvm/test/TableGen/trydecode-emission2.td
M llvm/test/TableGen/trydecode-emission3.td
M llvm/test/TableGen/trydecode-emission4.td
Log Message:
-----------
[LLVM][TableGen] Do not test fixed opcode value in DecoderEmitter tests (#136724)
Fix test to allow any opcode values for the OPC_Decode checks, since the
specific opcode value can be different for downstream configurations.
Commit: 800d949bb315349a116a980e99d0f36645ffefd3
https://github.com/llvm/llvm-project/commit/800d949bb315349a116a980e99d0f36645ffefd3
Author: Callum Fare <callum at codeplay.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M offload/liboffload/API/APIDefs.td
M offload/liboffload/API/Common.td
M offload/liboffload/API/Device.td
A offload/liboffload/API/Event.td
A offload/liboffload/API/Kernel.td
A offload/liboffload/API/Memory.td
M offload/liboffload/API/OffloadAPI.td
M offload/liboffload/API/Platform.td
A offload/liboffload/API/Program.td
A offload/liboffload/API/Queue.td
M offload/liboffload/API/README.md
M offload/liboffload/include/OffloadImpl.hpp
M offload/liboffload/include/generated/OffloadAPI.h
M offload/liboffload/include/generated/OffloadEntryPoints.inc
M offload/liboffload/include/generated/OffloadFuncs.inc
M offload/liboffload/include/generated/OffloadImplFuncDecls.inc
M offload/liboffload/include/generated/OffloadPrint.hpp
M offload/liboffload/src/OffloadImpl.cpp
M offload/liboffload/src/OffloadLib.cpp
M offload/test/tools/offload-tblgen/entry_points.td
M offload/test/tools/offload-tblgen/functions_ranged_param.td
M offload/test/tools/offload-tblgen/print_enum.td
M offload/test/tools/offload-tblgen/print_function.td
M offload/test/tools/offload-tblgen/type_tagged_enum.td
M offload/tools/offload-tblgen/APIGen.cpp
M offload/tools/offload-tblgen/EntryPointGen.cpp
M offload/tools/offload-tblgen/PrintGen.cpp
M offload/tools/offload-tblgen/RecordTypes.hpp
M offload/unittests/OffloadAPI/CMakeLists.txt
M offload/unittests/OffloadAPI/common/Environment.cpp
M offload/unittests/OffloadAPI/common/Environment.hpp
M offload/unittests/OffloadAPI/common/Fixtures.hpp
R offload/unittests/OffloadAPI/device/olGetDevice.cpp
R offload/unittests/OffloadAPI/device/olGetDeviceCount.cpp
M offload/unittests/OffloadAPI/device/olGetDeviceInfo.cpp
M offload/unittests/OffloadAPI/device/olGetDeviceInfoSize.cpp
A offload/unittests/OffloadAPI/device/olIterateDevices.cpp
A offload/unittests/OffloadAPI/device_code/CMakeLists.txt
A offload/unittests/OffloadAPI/device_code/bar.c
A offload/unittests/OffloadAPI/device_code/foo.c
A offload/unittests/OffloadAPI/kernel/olGetKernel.cpp
A offload/unittests/OffloadAPI/kernel/olLaunchKernel.cpp
A offload/unittests/OffloadAPI/memory/olMemAlloc.cpp
A offload/unittests/OffloadAPI/memory/olMemFree.cpp
A offload/unittests/OffloadAPI/memory/olMemcpy.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatform.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatformCount.cpp
M offload/unittests/OffloadAPI/platform/olGetPlatformInfo.cpp
M offload/unittests/OffloadAPI/platform/olGetPlatformInfoSize.cpp
M offload/unittests/OffloadAPI/platform/olPlatformInfo.hpp
A offload/unittests/OffloadAPI/program/olCreateProgram.cpp
A offload/unittests/OffloadAPI/program/olDestroyProgram.cpp
A offload/unittests/OffloadAPI/queue/olCreateQueue.cpp
A offload/unittests/OffloadAPI/queue/olDestroyQueue.cpp
A offload/unittests/OffloadAPI/queue/olWaitQueue.cpp
Log Message:
-----------
[Offload] Implement the remaining initial Offload API (#122106)
Implement the complete initial version of the Offload API, to the extent
that is usable for simple offloading programs. Tested with a basic SYCL
program.
As far as possible, these are simple wrappers over existing
functionality in the plugins.
* Allocating and freeing memory (host, device, shared).
* Creating a program
* Creating a queue (wrapper over asynchronous stream resource)
* Enqueuing memcpy operations
* Enqueuing kernel executions
* Waiting on (optional) output events from the enqueue operations
* Waiting on a queue to finish
Objects created with the API have reference counting semantics to handle
their lifetime. They are created with an initial reference count of 1,
which can be incremented and decremented with retain and release
functions. They are freed when their reference count reaches 0. Platform
and device objects are not reference counted, as they are expected to
persist as long as the library is in use, and it's not meaningful for
users to create or destroy them.
Tests have been added to `offload.unittests`, including device code for
testing program and kernel related functionality.
The API should still be considered unstable and it's very likely we will
need to change the existing entry points.
Commit: b5eae19f64d5a53cd85ece433f448be1fd4c8539
https://github.com/llvm/llvm-project/commit/b5eae19f64d5a53cd85ece433f448be1fd4c8539
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M flang/include/flang/Lower/DirectivesCommon.h
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/test/Semantics/OpenMP/atomic-hint-clause.f90
M flang/test/Semantics/OpenMP/critical-hint-clause.f90
M llvm/include/llvm/Frontend/OpenMP/OMP.td
Log Message:
-----------
[flang][OpenMP] Introduce OmpHintClause, simplify OmpAtomicClause (#136311)
The OmpAtomicClause is a variant of a few specific clauses that are used
on the ATOMIC construct. The HINT clause, however, was represented as a
generic OmpClause, which somewhat complicated the analysis of an
OmpAtomicClause.
Introduce OmpHintClause to represent the contents of the HINT clause,
and use it on OmpAtomicClause similarly to how OmpFailClause is used.
Commit: 80872d7a32cd335a7964df95e9fbcdee43eb1ad4
https://github.com/llvm/llvm-project/commit/80872d7a32cd335a7964df95e9fbcdee43eb1ad4
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
A clang/test/CIR/IR/stack-save-restore.cir
A clang/test/CIR/Lowering/stack-save-restore.cir
Log Message:
-----------
[CIR] Upstream StackSave and StackRestoreOp (#136426)
This change adds support for StackSave and StackRestoreOp as a preliminary patch of VLA support
Commit: 2dca9e80ffc7f300129fb8e5fcc8d1ee60a157e0
https://github.com/llvm/llvm-project/commit/2dca9e80ffc7f300129fb8e5fcc8d1ee60a157e0
Author: YongKang Zhu <yongzhu at fb.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M bolt/test/link_fdata.py
Log Message:
-----------
[BOLT][test] Resolve symlink for nm tool (NFC) (#136722)
Handle the case where nm could be a symlink to llvm-nm.
Commit: 718a50963ca4b3860fe1cb638d6030b8ae9e818c
https://github.com/llvm/llvm-project/commit/718a50963ca4b3860fe1cb638d6030b8ae9e818c
Author: Paul Kirth <paulkirth at google.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang-tools-extra/clang-doc/BitcodeWriter.cpp
M clang-tools-extra/clang-doc/HTMLGenerator.cpp
M clang-tools-extra/clang-doc/Serialize.cpp
Log Message:
-----------
[clang-doc] Fix clang-tidy naming diagnostics (#136444)
In quite a few places we were not following the project naming
conventions. This patch applies clang-tidy fixes, and updates
some additional names to follow more typical project wide patterns.
Commit: e5128332dbb3bedfa30633fad30a52f5b1567d70
https://github.com/llvm/llvm-project/commit/e5128332dbb3bedfa30633fad30a52f5b1567d70
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M mlir/lib/Dialect/Vector/TransformOps/VectorTransformOps.cpp
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul-mixed-types.mlir
Log Message:
-----------
[mlir][vector] Update ApplyVectorReductionToContractPatternsOp (#136699)
This PR removes the use of `populateSinkVectorOpsPatterns` from the
definition of:
* `transform.apply_patterns.vector.reduction_to_contract`
As of #131462, there is now a dedicated transform op for this pattern:
* `transform.apply_patterns.vector.sink_op`
Given that, we should now use the new TD op directly instead of relying
on unrelated TD ops to include it.
NOTE TO DOWNSTREAM USERS:
Please add the following to your TD scripts:
* `transform.apply_patterns.vector.sink_op`
See the updated test for an example.
Commit: 11d5c4dcccf19b5c01742a2a402889da89783630
https://github.com/llvm/llvm-project/commit/11d5c4dcccf19b5c01742a2a402889da89783630
Author: Paul Kirth <paulkirth at google.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang-tools-extra/clang-doc/Serialize.cpp
Log Message:
-----------
[clang-doc][NFC] Use isa<> over dyn_cast (#136445)
Commit: 694c52cef5d24673836cb2199598445753a96864
https://github.com/llvm/llvm-project/commit/694c52cef5d24673836cb2199598445753a96864
Author: Paul Kirth <paulkirth at google.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/include/llvm/IR/DiagnosticInfo.h
M llvm/lib/IR/DiagnosticInfo.cpp
M llvm/lib/Transforms/Utils/MisExpect.cpp
Log Message:
-----------
[llvm][misexpect][NFC] Fix Twine usage (#136446)
Commit: bf33f03f5a728d79bd828664cd155903a885a391
https://github.com/llvm/llvm-project/commit/bf33f03f5a728d79bd828664cd155903a885a391
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Move Ingredient accesses closer to uses (NFC).
Move accessing Ingredient closer to its only use for
VPWidenMemoryRecipes.
Commit: dee96a3d078f382b870b62146e38ab1f4a1e596b
https://github.com/llvm/llvm-project/commit/dee96a3d078f382b870b62146e38ab1f4a1e596b
Author: Paul Kirth <paulkirth at google.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/IR/ProfDataUtils.cpp
Log Message:
-----------
[llvm][IR][NFC] Apply clang-tidy fixes to ProfDataUtils (#136447)
A few functions in the TU could be made static, and a loop variable name
could be changed to avoid warnings.
Commit: d7460da554e3d5efdc5b9db3901078c9bf650fad
https://github.com/llvm/llvm-project/commit/d7460da554e3d5efdc5b9db3901078c9bf650fad
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M mlir/utils/generate-test-checks.py
Log Message:
-----------
[mlir][utils] Update generate-test-checks.py (#136721)
Following #128083, all `CHECK-SAME` lines generated by
generate-test-checks.py use a strict regex:
```mlir
// CHECK-SAME: %[[VAL_0:[0-9]+|[a-zA-Z$._-][a-zA-Z0-9$._-]*]]: memref<128x256x512xf32>,
```
However, in most cases this strict form is unnecessary and can obscure
readability. In such cases, the following would be sufficient:
```mlir
// CHECK-SAME: %[[VAL_0:.*]]: memref<128x256x512xf32>,
```
This patch adds a command-line flag to make the strict mode optional. To
enable strict regex matching, use:
```bash
generate-test-checks.py --strict_name_re=true file.mlir
```
Commit: 50320504c852e0cb3a8b1e43e85c9137219d44fd
https://github.com/llvm/llvm-project/commit/50320504c852e0cb3a8b1e43e85c9137219d44fd
Author: Benson Chu <bchu at localhost.localdomain>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/SemaARM.h
M clang/lib/CodeGen/Targets/ARM.cpp
M clang/lib/Sema/SemaARM.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
A clang/test/CodeGen/arm-interrupt-save-fp-attr-status-regs.c
A clang/test/CodeGen/arm-interrupt-save-fp-attr.c
M clang/test/Sema/arm-interrupt-attr.c
A clang/test/Sema/arm-interrupt-save-fp-attr.c
M llvm/include/llvm/IR/IntrinsicsARM.td
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
M llvm/lib/Target/ARM/ARMCallingConv.td
M llvm/lib/Target/ARM/ARMFrameLowering.cpp
M llvm/lib/Target/ARM/ARMFrameLowering.h
M llvm/lib/Target/ARM/ARMInstrVFP.td
M llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
M llvm/lib/Target/ARM/ARMRegisterInfo.td
A llvm/test/CodeGen/ARM/interrupt-save-fp-attr-status-regs.mir
A llvm/test/CodeGen/ARM/interrupt-save-fp-attr.ll
Log Message:
-----------
[ARM][Thumb] Save FPSCR + FPEXC for save-vfp attribute
FPSCR and FPEXC will be stored in FPStatusRegs, after GPRCS2 has been
saved.
- GPRCS1
- GPRCS2
- FPStatusRegs (new)
- DPRCS
- GPRCS3
- DPRCS2
FPSCR is present on all targets with a VFP, but the FPEXC register is
not present on Cortex-M devices, so different amounts of bytes are
being pushed onto the stack depending on our target, which would
affect alignment for subsequent saves.
DPRCS1 will sum up all previous bytes that were saved, and will emit
extra instructions to ensure that its alignment is correct. My
assumption is that if DPRCS1 is able to correct its alignment to be
correct, then all subsequent saves will also have correct alignment.
Avoid annotating the saving of FPSCR and FPEXC for functions marked
with the interrupt_save_fp attribute, even though this is done as part
of frame setup. Since these are status registers, there really is no
viable way of annotating this. Since these aren't GPRs or DPRs, they
can't be used with .save or .vsave directives. Instead, just record
that the intermediate registers r4 and r5 are saved to the stack
again.
Co-authored-by: Jake Vossen <jake at vossen.dev>
Co-authored-by: Alan Phipps <a-phipps at ti.com>
Commit: 32fd97c61d82b6cc0edec0ac389d69add9e64aab
https://github.com/llvm/llvm-project/commit/32fd97c61d82b6cc0edec0ac389d69add9e64aab
Author: Austin Schuh <AustinSchuh at users.noreply.github.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
R clang/test/CodeGen/Inputs/cuda.h
R clang/test/CodeGen/nvptx-surface.cu
M clang/test/CodeGenCUDA/Inputs/cuda.h
M clang/test/CodeGenCUDA/correctly-rounded-div.cu
A clang/test/CodeGenCUDA/nvptx-surface.cu
M clang/test/CodeGenCUDA/offloading-entries.cu
M clang/test/CodeGenCUDA/profile-coverage-mapping.cu
M clang/test/CodeGenCUDA/propagate-attributes.cu
Log Message:
-----------
cuda clang: Move nvptx-surface.cu test to CodeGenCUDA (#134758)
Signed-off-by: Austin Schuh <austin.linux at gmail.com>
Commit: d6622df115c0de92bf8fc10f8787345ff96b26cc
https://github.com/llvm/llvm-project/commit/d6622df115c0de92bf8fc10f8787345ff96b26cc
Author: Martin Storsjö <martin at martin.st>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array.pass.cpp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete.pass.cpp
Log Message:
-----------
[libcxx] [test] Extend mingw workarounds for armv7/aarch64 too (#136419)
This would be more convenient, if ADDITIONAL_COMPILE_FLAGS(target=...)
could be set with a regular expression, just like within e.g. XFAIL
lines.
Commit: ce2b3ce3b6f707b8941dcdbf2c3a9be9fe5fa01b
https://github.com/llvm/llvm-project/commit/ce2b3ce3b6f707b8941dcdbf2c3a9be9fe5fa01b
Author: ShatianWang <38512325+ShatianWang at users.noreply.github.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M bolt/lib/Passes/ProfileQualityStats.cpp
A bolt/test/X86/profile-quality-reporting-small-binary.s
M bolt/test/X86/profile-quality-reporting.test
Log Message:
-----------
[BOLT] Improve profile quality reporting (#130810)
Improve profile quality reporting by 1) fixing a format issue for small
binaries, 2) adding new stats for exception handling usage, 3) excluding
selected blocks when computing the CFG flow conservation score.
More specifically for 3), we are excluding blocks that satisfy at least
one of the following characteristics: a) is a landing pad, b) has at
least one landing pad with non-zero execution counts, c) ends with a
recursive call. The reason for a) and b) is because the thrower -->
landing pad edges are not explicitly represented in the CFG. The reason
for c) is because the call-continuation fallthrough edge count is not
important in case of recursive calls.
Modified test `bolt/test/X86/profile-quality-reporting.test`.
Added test `bolt/test/X86/profile-quality-reporting-small-binary.s`.
Commit: 5e6747686dc2eea4aa988f61db567c4f67a7421e
https://github.com/llvm/llvm-project/commit/5e6747686dc2eea4aa988f61db567c4f67a7421e
Author: Shafik Yaghmour <shafik.yaghmour at intel.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/lib/Basic/DiagnosticIDs.cpp
Log Message:
-----------
[Clang] Remove use after move of lambda (#136728)
Static analysis flagged this use after move. It is undefined behavior
and I don't see any possible performance gains here to attempt to do
anything else but simply remove it.
Commit: f5564895ea8a9e09744826c9fa918a6fe0d2e478
https://github.com/llvm/llvm-project/commit/f5564895ea8a9e09744826c9fa918a6fe0d2e478
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M mlir/lib/Transforms/Utils/DialectConversion.cpp
Log Message:
-----------
[mlir] Fix a warning
This patch fixes:
mlir/lib/Transforms/Utils/DialectConversion.cpp:2104:9: error:
unused variable 'rewriterImpl' [-Werror,-Wunused-variable]
Commit: 66b2c343541a914e591aeae7091b97564cf534a7
https://github.com/llvm/llvm-project/commit/66b2c343541a914e591aeae7091b97564cf534a7
Author: Adrian Prantl <aprantl at apple.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M lldb/include/lldb/Symbol/CompilerType.h
M lldb/include/lldb/Symbol/TypeSystem.h
Log Message:
-----------
[lldb] Clarify the documentation for GetIndexOfChildMemberWithName (#136633)
Commit: 6f1adbdb2b6f21d81e491c9ddd307fca0d183850
https://github.com/llvm/llvm-project/commit/6f1adbdb2b6f21d81e491c9ddd307fca0d183850
Author: Adrian Prantl <aprantl at apple.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M lldb/include/lldb/Core/Debugger.h
M lldb/include/lldb/Core/FormatEntity.h
M lldb/source/Core/CoreProperties.td
M lldb/source/Core/Debugger.cpp
M lldb/source/Core/FormatEntity.cpp
M lldb/test/API/functionalities/statusline/TestStatusline.py
Log Message:
-----------
[lldb] Make the statusline separator configurable (#136611)
And use this functionality to replace the ASCII "|" with the same
full-geight line-drawing character used in diagnostics rendering on a
color terminal.
Commit: 89a792e4e3f0464d071e71db0fd14d01e4aff971
https://github.com/llvm/llvm-project/commit/89a792e4e3f0464d071e71db0fd14d01e4aff971
Author: arun-thmn <arun.thangamani at intel.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/X86Vector/X86Vector.td
M mlir/include/mlir/Dialect/X86Vector/X86VectorDialect.h
M mlir/include/mlir/Dialect/X86Vector/X86VectorInterfaces.td
M mlir/lib/Dialect/X86Vector/IR/X86VectorDialect.cpp
M mlir/lib/Dialect/X86Vector/Transforms/LegalizeForLLVMExport.cpp
M mlir/test/Dialect/X86Vector/legalize-for-llvm.mlir
M mlir/test/Dialect/X86Vector/roundtrip.mlir
M mlir/test/Target/LLVMIR/x86vector.mlir
Log Message:
-----------
[mlir][x86vector] AVX Convert/Broadcast BF16 to F32 instructions (#135143)
Adds AVX broadcast and conversion from BF16 to packed F32. The
instructions that are added:
- `llvm.x86.vcvtneebf162ps128/256`
- `llvm.x86.vcvtneobf162ps128/256`
- `llvm.x86.vbcstnebf162ps128/256`
Commit: 21bc23e35efa6f285402c299e2991a8e991164cc
https://github.com/llvm/llvm-project/commit/21bc23e35efa6f285402c299e2991a8e991164cc
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/Dialect/IR/CIRTypes.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenRecordLayout.h
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.h
M clang/lib/CIR/CodeGen/CIRGenValue.h
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
M clang/test/CIR/CodeGen/struct.c
Log Message:
-----------
[CIR] Upstream support for accessing structure members (#136383)
This adds ClangIR support for accessing structure members. Access to
union members is deferred to a later change.
Commit: 2c2ba7efd4d5f270e7dea2e6a5f0a22bd7aaecd0
https://github.com/llvm/llvm-project/commit/2c2ba7efd4d5f270e7dea2e6a5f0a22bd7aaecd0
Author: Kiran Chandramohan <kiran.chandramohan at arm.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
A flang/docs/OpenMPSupport.md
M flang/docs/index.md
Log Message:
-----------
[Flang][OpenMP] Add OpenMP standards support doc (#132707)
Commit: 49b6c746b80cb0bd8e5735a2d154058efa18854a
https://github.com/llvm/llvm-project/commit/49b6c746b80cb0bd8e5735a2d154058efa18854a
Author: Prabhu Rajasekaran <prabhukr at google.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
Log Message:
-----------
[NFC][llvm] Remove duplicate isUEFI check (#136593)
In `X86MCTargetDesc.cpp` while fixing the handling of UEFI target in the
`createX86MCAsmInfo` function (#132461), the previous incorrect handling
of isUEFI was not removed. This patch cleans up that case.
Commit: afda4c295b1f8c4c4011358eddc1a08e17cd5b4d
https://github.com/llvm/llvm-project/commit/afda4c295b1f8c4c4011358eddc1a08e17cd5b4d
Author: zhijian lin <zhijian at ca.ibm.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll
M llvm/test/CodeGen/AArch64/optimize-cond-branch.ll
M llvm/test/CodeGen/AArch64/sve-extract-element.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/dead-machine-elim-after-dead-lane.ll
M llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll
M llvm/test/CodeGen/PowerPC/undef-args.ll
M llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
M llvm/test/CodeGen/VE/Vector/ticket-64420.ll
M llvm/test/CodeGen/X86/avx512-i1test.ll
M llvm/test/CodeGen/X86/bfloat.ll
M llvm/test/CodeGen/X86/clobber_frame_ptr.ll
M llvm/test/CodeGen/X86/concat-fpext-v2bf16.ll
M llvm/test/CodeGen/X86/jump_sign.ll
M llvm/test/CodeGen/X86/machine-trace-metrics-crash.ll
M llvm/test/CodeGen/X86/pr50254.ll
M llvm/test/CodeGen/X86/pr57673.ll
M llvm/test/CodeGen/X86/pr63108.ll
M llvm/test/CodeGen/X86/pr91005.ll
M llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
M llvm/test/CodeGen/X86/shift-combine.ll
M llvm/test/CodeGen/X86/shuffle-combine-crash.ll
M llvm/test/CodeGen/X86/shuffle-half.ll
M llvm/test/CodeGen/X86/swifterror.ll
M llvm/test/CodeGen/X86/tailcall-cgp-dup.ll
M llvm/test/CodeGen/X86/vaargs-prolog-insert.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
M llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
Log Message:
-----------
Reland [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode (#136701)
This patch addresses the signed/zero extension of poison by using a
poison value of the extended type instead of a constant zero of the
extended type.
Commit: d6a68be7af0e1cec95e5fb9442dc1867cbde9f8d
https://github.com/llvm/llvm-project/commit/d6a68be7af0e1cec95e5fb9442dc1867cbde9f8d
Author: modiking <mmo at nvidia.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/lib/Basic/Targets/NVPTX.cpp
M clang/test/CodeGen/target-data.c
M llvm/include/llvm/Support/NVPTXAddrSpace.h
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTX.h
M llvm/lib/Target/NVPTX/NVPTXAliasAnalysis.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.h
A llvm/test/CodeGen/NVPTX/addrspacecast-ptx64.ll
A llvm/test/CodeGen/NVPTX/distributed-shared-cluster.ll
M llvm/test/CodeGen/NVPTX/nvptx-aa.ll
M llvm/test/Transforms/InferAddressSpaces/NVPTX/isspacep.ll
Log Message:
-----------
[NVPTX] Add support for Shared Cluster Memory address space [1/2] (#135444)
Adds support for new Shared Cluster Memory Address Space
(SHARED_CLUSTER, addrspace 7). See
https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#distributed-shared-memory
for details.
1. Update address space structures and datalayout to contain the new
space
2. Add new intrinsics that use this new address space
3. Update NVPTX alias analysis
The existing intrinsics are updated in
https://github.com/llvm/llvm-project/pull/136768
Commit: 09147b4c3c5579e9d76aa090605ccc9b46e307f6
https://github.com/llvm/llvm-project/commit/09147b4c3c5579e9d76aa090605ccc9b46e307f6
Author: Ivan Butygin <ivan.butygin at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/include/mlir/Analysis/SliceAnalysis.h
M mlir/include/mlir/Conversion/GPUCommon/GPUCommonPass.h
M mlir/include/mlir/ExecutionEngine/SparseTensor/MapRef.h
M mlir/include/mlir/ExecutionEngine/SparseTensorRuntime.h
M mlir/include/mlir/Pass/PassManager.h
M mlir/include/mlir/Reducer/Tester.h
Log Message:
-----------
[mlir][nfc] Cleanup some unused headers (#136738)
Commit: e112dccc8ba49425c575a6b15325f2cbeef5c606
https://github.com/llvm/llvm-project/commit/e112dccc8ba49425c575a6b15325f2cbeef5c606
Author: Fabian Mora <fmora.dev at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/Ptr/IR/PtrAttrDefs.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrAttrs.h
M mlir/include/mlir/Dialect/Ptr/IR/PtrEnums.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrOps.h
M mlir/include/mlir/Dialect/Ptr/IR/PtrOps.td
M mlir/lib/Dialect/Ptr/IR/CMakeLists.txt
M mlir/lib/Dialect/Ptr/IR/PtrAttrs.cpp
M mlir/lib/Dialect/Ptr/IR/PtrDialect.cpp
A mlir/test/Dialect/Ptr/canonicalize.mlir
A mlir/test/Dialect/Ptr/ops.mlir
Log Message:
-----------
[mlir][ptr] Add the `ptradd` and `type_offset` ops, and `generic_space` attr (#136434)
This patch adds the `ptr.ptradd` and `ptr.type_offset` operations. Given
a `ptr` value these operations can be used to compute new addresses. For
example:
```mlir
func.func @ops0(%ptr: !ptr.ptr<#ptr.int_space>) -> !ptr.ptr<#ptr.int_space> {
%off = ptr.type_offset f32 : index
%res = ptr.ptradd %ptr, %off : !ptr.ptr<#ptr.int_space>, index
return %res : !ptr.ptr<#ptr.int_space>
}
```
Additionally, this patch also adds the `#ptr.generic_space`. This memory
space allows loading and storing values to all types.
---------
Co-authored-by: Mehdi Amini <joker.eph at gmail.com>
Co-authored-by: Tobias Gysi <tobias.gysi at nextsilicon.com>
Commit: a2be4543fc2c1cbd2f9dafade8c29475e7a37e51
https://github.com/llvm/llvm-project/commit/a2be4543fc2c1cbd2f9dafade8c29475e7a37e51
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/test/CodeGen/NVPTX/fp128-storage-type.ll
M llvm/test/CodeGen/NVPTX/i128-array.ll
M llvm/test/CodeGen/NVPTX/i128-retval.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test1.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test3.ll
M llvm/test/CodeGen/NVPTX/load-with-non-coherent-cache.ll
Log Message:
-----------
[NVPTX] Use v2.u64 to load/store 128-bit values (#136638)
Commit: 0797f708f52e5ab38845f18263de1b6d7c77c653
https://github.com/llvm/llvm-project/commit/0797f708f52e5ab38845f18263de1b6d7c77c653
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/include/clang/Frontend/CompilerInstance.h
M clang/lib/Frontend/CompilerInstance.cpp
Log Message:
-----------
[clang] Enable making `CompilerInstance` diagnostics thread-safe (#136601)
The `DiagnosticConsumer` interface is not thread-safe. To enable
thread-safety of `CompilerInstance` objects cloned from the same parent,
this PR allows passing an explicit `DiagnosticConsumer` to
`cloneForModuleCompile()`. This will be used from the dependency
scanner.
Commit: 7e86afa6526dc5e809a6d5f2c71a2b97c9713159
https://github.com/llvm/llvm-project/commit/7e86afa6526dc5e809a6d5f2c71a2b97c9713159
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/X86Vector/X86Vector.td
M mlir/include/mlir/Dialect/X86Vector/X86VectorDialect.h
M mlir/include/mlir/Dialect/X86Vector/X86VectorInterfaces.td
M mlir/lib/Dialect/X86Vector/IR/X86VectorDialect.cpp
M mlir/lib/Dialect/X86Vector/Transforms/LegalizeForLLVMExport.cpp
M mlir/test/Dialect/X86Vector/legalize-for-llvm.mlir
M mlir/test/Dialect/X86Vector/roundtrip.mlir
M mlir/test/Target/LLVMIR/x86vector.mlir
Log Message:
-----------
Revert "[mlir][x86vector] AVX Convert/Broadcast BF16 to F32 instructions" (#136781)
Reverts llvm/llvm-project#135143
This broke multiple bots, see PR.
Commit: a7dcedc5cf73bdeb4e3bb8cd8e32b65349b75b6e
https://github.com/llvm/llvm-project/commit/a7dcedc5cf73bdeb4e3bb8cd8e32b65349b75b6e
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvqdotq.ll
Log Message:
-----------
[RISCV] Add initial batch of test coverage for zvqdotq codegen
This is not complete coverage, but it's a starting point for working
on codegen for this extension.
Commit: 8ca8c404d30ab6fd567b6855ed2d790bfbac5435
https://github.com/llvm/llvm-project/commit/8ca8c404d30ab6fd567b6855ed2d790bfbac5435
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
M clang/test/Analysis/Checkers/WebKit/unretained-call-args-arc.mm
M clang/test/Analysis/Checkers/WebKit/unretained-call-args.mm
M clang/test/Analysis/Checkers/WebKit/unretained-local-vars-arc.mm
M clang/test/Analysis/Checkers/WebKit/unretained-local-vars.mm
Log Message:
-----------
[WebKit checkers] Treat global const variables as safe (#136170)
This PR makes WebKit checkers treat a variable with global storage as
safe instead of constraining to ones that start with k or _k.
Commit: 8dbf92e06a9f86ba256b537b2a1a99bce9dee765
https://github.com/llvm/llvm-project/commit/8dbf92e06a9f86ba256b537b2a1a99bce9dee765
Author: modiking <mmo at nvidia.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/test/CodeGen/NVPTX/addrspacecast-ptx64.ll
M llvm/test/CodeGen/NVPTX/distributed-shared-cluster.ll
Log Message:
-----------
[NVPTX] Fix ptxas tests from #135444 (#136782)
ptxas needs to be updated to the correct arch to match what llc is
outputting
Commit: 8c74dc1adf83d370e740e44ffe073487fd3b38d2
https://github.com/llvm/llvm-project/commit/8c74dc1adf83d370e740e44ffe073487fd3b38d2
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/test/Dialect/Affine/canonicalize.mlir
M mlir/test/Dialect/Affine/invalid.mlir
M mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir
Log Message:
-----------
[MLIR][Affine] Fix affine.apply verifier and add functionality to demote invalid symbols to dims (#128289)
Fixes: https://github.com/llvm/llvm-project/issues/120189,
https://github.com/llvm/llvm-project/issues/128403
Fix affine.apply verifier to reject symbolic operands that are valid
dims for affine purposes. This doesn't affect other users in other
contexts where the operands were neither valid dims or symbols (for eg.
in scf.for or other region ops). Otherwise, it was possible for
`-canonicalize` to have generated invalid IR when such
affine.apply ops were composed.
Introduce a method to demote a symbolic operand to a dimensional one
(the inverse of the current canonicalizePromotedSymbols). Demote
operands that could/should have been valid affine dimensional values
(affine loop IVs or their functions) from symbols to dims. This is a
general method that can be used to legalize a map + operands post
construction depending on its operands. Use it during
`canonicalizeMapOrSetAndOperands` so that pattern rewriter-based passes
are able to generate valid IR post folding. Users outside of affine
analyses/dialects remain unaffected.
In some cases, this change also leads to better simplified operands,
duplicates eliminated as shown in one of the test cases where the same
operand appeared as a symbol and as a dim.
This commit also fixes test cases where dimensional positions should have
been ideally used with affine.apply (for affine loop IVs for example).
Commit: 3d04da5bc022269b3238b2a84347dce7a7afd51b
https://github.com/llvm/llvm-project/commit/3d04da5bc022269b3238b2a84347dce7a7afd51b
Author: modiking <mmo at nvidia.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/test/CodeGenCUDA/builtins-sm90.cu
M llvm/docs/NVPTXUsage.rst
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/test/Assembler/auto_upgrade_nvvm_intrinsics.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk.ll
M llvm/test/CodeGen/NVPTX/distributed-shared-cluster.ll
M mlir/include/mlir/Dialect/LLVMIR/NVVMDialect.h
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/test/Target/LLVMIR/nvvm/tma_bulk_copy.mlir
Log Message:
-----------
[NVPTX] Add support for Shared Cluster Memory address space [2/2] (#136768)
Adds support for new Shared Cluster Memory Address Space
(SHARED_CLUSTER, addrspace 7). See
https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#distributed-shared-memory
for details.
Follow-up to https://github.com/llvm/llvm-project/pull/135444
1. Update existing codegen/intrinsics in LLVM and MLIR that now use this
address space
2. Auto-upgrade previous intrinsics that used SMEM (addrspace 3) but
were really taking in a shared cluster pointer to the new address space
Commit: 85b35a90770b6053f91d79ca685cdfa4bf6499a4
https://github.com/llvm/llvm-project/commit/85b35a90770b6053f91d79ca685cdfa4bf6499a4
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
Log Message:
-----------
[MLIR] Fix build failure introduced by 3d04da5bc022
Fix build failure in assert mode introduced by
8c74dc1adf83d370e740e44ffe073487fd3b38d2.
Commit: 4e679ea89cc68829c4b9efc73121467bee56519c
https://github.com/llvm/llvm-project/commit/4e679ea89cc68829c4b9efc73121467bee56519c
Author: Sergei Lebedev <185856+superbobry at users.noreply.github.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
Log Message:
-----------
[MLIR] [python] Fixed the signature of `_OperationBase.get_asm` (#136676)
It claimed to return an `io.StringIO` or an `io.BytesIO`, but it did in
fact return `str` or `bytes`.
Commit: 2484060ad970b692443a6a1e7d3bef2797aa751b
https://github.com/llvm/llvm-project/commit/2484060ad970b692443a6a1e7d3bef2797aa751b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
A llvm/test/CodeGen/RISCV/fold-mem-offset.mir
Log Message:
-----------
[RISCV] Clear kill flags after replaceRegWith in RISCVFoldMemOffset. (#136762)
Any kill flags that were present for the old register are not valid for
the replacement and the replacement may have extended the live range of
the replacement register.
Commit: 122e5151ba84560de824d46f7b636502d41f2aa0
https://github.com/llvm/llvm-project/commit/122e5151ba84560de824d46f7b636502d41f2aa0
Author: Peter Collingbourne <peter at pcc.me.uk>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Sema/BUILD.gn
Log Message:
-----------
gn build: Port d1cce66469d0 more
Commit: 4f71655b64a815143d2aedb22b8f423f7ce99e29
https://github.com/llvm/llvm-project/commit/4f71655b64a815143d2aedb22b8f423f7ce99e29
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Fix a bug in parsing C-style cast of lambdas (#136099)
Fix #135959
Commit: 9efabbbbe58bd8bc2141ba1c914f79376e09cbcf
https://github.com/llvm/llvm-project/commit/9efabbbbe58bd8bc2141ba1c914f79376e09cbcf
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/lib/Format/FormatTokenLexer.cpp
M clang/lib/Format/FormatTokenLexer.h
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Fix a bug in lexing C++ UDL ending in $ (#136476)
Fix #61612
Commit: 037657de7e5ccd4a37054829874a209b82fb8be7
https://github.com/llvm/llvm-project/commit/037657de7e5ccd4a37054829874a209b82fb8be7
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Correctly annotate kw_operator in using decls (#136545)
Fix #136541
Commit: afc030dd30e377ca7bf225a97179fa1b64eedd28
https://github.com/llvm/llvm-project/commit/afc030dd30e377ca7bf225a97179fa1b64eedd28
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/unittests/Format/FormatTestJS.cpp
Log Message:
-----------
[clang-format] Don't test stability if JS format test fails (#136662)
Commit: 68d89e931619ce5c9bc6fffcbe2d5b5268047f3c
https://github.com/llvm/llvm-project/commit/68d89e931619ce5c9bc6fffcbe2d5b5268047f3c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/TargetParser/RISCVISAInfo.cpp
Log Message:
-----------
[RISCV] Remove stale comment. NFC
Commit: 34a4c58018730736b940c4db4d694feed3266f52
https://github.com/llvm/llvm-project/commit/34a4c58018730736b940c4db4d694feed3266f52
Author: Michele Scandale <michele.scandale at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/include/clang/AST/Type.h
M clang/lib/AST/Type.cpp
M clang/lib/CodeGen/CGExpr.cpp
Log Message:
-----------
[clang] Rework `hasBooleanRepresentation`. (#136038)
This is a follow-up of 13aac46332f607a38067b5ddd466071683b8c255.
This commit adjusts the implementation of `hasBooleanRepresentation` to
be somewhat aligned to `hasIntegerRepresentation`.
In particular vector of booleans should be handled in
`hasBooleanRepresentation`, while `_Atomic(bool)` should not.
Commit: 141c14c9522ba2bf7472d660d64928b9982b5f6e
https://github.com/llvm/llvm-project/commit/141c14c9522ba2bf7472d660d64928b9982b5f6e
Author: tangaac <tangyan01 at loongson.cn>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
A llvm/test/CodeGen/LoongArch/lasx/widen-shuffle-mask.ll
A llvm/test/CodeGen/LoongArch/lsx/widen-shuffle-mask.ll
Log Message:
-----------
[LoongArch] Pre-commit for widen shuffle mask (#136544)
Commit: 7547ad3a7bc1e249c240512438eb39581f58c8ef
https://github.com/llvm/llvm-project/commit/7547ad3a7bc1e249c240512438eb39581f58c8ef
Author: lntue <lntue at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M libc/src/math/generic/expm1f.cpp
Log Message:
-----------
[libc][math] Skip checking for exceptional values in expm1f when LIBC_MATH_SKIP_ACCURATE_PASS is set. (#130968)
Commit: 439f16a7e12f1aece321266e4fce760841bfcdf1
https://github.com/llvm/llvm-project/commit/439f16a7e12f1aece321266e4fce760841bfcdf1
Author: Christian Sigg <csigg at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] Port e112dccc8ba49425c575a6b15325f2cbeef5c606.
Commit: 3ccfbc8a002e1e0f64b5408d26bc42282afc194b
https://github.com/llvm/llvm-project/commit/3ccfbc8a002e1e0f64b5408d26bc42282afc194b
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M lldb/source/Core/Debugger.cpp
M lldb/test/API/functionalities/statusline/TestStatusline.py
Log Message:
-----------
[lldb] Make sure changing the separator takes immediate effect (#136779)
The setter is only used when changing the setting programmatically. When
using the settings command, we need to monitor SetPropertyValue.
Commit: 7b6801574d978ef418dd76257478cbbe5866b09f
https://github.com/llvm/llvm-project/commit/7b6801574d978ef418dd76257478cbbe5866b09f
Author: Henrich Lauko <xlauko at mail.muni.cz>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
Log Message:
-----------
[CIR] Infer MLIRContext in attr builders when possible (#136741)
Mirrors incubator changes from https://github.com/llvm/clangir/pull/1582
Commit: 5080a0251fe3352d26560075a9b3b8c9acb13d23
https://github.com/llvm/llvm-project/commit/5080a0251fe3352d26560075a9b3b8c9acb13d23
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
A llvm/test/CodeGen/RISCV/pr101786.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/X86/ispow2.ll
A llvm/test/CodeGen/X86/pr94829.ll
M llvm/test/CodeGen/X86/vector-popcnt-128.ll
M llvm/test/CodeGen/X86/vector-popcnt-256-ult-ugt.ll
M llvm/test/CodeGen/X86/vector-popcnt-256.ll
M llvm/test/CodeGen/X86/vector-popcnt-512-ult-ugt.ll
M llvm/test/CodeGen/X86/vector-popcnt-512.ll
A llvm/test/Transforms/CodeGenPrepare/unfold-pow2-test-vec.ll
A llvm/test/Transforms/CodeGenPrepare/unfold-pow2-test.ll
Log Message:
-----------
[CodeGenPrepare] Unfold slow ctpop when used in power-of-two test (#102731)
DAG combiner already does this transformation, but in some cases it does
not have a chance because either CodeGenPrepare or SelectionDAGBuilder
move icmp to a different basic block.
https://alive2.llvm.org/ce/z/ARzh99
Fixes #94829
Pull Request: https://github.com/llvm/llvm-project/pull/102731
Commit: 1a78ef9a9eddd73de7932f5c33a7a7ad7e8b1806
https://github.com/llvm/llvm-project/commit/1a78ef9a9eddd73de7932f5c33a7a7ad7e8b1806
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpState.cpp
M clang/lib/AST/ByteCode/InterpState.h
M clang/test/AST/ByteCode/c.c
M clang/test/AST/ByteCode/cxx11.cpp
M clang/test/AST/ByteCode/cxx23.cpp
M clang/test/AST/ByteCode/cxx26.cpp
Log Message:
-----------
[clang][bytecode] Allow casts from void* only in std::allocator calls (#136714)
Otherwise, add the missing diagnostic.
Commit: 832ca744f2f25a7a5334f2f04380c84e41f71678
https://github.com/llvm/llvm-project/commit/832ca744f2f25a7a5334f2f04380c84e41f71678
Author: Jim Lin <jim at andestech.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/test/Driver/riscv-cpus.c
M clang/test/Misc/target-invalid-cpu-note/riscv.c
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/RISCVProcessors.td
Log Message:
-----------
[RISCV] Add Andes N45/NX45 processor definition (#136670)
Andes N45/NX45 are 32/64bit in-order dual-issue 8-stage pipeline CPU
architecture implementing the RV[32|64]IMAFDC_Zba_Zbb_Zbs ISA
extensions. They are developed by Andes Technology
https://www.andestech.com, a RISC-V IP provider.
The overviews for N45/NX45:
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-n45/
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-nx45/
Scheduling model will be implemented in a later PR.
Commit: 30c47147262523663892836fee42e02f8f9366f5
https://github.com/llvm/llvm-project/commit/30c47147262523663892836fee42e02f8f9366f5
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/utils/generate-test-checks.py
Log Message:
-----------
[mlir][utils] Update generate-test-checks.py (#136757)
At the moment, the `CHECK-SAME` lines generated by
"generate-test-checks.py" (i.e. check-lines that correspond to the
preceeding `CHECK-LABEL` line) are indented to match the label length.
For example,
```mlir
func.func @batch_reduce_matmul_bcast_k_to_fill_missing_dims_A(%arg0: memref<5xf32>, %arg1: memref<2x5x7xf32>, %arg2: memref<3x7xf32>) {
linalg.batch_reduce_matmul indexing_maps = (...)
}
```
will lead to the following:
```mlir
// CHECK-LABEL: func.func @batch_reduce_matmul_bcast_k_to_fill_missing_dims_A(
// CHECK-SAME: %[[VAL_0:[0-9]+|[a-zA-Z$._-][a-zA-Z0-9$._-]*]]: memref<5xf32>,
// CHECK-SAME: %[[VAL_1:[0-9]+|[a-zA-Z$._-][a-zA-Z0-9$._-]*]]: memref<2x5x7xf32>,
// CHECK-SAME: %[[VAL_2:[0-9]+|[a-zA-Z$._-][a-zA-Z0-9$._-]*]]: memref<3x7xf32>) {
// CHECK: linalg.batch_reduce_matmul indexing_maps = (...)
```
This indentation is unnecasarilly deep. With this change, for labales
that are longer than 20 chars, the indentation is trimmed to 4 spaces:
```mlir
// CHECK-LABEL: func.func @batch_reduce_matmul_bcast_k_to_fill_missing_dims_A(
// CHECK-SAME: %[[VAL_0:[0-9]+|[a-zA-Z$._-][a-zA-Z0-9$._-]*]]: memref<5xf32>,
// CHECK-SAME: %[[VAL_1:[0-9]+|[a-zA-Z$._-][a-zA-Z0-9$._-]*]]: memref<2x5x7xf32>,
// CHECK-SAME: %[[VAL_2:[0-9]+|[a-zA-Z$._-][a-zA-Z0-9$._-]*]]: memref<3x7xf32>) {
// CHECK: linalg.batch_reduce_matmul indexing_maps = (...)
```
Commit: 665914fea1433409015a87fef2837218bcd21460
https://github.com/llvm/llvm-project/commit/665914fea1433409015a87fef2837218bcd21460
Author: Mythreya <git at mythreya.dev>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang-tools-extra/clangd/InlayHints.cpp
M clang-tools-extra/clangd/InlayHints.h
M clang-tools-extra/clangd/unittests/InlayHintTests.cpp
Log Message:
-----------
[clangd] Improve `BlockEnd` inlayhint presentation (#136106)
* Only show for blocks 10 lines or taller (including braces)
* Add parens for function call: "// if foo" -> "// if foo()" or "// if foo(...)"
* Print literal nullptr
* Escaping for abbreviated strings
Fixes https://github.com/clangd/clangd/issues/1807.
Based on the original PR at https://github.com/llvm/llvm-project/pull/72345.
Co-authored-by: daiyousei-qz <qyzheng2 at outlook.com>
Commit: 98b6f8dc699d789d834e5b6d810ed217f560aad0
https://github.com/llvm/llvm-project/commit/98b6f8dc699d789d834e5b6d810ed217f560aad0
Author: David Green <david.green at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/Support/InstructionCost.h
M llvm/include/llvm/Transforms/Utils/UnrollLoop.h
M llvm/lib/Analysis/CostModel.cpp
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Transforms/IPO/FunctionSpecialization.cpp
M llvm/lib/Transforms/IPO/PartialInlining.cpp
M llvm/lib/Transforms/Scalar/ConstantHoisting.cpp
M llvm/lib/Transforms/Scalar/LoopDataPrefetch.cpp
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
M llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/unittests/Support/InstructionCostTest.cpp
Log Message:
-----------
[CostModel] Remove optional from InstructionCost::getValue() (#135596)
InstructionCost is already an optional value, containing an Invalid
state that can be checked with isValid(). There is little point in
returning another optional from getValue(). Most uses do not make use of
it being a std::optional, dereferencing the value directly (either
isValid has been checked previously or the Cost is assumed to be valid).
The one case that does in AMDGPU used value_or which has been replaced
by a isValid() check.
Commit: ca3a5d37ef64668234cbce7236dd640a98e2d687
https://github.com/llvm/llvm-project/commit/ca3a5d37ef64668234cbce7236dd640a98e2d687
Author: jeremyd2019 <github at jdrake.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/cxa-atexit.cpp
Log Message:
-----------
[Clang] [Driver] use __cxa_atexit by default on Cygwin. (#135701)
GCC on Cygwin and MSYS2 are built with --enable-__cxa_atexit.
Adjust test to expect this change.
Commit: 1a99f7981f16461dc8e9add411abd1218435320e
https://github.com/llvm/llvm-project/commit/1a99f7981f16461dc8e9add411abd1218435320e
Author: Luke Lau <luke at igalia.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
Log Message:
-----------
[RISCV] Add tests for fixed-length vwadd[u].{w,v}v with disjoint or. NFC
Commit: da8f2d52423bb82b5d4e75cff3018704effe044f
https://github.com/llvm/llvm-project/commit/da8f2d52423bb82b5d4e75cff3018704effe044f
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
Revert "[clang-format] Allow breaking before kw___attribute (#128623)"
This reverts commit 8fc8a84e23471fe56214e68706addc712b5a2949, which caused a
regression.
Fixes #136675.
Commit: dfc60b2ceb50e75dc07bdda18ae74695f18b370c
https://github.com/llvm/llvm-project/commit/dfc60b2ceb50e75dc07bdda18ae74695f18b370c
Author: Christian Sigg <csigg at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] Also add SideEffectInterfaces dep to PtrDialect.
Fix for port of e112dcc.
Commit: 82049310385d5222527cf7d12984bd8d4f955dd1
https://github.com/llvm/llvm-project/commit/82049310385d5222527cf7d12984bd8d4f955dd1
Author: Luke Lau <luke at igalia.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
Log Message:
-----------
[RISCV] Add disjoint or patterns for vwadd[u].v{v,x} (#136716)
DAGCombiner::hoistLogicOpWithSameOpcodeHands will hoist
(or disjoint (ext a), (ext b)) -> (ext (or disjoint a, b))
So this adds patterns to match vwadd[u].v{v,x} in this case.
We have to teach the combine to preserve the disjoint flag.
Commit: dd3de590ebd63566a1a54eb0e2140c433a9add84
https://github.com/llvm/llvm-project/commit/dd3de590ebd63566a1a54eb0e2140c433a9add84
Author: David Green <david.green at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Analysis/InlineSizeEstimatorAnalysis.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
Log Message:
-----------
[CostModel] Fix InlineSizeEstimatorAnalysis after #135596
Fix a reference to getValue() being optional in InlineSizeEstimatorAnalysis, a
file that is not included in the default build. A "warning: enumerated and
non-enumerated type in conditional expression" warning is fixed in AMDGPU too.
Commit: ae47f2533709058d3442a34af783d8cd721b4177
https://github.com/llvm/llvm-project/commit/ae47f2533709058d3442a34af783d8cd721b4177
Author: Arseniy Zaostrovnykh <necto.ne at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/docs/StandardCPlusPlusModules.rst
Log Message:
-----------
[docs] Fix the use of word "dependent" and other typos in the C++ Modules Doc (#136719)
"Dependant BMI" / "Dependent BMI" was used incorrectly in the
documentation:
"Dependent BMI" refers to a BMI that depends on the current TU, but it
was used for the BMI that current TU depends on.
I replaced all the mentions with "BMI dependency".
Commit: d0cd6f3b9339326af01549ee09f17a6e9b54f505
https://github.com/llvm/llvm-project/commit/d0cd6f3b9339326af01549ee09f17a6e9b54f505
Author: David Green <david.green at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/arm64-tbl.ll
Log Message:
-----------
[AArch64] Fix tryToConvertShuffleOfTbl2ToTbl4 with non-buildvector input operands. (#135961)
It looks like this code is only considering buildvector inputs,
expecting the inputs to have at least 16 operands. This adds a check to
make sure that is true.
Fixes #135950
Commit: 91edbe223177504cf878340f37a36dfcee349cab
https://github.com/llvm/llvm-project/commit/91edbe223177504cf878340f37a36dfcee349cab
Author: wanglei <wanglei at loongson.cn>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
Log Message:
-----------
[lldb][LoongArch] Fix expression function call failure
After upgrading the default code model from small to medium on
LoongArch, function calls using expression may fail. This is because the
function call instruction has changed from `bl` to `pcalau18i + jirl`,
but `RuntimeDyld` does not handle out-of-range jumps for this
instruction sequence.
This patch fixes: #136561
Reviewed By: SixWeining
Pull Request: https://github.com/llvm/llvm-project/pull/136563
Commit: 8a57df6a5210d0c54ed482eb7230b7689a1f9cb9
https://github.com/llvm/llvm-project/commit/8a57df6a5210d0c54ed482eb7230b7689a1f9cb9
Author: Allin Lee <60502081+AllinLeeYL at users.noreply.github.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/IR/Value.h
M llvm/lib/IR/Value.cpp
A llvm/test/tools/llvm-extract/extract-unnamed-bb.ll
M llvm/tools/llvm-extract/llvm-extract.cpp
Log Message:
-----------
[llvm-extract] support unnamed bbs. (#135140)
Dear developer:
I have recently working with LLVM IR and I want to isolate basic blocks
using the command "llvm-extract". However, I found that the command
option "llvm-extract --bb func_name:bb_name" will only function when
dumping source code into IRs with options "-fno-discard-value-names".
That is to say, the "llvm-extract" command cannot support unnamed basic
blocks, which is a default output of the compiler. So, I made these
changes and hope they will make LLVM better.
Best regards,
Co-authored-by: Yilin Li <allinleeme at gmail.com>
Commit: 6db447f824d46956172b104f08105b25f9428f55
https://github.com/llvm/llvm-project/commit/6db447f824d46956172b104f08105b25f9428f55
Author: Iris Shi <0.0 at owo.li>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/test/Transforms/InstCombine/clamp-to-minmax.ll
A llvm/test/Transforms/InstCombine/max-min-canonicalize.ll
M llvm/test/Transforms/InstCombine/max_known_bits.ll
M llvm/test/Transforms/InstCombine/minmax-fold.ll
M llvm/test/Transforms/InstCombine/minmax-intrinsics.ll
M llvm/test/Transforms/InstCombine/sadd_sat.ll
M llvm/test/Transforms/InstCombine/select-min-max.ll
Log Message:
-----------
[InstCombine] Canonicalize `max(min(X, MinC), MaxC) -> min(max(X, MaxC), MinC)` (#136665)
Closes #121870.
https://alive2.llvm.org/ce/z/WjmAjz
https://alive2.llvm.org/ce/z/4KCjgL
Commit: 4a58071d87265dfccba72134b25cf4d1595d98c5
https://github.com/llvm/llvm-project/commit/4a58071d87265dfccba72134b25cf4d1595d98c5
Author: Diana Picus <Diana-Magda.Picus at amd.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineFrameInfo.h
M llvm/include/llvm/CodeGen/TargetFrameLowering.h
M llvm/lib/CodeGen/PrologEpilogInserter.cpp
M llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
A llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir
A llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll
A llvm/test/CodeGen/AMDGPU/vgpr-blocks-funcinfo.mir
M llvm/unittests/Target/AMDGPU/CMakeLists.txt
A llvm/unittests/Target/AMDGPU/LiveRegUnits.cpp
Log Message:
-----------
[AMDGPU] Support block load/store for CSR (#130013)
Add support for using the existing `SCRATCH_STORE_BLOCK` and
`SCRATCH_LOAD_BLOCK` instructions for saving and restoring callee-saved
VGPRs. This is controlled by a new subtarget feature, `block-vgpr-csr`.
It does not include WWM registers - those will be saved and restored
individually, just like before. This patch does not change the ABI.
Use of this feature may lead to slightly increased stack usage, because
the memory is not compacted if certain registers don't have to be
transferred (this will happen in practice for calling conventions where
the callee and caller saved registers are interleaved in groups of 8).
However, if the registers at the end of the block of 32 don't have to be
transferred, we don't need to use a whole 128-byte stack slot - we can
trim some space off the end of the range.
In order to implement this feature, we need to rely less on the
target-independent code in the PrologEpilogInserter, so we override
several new methods in `SIFrameLowering`. We also add new pseudos,
`SI_BLOCK_SPILL_V1024_SAVE/RESTORE`.
One peculiarity is that both the SI_BLOCK_V1024_RESTORE pseudo and the
SCRATCH_LOAD_BLOCK instructions will have all the registers that are not
transferred added as implicit uses. This is done in order to inform
LiveRegUnits that those registers are not available before the restore
(since we're not really restoring them - so we can't afford to scavenge
them). Unfortunately, this trick doesn't work with the save, so before
the save all the registers in the block will be unavailable (see the
unit test).
Commit: 48585caf727004678617dc34fa50383c3f4eb2de
https://github.com/llvm/llvm-project/commit/48585caf727004678617dc34fa50383c3f4eb2de
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/test/Transforms/InstCombine/icmp.ll
Log Message:
-----------
InstCombine: Avoid counting uses of constants (#136566)
Logically it does not matter; getFreelyInvertedImpl doesn't
depend on the value for the m_ImmConstant case.
This use count logic should probably sink into getFreelyInvertedImpl,
every use of this appears to just be a hasOneUse or hasNUse count,
so this could change to just be a use count threshold.
Commit: a1331704752c46cd4d954eb8682af230937fe5a6
https://github.com/llvm/llvm-project/commit/a1331704752c46cd4d954eb8682af230937fe5a6
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/Target/AMDGPU/BUILD.gn
Log Message:
-----------
[gn build] Port 4a58071d8726
Commit: 3cd6b86cc1e1fd1d8d62ca1bcb8498362a4f7b68
https://github.com/llvm/llvm-project/commit/3cd6b86cc1e1fd1d8d62ca1bcb8498362a4f7b68
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachinePipeliner.h
M llvm/lib/CodeGen/MachinePipeliner.cpp
A llvm/test/CodeGen/Hexagon/swp-alias-cross-iteration.mir
A llvm/test/CodeGen/Hexagon/swp-no-alias.mir
Log Message:
-----------
[MachinePipeliner] Use AliasAnalysis properly when analyzing loop-carried dependencies (#136691)
MachinePipeliner uses AliasAnalysis to collect loop-carried memory
dependencies. To analyze loop-carried dependencies, we need to
explicitly tell AliasAnalysis that the values may come from different
iterations. Before this patch, MachinePipeliner didn't do this, so some
loop-carried dependencies might be missed. For example, in the following
case, there is a loop-carried dependency from the load to the store, but
it wasn't considered.
```
def @f(ptr noalias %p0, ptr noalias %p1) {
entry:
br label %body
loop:
%idx0 = phi ptr [ %p0, %entry ], [ %p1, %body ]
%idx1 = phi ptr [ %p1, %entry ], [ %p0, %body ]
%v0 = load %idx0
...
store %v1, %idx1
...
}
```
Further, the handling of the underlying objects was not sound. If there
is no information about memory operands (i.e., `memoperands()` is
empty), it must be handled conservatively. However, Machinepipeliner
uses a dummy value (namely `UnknownValue`). It is distinguished from
other "known" objects, causing necessary dependencies to be missed.
(NOTE: in such cases, `buildSchedGraph` adds non-loop-carried
dependencies correctly, so perhaps a critical problem has not occurred.)
This patch fixes the above problems. This change has increased false
dependencies that didn't exist before. Therefore, this patch also
introduces additional alias checks with the underlying objects.
Split off from #135148
Commit: 0de2f64e652a1b8c1e051635c98fb2b69c6b2c62
https://github.com/llvm/llvm-project/commit/0de2f64e652a1b8c1e051635c98fb2b69c6b2c62
Author: Alex Rønne Petersen <alex at alexrp.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/test/Driver/Xclangas.s
Log Message:
-----------
[clang] XFAIL the `Xclangas.s` test on AIX. (#136744)
Clang on AIX does not use the integrated assembler.
https://github.com/llvm/llvm-project/pull/100714#issuecomment-2822056054
Commit: 11a3de7e98785b0df8f2010fb22c10c0590d2707
https://github.com/llvm/llvm-project/commit/11a3de7e98785b0df8f2010fb22c10c0590d2707
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/IR/RuntimeLibcalls.def
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/ARM/popcnt.ll
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
M llvm/test/CodeGen/RISCV/pr56457.ll
M llvm/test/CodeGen/RISCV/pr95271.ll
M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/RISCV/sextw-removal.ll
M llvm/test/CodeGen/Thumb2/mve-ctpop.ll
Log Message:
-----------
[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall (#101786)
This is a reland of #99752 with the bug fixed (see test diff in the
third commit in this PR).
All `popcount` libcalls return `int`, but `ISD::CTPOP` returns the type
of the argument, which can be wider than `int`. The fix is to make DAG
legalizer pass the correct return type to `makeLibCall` and sign-extend
the result afterwards.
Original commit message:
The main change is adding CTPOP to `RuntimeLibcalls.def` to allow
targets to use LibCall action for CTPOP. DAG legalizers are changed
accordingly.
Pull Request: https://github.com/llvm/llvm-project/pull/101786
Commit: 8e9ff8ea51b5a734df1314bd87ddb8dab31c2fbd
https://github.com/llvm/llvm-project/commit/8e9ff8ea51b5a734df1314bd87ddb8dab31c2fbd
Author: Jerry-Ge <jerry.ge at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaUtilOps.td
M mlir/lib/Conversion/TosaToMLProgram/TosaToMLProgram.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-pipeline.mlir
M mlir/test/Conversion/TosaToMLProgram/tosa-to-mlprogram.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/level_check.mlir
M mlir/test/Dialect/Tosa/variables.mlir
Log Message:
-----------
[mlir][tosa] Align Variable ops to match with TOSA v1.0 spec (#130680)
- updated AnyType:$value to Tosa_Tensor:$input1 and Tosa_Tensor:$output1
for VariableWrite and VriableRead Operators
- updated description discrepancies
- note: in the TOSA spec, we had var_shape attr, but it's already
included
in the TypeAttr:$type in MLIR
Signed-off-by: Jerry Ge <jerry.ge at arm.com>
Commit: a7999f3fba49b7b5da08afb070841f792ea1c796
https://github.com/llvm/llvm-project/commit/a7999f3fba49b7b5da08afb070841f792ea1c796
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
Log Message:
-----------
[NFC][AArch64TTI] Refactor instCombineSVEVectorMul into simplifySVEIntrinsicBinOp.
Commit: 3c3fb357a0ed4dbf640bdb6c61db2a430f7eb298
https://github.com/llvm/llvm-project/commit/3c3fb357a0ed4dbf640bdb6c61db2a430f7eb298
Author: TatWai Chong <tatwai.chong at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
M mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/level_check.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/profile_pro_fp_unsupported.mlir
M mlir/test/Dialect/Tosa/profile_pro_int_unsupported.mlir
M mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
M mlir/test/Dialect/Tosa/verifier.mlir
Log Message:
-----------
[mlir][tosa] Enhance CONV3D & DEPTHWISE_CONV2D verifier (#135738)
Verify the correctness of pad, stride, dilation, and dimension of
input/weight/bias/output.
Adapt and extend the existing conv2d error_if function to support
additional convolution variants.
Commit: 8c47f23232fc8b547f643d379175f322d01e4cbd
https://github.com/llvm/llvm-project/commit/8c47f23232fc8b547f643d379175f322d01e4cbd
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/docs/SPIRVUsage.rst
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroup_matrix_multiply_accumulate/subgroup_matrix_multiply_accumulate_generic.ll
Log Message:
-----------
[SPIRV] Support for the SPV_INTEL_subgroup_matrix_multiply_accumulate SPIR-V extension (#135225)
Adds support for the SPV_INTEL_subgroup_matrix_multiply_accumulate
SPIR-V extension according to
https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_subgroup_matrix_multiply_accumulate.asciidoc
Commit: 15d8b3cae9debc2bd7d27ca92ff599ba9fb30da5
https://github.com/llvm/llvm-project/commit/15d8b3cae9debc2bd7d27ca92ff599ba9fb30da5
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrGISel.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/lower-neon-vector-fcmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vector-fcmp.mir
M llvm/test/CodeGen/AArch64/arm64-zip.ll
M llvm/test/CodeGen/AArch64/select_cc.ll
Log Message:
-----------
[LLVM][ISel][AArch64 Remove AArch64ISD::FCM##z nodes. (#135817)
We can easily select compare-to-zero instructions without dedicated
nodes. The test changes show opportunities that were previous missed
because of the redundant complexity.
Commit: 37e8c6c6ee7c809e45d0e5b61c601a0bb91ca1c4
https://github.com/llvm/llvm-project/commit/37e8c6c6ee7c809e45d0e5b61c601a0bb91ca1c4
Author: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M bolt/lib/Core/MCPlusBuilder.cpp
M bolt/unittests/Core/MCPlusBuilder.cpp
Log Message:
-----------
[BOLT] Do not return Def-ed registers from MCPlusBuilder::getUsedRegs (#129890)
Update the implementation of `MCPlusBuilder::getUsedRegs` to match its
description in the header file, add unit tests.
Commit: c93af22d124ed70742fb692886ff26d8786f8c2d
https://github.com/llvm/llvm-project/commit/c93af22d124ed70742fb692886ff26d8786f8c2d
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineConstantPoolLoads - remove duplicate SDLoc. NFC.
Commit: 720a91183b16f94876adaa831d0a49a04d31420a
https://github.com/llvm/llvm-project/commit/720a91183b16f94876adaa831d0a49a04d31420a
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/preserve-inbounds.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep.ll
Log Message:
-----------
[SeparateConstOffsetFromGEP] Preserve inbounds flag based on ValueTracking and NUW (#130617)
If we know that the initial GEP was inbounds, and we change it to a
sequence of GEPs from the same base pointer where every offset is
non-negative, then the new GEPs are inbounds.
We can also preserve inbounds if the inbounds GEP and the involved additions are NUW.
For SWDEV-516125.
Commit: b0524f332958b6e593868533127fd0651bdcf553
https://github.com/llvm/llvm-project/commit/b0524f332958b6e593868533127fd0651bdcf553
Author: Ben Shi <2283975856 at qq.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/Basic/Targets/AVR.h
M clang/test/CodeGen/avr/avr-inline-asm-constraints.c
M clang/test/CodeGen/avr/avr-unsupported-inline-asm-constraints.c
M llvm/test/CodeGen/AVR/inline-asm/inline-asm-invalid.ll
Log Message:
-----------
[clang][AVR] Improve compatibility of inline assembly with avr-gcc (#136534)
Allow the value 64 to be round up to 0 for constraint 'I'.
Commit: 717efc0a994dfc5b2ed65ddb13b47fb917c9a467
https://github.com/llvm/llvm-project/commit/717efc0a994dfc5b2ed65ddb13b47fb917c9a467
Author: Luke Lau <luke at igalia.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
Log Message:
-----------
[RISCV] Support disjoint RISCVISD::OR_VL in combineOp_VLToVWOp_VL (#136820)
This handles combining fixed-length disjoint ors to vwadd[u].wv, as was
done for scalable vectors in #86929.
vwadd[u].vv patterns need to be handled separately with a pattern in a
separate patch due to the extends being sunk, see #136716.
Commit: 2a9f77f6bd48d757b2d45aadcb6cf76ef4b4ef32
https://github.com/llvm/llvm-project/commit/2a9f77f6bd48d757b2d45aadcb6cf76ef4b4ef32
Author: Björn Pettersson <bjorn.a.pettersson at ericsson.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/Reassociate.cpp
A llvm/test/Transforms/Reassociate/canonicalize-made-change.ll
Log Message:
-----------
[Reassociate] Invalidate analysis passes after canonicalizeOperands (#136835)
When ranking operands for an expression tree the reassociate pass also
perform canonicalization, putting constants on the right hand side. Such
transforms was however not registered as modifying the IR. So at the end
of the pass, if not having made any other changes, the pass returned
that all analyses should be kept.
With this patch we make sure to set MadeChange to true when modifying
the IR via canonicalizeOperands. This is to make sure analyses such as
DemandedBits are properly invalidated when instructions are modified.
Commit: 71ce9e26aec00e4af27a69ccfab8ca1773ed7018
https://github.com/llvm/llvm-project/commit/71ce9e26aec00e4af27a69ccfab8ca1773ed7018
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Sema/AnalysisBasedWarnings.h
M clang/lib/Sema/AnalysisBasedWarnings.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaExpr.cpp
A clang/test/Analysis/pragma-diag-control.cpp
Log Message:
-----------
Control analysis-based diagnostics with #pragma (#136323)
Previously, analysis-based diagnostics (like -Wconsumed) had to be
enabled at file scope in order to be run at the end of each function
body. This meant that they did not respect #pragma clang diagnostic
enabling or disabling the diagnostic.
Now, these pragmas can control the diagnostic emission.
Fixes #42199
Commit: 05b7e97c78ba375cc146c67a4539446f8bcb880c
https://github.com/llvm/llvm-project/commit/05b7e97c78ba375cc146c67a4539446f8bcb880c
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M flang/examples/FeatureList/FeatureList.cpp
M flang/include/flang/Lower/DirectivesCommon.h
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Semantics/symbol.h
M flang/include/flang/Support/Fortran.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/rewrite-directives.cpp
Log Message:
-----------
[flang][OpenMP] Extend common::AtomicDefaultMemOrderType enumeration (#136312)
Add "Acquire" and "Release", and rename it to OmpMemoryOrderType, since
memory order type is a concept extending beyond the
ATOMIC_DEFAULT_MEM_ORDER clause.
When processing a REQUIRES directive (in rewrite-directives.cpp), do not
add Acquire or Release to ATOMIC constructs, because handling of those
types depends on the OpenMP version, which is not available in that
file. This issue will be addressed later.
Commit: 013aab40511bf56a856643105e42c4204fe58f45
https://github.com/llvm/llvm-project/commit/013aab40511bf56a856643105e42c4204fe58f45
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-binop.ll
A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-shift.ll
Log Message:
-----------
[NFC][LLVM] Add test coverage for all binops to sve-intrinsic-simplify-binop.ll.
Also adds sve-intrinsic-simplify-shift.ll to test asr, shl and shr.
Commit: 0f32809139bd104adb2c1de4fa1044da78a7e5af
https://github.com/llvm/llvm-project/commit/0f32809139bd104adb2c1de4fa1044da78a7e5af
Author: arun-thmn <arun.thangamani at intel.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/X86Vector/X86Vector.td
M mlir/include/mlir/Dialect/X86Vector/X86VectorDialect.h
M mlir/include/mlir/Dialect/X86Vector/X86VectorInterfaces.td
M mlir/lib/Dialect/X86Vector/IR/CMakeLists.txt
M mlir/lib/Dialect/X86Vector/IR/X86VectorDialect.cpp
M mlir/lib/Dialect/X86Vector/Transforms/LegalizeForLLVMExport.cpp
M mlir/test/Dialect/X86Vector/legalize-for-llvm.mlir
M mlir/test/Dialect/X86Vector/roundtrip.mlir
M mlir/test/Target/LLVMIR/x86vector.mlir
Log Message:
-----------
Reland [mlir][x86vector] AVX Convert/Broadcast BF16 to F32 instructions (#136830)
Quick fix for the PR: https://github.com/llvm/llvm-project/pull/135143
which failed building on `amd` and `arm` bots build. See the logs in the
above PR for the errors.
Commit: 500cccca0cbcbb547e2a54b25162f20808b45af0
https://github.com/llvm/llvm-project/commit/500cccca0cbcbb547e2a54b25162f20808b45af0
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/Sema/AnalysisBasedWarnings.cpp
Log Message:
-----------
Remove spurious semicolon; NFC
Commit: a99e055030f0da61651e808cbb208bb39594cdc0
https://github.com/llvm/llvm-project/commit/a99e055030f0da61651e808cbb208bb39594cdc0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/BPF/BPFISelLowering.h
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.h
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
Log Message:
-----------
[DAG] shouldReduceLoadWidth - add optional<unsigned> byte offset argument (#136723)
Based off feedback for #129695 - we need to be able to determine the
load offset of smaller loads when trying to determine whether a multiple
use load should be split (in particular for AVX subvector extractions).
This patch adds a std::optional<unsigned> ByteOffset argument to
shouldReduceLoadWidth calls for where we know the constant offset to
allow targets to make use of it in future patches.
Commit: 1fd0b41b44603c190f507f222c16d9f98470f89d
https://github.com/llvm/llvm-project/commit/1fd0b41b44603c190f507f222c16d9f98470f89d
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
R lldb/test/Shell/SymbolFile/DWARF/range-lower-then-low-pc.s
M lldb/test/Shell/SymbolFile/DWARF/x86/discontinuous-inline-function.s
Log Message:
-----------
[lldb/DWARF] Remove "range lower than function low_pc" check (#132395)
The check is not correct for discontinuous functions, as one of the
blocks could very well begin before the function entry point. To catch
dead-stripped ranges, I check whether the functions is after the first
known code address. I don't print any error in this case as that is a
common/expected situation.
This avoids many errors like:
```
error: ld-linux-x86-64.so.2 0x00085f3b: adding range [0x0000000000001ae8-0x0000000000001b07) which has a
base that is less than the function's low PC 0x000000000001cfb0. Please file a bug and attach the file at
the start of this error message
```
when debugging binaries on debian trixie because the dynamic linker
(ld-linux) contains discontinuous functions.
If the block ranges is not a subrange of the enclosing block then this
will range will currently be added to the outer block as well (i.e., we
get the same behavior that's currently possible for non-subrange blocks
larger than function_low_pc). However, this code path is buggy and I'd
like to change that (#117725).
Commit: 94206c9700d52e1a9e42da10e32f0368f9503b44
https://github.com/llvm/llvm-project/commit/94206c9700d52e1a9e42da10e32f0368f9503b44
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/CMakeLists.txt
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.h
A lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndexSet.cpp
A lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndexSet.h
M lldb/unittests/SymbolFile/DWARF/DWARFIndexCachingTest.cpp
Log Message:
-----------
[lldb] Preparation for DWARF indexing speedup (#123732)
This is part of the work proposed in
<https://discourse.llvm.org/t/rfc-speeding-up-dwarf-indexing-again/83979>.
One of the change is that the there will be a different structure for
holding the partial indexes and the final (consolidated) index. To
prepare for this, I'm making the IndexSet structure a template. The
index cache encoding/decoding methods are changed into free functions,
as they only need to know how to work with the final index.
I've moved this functionality to a separate file as all this doesn't
really depend on the rest of the ManualDWARFIndex and it needs to be
public due to its use in the unit test (both of which indicate that it
could be a component of its own).
Commit: 4e073a11c24cc0abfe5a8eabd99f1e4762c89e2b
https://github.com/llvm/llvm-project/commit/4e073a11c24cc0abfe5a8eabd99f1e4762c89e2b
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/Plugins/SymbolFile/DWARF/BUILD.gn
Log Message:
-----------
[gn build] Port 94206c9700d5
Commit: 6bb2f90557fb2b4b216299cc2beb4afb641476aa
https://github.com/llvm/llvm-project/commit/6bb2f90557fb2b4b216299cc2beb4afb641476aa
Author: Diana Picus <Diana-Magda.Picus at amd.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineFrameInfo.h
M llvm/include/llvm/CodeGen/TargetFrameLowering.h
M llvm/lib/CodeGen/PrologEpilogInserter.cpp
M llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
R llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir
R llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll
R llvm/test/CodeGen/AMDGPU/vgpr-blocks-funcinfo.mir
M llvm/unittests/Target/AMDGPU/CMakeLists.txt
R llvm/unittests/Target/AMDGPU/LiveRegUnits.cpp
Log Message:
-----------
Revert "[AMDGPU] Support block load/store for CSR" (#136846)
Reverts llvm/llvm-project#130013 due to failures with expensive checks
on.
Commit: 673882cfbc5cf8425444811f92080bdd0b7cbb78
https://github.com/llvm/llvm-project/commit/673882cfbc5cf8425444811f92080bdd0b7cbb78
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/Target/AMDGPU/BUILD.gn
Log Message:
-----------
[gn build] Port 6bb2f90557fb
Commit: 14b38cf946c5b10039865f1aaedac8ea1ca06abb
https://github.com/llvm/llvm-project/commit/14b38cf946c5b10039865f1aaedac8ea1ca06abb
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/matmul.mlir
Log Message:
-----------
[mlir][vector] Update test post 136699 (nfc) (#136841)
Updates a test that I forgot to update in #136699. Failing bot:
* https://lab.llvm.org/buildbot/#/builders/143/builds/7166
Commit: 8292e050e62f69ae9aea68fafd011152eede7e4d
https://github.com/llvm/llvm-project/commit/8292e050e62f69ae9aea68fafd011152eede7e4d
Author: Wenju He <wenju.he at intel.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M libclc/CMakeLists.txt
Log Message:
-----------
[libclc] Build for OpenCL 3.0 (#135733)
This PR is modified cherry-pick of
https://github.com/intel/llvm/commit/cba338e5fb1c
This PR sets OpenCL language version to be the same, which is 3.0,
for every target and device, in order to unify the build process.
Target should define supported extensions and features via
setSupportedOpenCLOpts API.
llvm-diff shows one change to amdgcn--amdhsa.bc:
* ctz symbols are added since they are now enabled for amdgcn.
Commit: 1ce709cb845b8b0bc4625198afa7a26c0a198fe4
https://github.com/llvm/llvm-project/commit/1ce709cb845b8b0bc4625198afa7a26c0a198fe4
Author: Nicholas Guy <nicholas.guy at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-no-dotprod.ll
Log Message:
-----------
[LV] Fix crash when building partial reductions using types that aren't known scale factors (#136680)
Commit: a1f369e6309c8c6adaae886afc55817b97953641
https://github.com/llvm/llvm-project/commit/a1f369e6309c8c6adaae886afc55817b97953641
Author: Nicholas Guy <nicholas.guy at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
Log Message:
-----------
[AArch64][SVE] Add dot product lowering for PARTIAL_REDUCE_MLA node (#130933)
Add lowering in tablegen for PARTIAL_REDUCE_U/SMLA ISD nodes. Only
happens when the combine has been performed on the ISD node. Also adds
in check to only do the DAG combine when the node can then eventually be
lowered, so changes neon tests too.
---------
Co-authored-by: James Chesterman <james.chesterman at arm.com>
Commit: 386ff113f974967dee9d3fd654c2259a94c59b2e
https://github.com/llvm/llvm-project/commit/386ff113f974967dee9d3fd654c2259a94c59b2e
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
Log Message:
-----------
[flang][OpenMP] Use OmpMemoryOrderType enumeration in FAIL clause (#136313)
Make the FAIL clause contain OmpMemoryOrderType enumeration instead of
OmpClause. This simplifies the semantic checks of the FAIL clause.
Commit: 5b0cd17c386ecd126c7f0ab514413bab8222b421
https://github.com/llvm/llvm-project/commit/5b0cd17c386ecd126c7f0ab514413bab8222b421
Author: Virginia Cangelosi <virginia.cangelosi at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/include/clang/Basic/arm_sme.td
A clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
A clang/test/Sema/aarch64-sme2p2-instrinsics/acle_sme2p2_fp8_imm.cpp
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/SMEInstrFormats.td
A llvm/test/CodeGen/AArch64/sme2-intrinsics-mop4-fp8.ll
Log Message:
-----------
[Clang][llvm] Implement fp8 FMOP4A intrinsics (#130127)
Implement all mf8 FMOP4A instructions in clang and llvm following the
acle in https://github.com/ARM-software/acle/pull/381/files.
It also updates previous mop4 instructions from IntrNoMem to
IntrInaccessibleMemOnly
Commit: 92bba68634ec48c738d45bc86b05b1390aa82f4b
https://github.com/llvm/llvm-project/commit/92bba68634ec48c738d45bc86b05b1390aa82f4b
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/Frontend/OpenMP/OMPDeviceConstants.h
M offload/DeviceRTL/src/Kernel.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/test/offloading/ompx_bare.c
M offload/test/offloading/ompx_bare_multi_dim.cpp
Log Message:
-----------
[Offload] Fix handling of 'bare' mode when environment missing (#136794)
Summary:
We treated the missing kernel environment as a unique mode, but it was
kind of this random bool that was doing the same thing and it explicitly
expects the kernel environment to be zero. It broke after the previous
change since it used to default to SPMD and didn't handle zero in any of
the other cases despite being used. This fixes that and queries for it
without needing to consume an error.
Commit: 6d0d50f0ac0cb108a06558cb178a68fb78cfa06f
https://github.com/llvm/llvm-project/commit/6d0d50f0ac0cb108a06558cb178a68fb78cfa06f
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M offload/DeviceRTL/CMakeLists.txt
Log Message:
-----------
[OpenMP] Update the bitcode library install and search path (#136754)
Summary:
This was accidentally kept in the old location when we moved to the
new `lib/<triple>/` location for the DeviceRTL. Move this to reduce the
delta with https://github.com/llvm/llvm-project/pull/136729.
Commit: 91e1922d45bdefd444a2ba0484fd858e2ad80254
https://github.com/llvm/llvm-project/commit/91e1922d45bdefd444a2ba0484fd858e2ad80254
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
Log Message:
-----------
[DSE] Skip non-pointer args in initializes handling (NFCI)
Avoid performing AA queries on non-pointers.
Commit: 14dee0aeaaef2ebd5c3295edca4c5d3762464934
https://github.com/llvm/llvm-project/commit/14dee0aeaaef2ebd5c3295edca4c5d3762464934
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/NewGVN.cpp
Log Message:
-----------
[NewGVN] Avoid AA query on non-pointers (NFCI)
In order for the instruction result to alias with the pointer it
needs to be a pointer.
Commit: 01ee03c262519597307301715dc4d41e6d62b774
https://github.com/llvm/llvm-project/commit/01ee03c262519597307301715dc4d41e6d62b774
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Coroutines/CoroElide.cpp
Log Message:
-----------
[CoroElide] Avoid AA query on non-pointers (NFCI)
Commit: 208257f7e0f1e7bbf878753bb8a7554891b84380
https://github.com/llvm/llvm-project/commit/208257f7e0f1e7bbf878753bb8a7554891b84380
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Coroutines/CoroElide.cpp
Log Message:
-----------
[CoroElide] Remove unnecessary bitcast (NFCI)
No longer needed with opaque pointers.
Commit: eea1efed305fbeba5dc2b5e856d934ba8e57965c
https://github.com/llvm/llvm-project/commit/eea1efed305fbeba5dc2b5e856d934ba8e57965c
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
Log Message:
-----------
[InstrProfiling] Avoid unnecessary bitcast (NFC)
Not needed with opaque pointers.
Commit: 00934beb8e6b9a5fe04ff7805249706d0edc3c5b
https://github.com/llvm/llvm-project/commit/00934beb8e6b9a5fe04ff7805249706d0edc3c5b
Author: jyli0116 <jyli0116 at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/test/CodeGen/AArch64/fsh.ll
Log Message:
-----------
[AArch64] Funnel Shift now uses rev32/rev64 instructions (#136707)
Fixes #130469
Now uses REV32/REV64 instructions to complete operation.
New Output:
```
G1:
rev64 v0.4s, v0.4s
ret
G2:
rev32 v0.8h, v0.8h
ret
G3:
rev16 v0.16b, v0.16b
ret
G4:
rev32 v0.4h, v0.4h
ret
G5:
rev16 v0.8b, v0.8b
ret
```
Old Output:
```
G1:
shl v1.2d, v0.2d, #32
usra v1.2d, v0.2d, #32
mov v0.16b, v1.16b
ret
G2:
shl v1.4s, v0.4s, #16
usra v1.4s, v0.4s, #16
mov v0.16b, v1.16b
ret
G3:
rev16 v0.16b, v0.16b
ret
G4:
shl v1.2s, v0.2s, #16
usra v1.2s, v0.2s, #16
fmov d0, d1
ret
G5:
rev16 v0.8b, v0.8b
ret
```
Commit: 52cb1c93acdad4fa2aa0ce17691d7205cc9645f9
https://github.com/llvm/llvm-project/commit/52cb1c93acdad4fa2aa0ce17691d7205cc9645f9
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
Log Message:
-----------
[AArch64Arm64ECCallLowering] Remove unnecessary bitcasts (NFCI)
These are all pointer bitcasts, which are no longer necessary
with opaque pointers.
Commit: a2c1ff10eb930dd56be306dc0818d6ff31fff546
https://github.com/llvm/llvm-project/commit/a2c1ff10eb930dd56be306dc0818d6ff31fff546
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
Log Message:
-----------
[mlir][acc] Use consistent name for device_num operand (#136745)
`acc.set`, `acc.init`, and `acc.shutdown` take a `device_num` operand.
However, this was named inconsistently. Give it the same consistent name
for all aforementioned operations.
---------
Co-authored-by: erichkeane <ekeane at nvidia.com>
Commit: 4cc806f9f5b76b3ca42de29fb6a3affe9774d7f8
https://github.com/llvm/llvm-project/commit/4cc806f9f5b76b3ca42de29fb6a3affe9774d7f8
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
Log Message:
-----------
[AArch64Arm64ECCallLowering] Drop unnecessary pointer type members (NFC)
With opaque pointers, these are all the same type. Consolidate to
just PtrTy.
Commit: 5afe85982a6e911326c5df141c718b239edea9c8
https://github.com/llvm/llvm-project/commit/5afe85982a6e911326c5df141c718b239edea9c8
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
Log Message:
-----------
[OMPIRBuilder] Remove unnecessary pointer bitcasts (NFCI)
Not needed with opaque pointers.
Commit: 237ed0cffcd721f0ae48420f17db2e2da97fb625
https://github.com/llvm/llvm-project/commit/237ed0cffcd721f0ae48420f17db2e2da97fb625
Author: Christian Sigg <csigg at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] Port 0f32809139bd104adb2c1de4fa1044da78a7e5af.
Commit: e58d227b09d533e2df644f827cedff8e206e0bfc
https://github.com/llvm/llvm-project/commit/e58d227b09d533e2df644f827cedff8e206e0bfc
Author: Tobias Stadler <mail at stadler-tobias.de>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
A llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector.mir
Log Message:
-----------
[NFC][AArch64][GlobalISel] Add test coverage for vector load/store legalization (#134904)
Precommit tests for vector load/store legalization changes. This exposes
a miscompile in LegalizerHelper::reduceLoadStoreWidth for non-byte-sized
vector elements, which will be fixed in a follow-up patch.
The other tests are potential miscompilations due to unclear semantics
of vector load/stores, which will be addressed in a follow-up
discussion.
Commit: 46f18b7c6febe75b2cc0095f2227d935c14f70f2
https://github.com/llvm/llvm-project/commit/46f18b7c6febe75b2cc0095f2227d935c14f70f2
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M libcxxabi/test/test_demangle.pass.cpp
Log Message:
-----------
[ItaniumDemangle][test] Add test-cases for ref-qualified member pointer parameters
I noticed that there are test-cases that are commented out. But the
manglings for them seem to be impossible to generate from valid C++. I
added two test-cases generated from following C++ program:
```
struct X {
int func() const && { return 5; }
const int &&func2() { return 5; }
const int &&func3(const int &x) volatile { return 5; }
};
void f(int (X::*)() const &&, int const && (X::*)(),
int const && (X::*)(const int &) volatile) {}
int main() {
f(&X::func, &X::func2, &X::func3);
return 0;
}
```
Commit: 8158d43da33b33d260f2c43eb3f448f42b839b21
https://github.com/llvm/llvm-project/commit/8158d43da33b33d260f2c43eb3f448f42b839b21
Author: Dmitriy Smirnov <dmitriy.smirnov at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
Log Message:
-----------
[TOSA] Rescale output_zp fix (#136116)
Patch corrects output_zp in case of usigned output
Commit: 8502ba1eb40acdb0eda1039807afc34db0c7084a
https://github.com/llvm/llvm-project/commit/8502ba1eb40acdb0eda1039807afc34db0c7084a
Author: lorenzo chelini <l.chelini at icloud.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/MemRef/Transforms/Passes.h
M mlir/include/mlir/Dialect/MemRef/Transforms/Passes.td
M mlir/lib/Dialect/Bufferization/Pipelines/BufferizationPipelines.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandRealloc.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
M mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/NormalizeMemRefs.cpp
M mlir/lib/Dialect/MemRef/Transforms/ResolveShapedTypeResultDims.cpp
M mlir/test/python/pass_manager.py
Log Message:
-----------
[MLIR][NFC] Retire let constructor for MemRef (#134788)
let constructor is legacy (do not use in tree!) since the tableGen
backend emits most of the glue logic to build a pass.
Note: The following constructor has been retired:
```cpp
std::unique_ptr<Pass> createExpandReallocPass(bool emitDeallocs = true);
```
To update your codebase, replace it with the new options-based API:
```cpp
memref::ExpandReallocPassOptions expandAllocPassOptions{
/*emitDeallocs=*/false};
pm.addPass(memref::createExpandReallocPass(expandAllocPassOptions));
```
Commit: 806d59eecd16dc35473638fd73ea0be8e59c6275
https://github.com/llvm/llvm-project/commit/806d59eecd16dc35473638fd73ea0be8e59c6275
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M libclc/generic/include/clc/image/image.h
Log Message:
-----------
[libclc] Fix unguarded use of image types (#136871)
Commit 8292e05 which switched the OpenCL C version to 3.0 exposed this
issue, which wasn't caught in pre-commit CI.
Commit: 6c561604336497cbeebc90f9066a9f474458a38d
https://github.com/llvm/llvm-project/commit/6c561604336497cbeebc90f9066a9f474458a38d
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M libclc/CMakeLists.txt
Log Message:
-----------
[libclc] Re-enable compiler warning (#136872)
libclc is now clean of code that triggers the
bitwise-conditional-parentheses warning, so we can finally remove the
workaround.
Commit: f11b3decdd603655d886061c0b2e26b64a6563d2
https://github.com/llvm/llvm-project/commit/f11b3decdd603655d886061c0b2e26b64a6563d2
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M flang/lib/Optimizer/CodeGen/TargetRewrite.cpp
M flang/test/Fir/CUDA/cuda-target-rewrite.mlir
Log Message:
-----------
[flang][cuda] Carry over the CUDA attribute in target rewrite (#136811)
Commit: 96519028d514853d429c2d09482ba0bd9a899c57
https://github.com/llvm/llvm-project/commit/96519028d514853d429c2d09482ba0bd9a899c57
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/source/Plugins/Language/CPlusPlus/LibCxxInitializerList.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxSpan.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxVariant.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxVector.cpp
Log Message:
-----------
[lldb][DataFormatters] Make data-formatters log to the DataFormatters channel
Currently the data-formatters log to either DataFormatters or Types. The
former is probably more sensible, so log there consistently from all
formatters.
Commit: cc6def4b7521676fd339936d027e48928e0ba398
https://github.com/llvm/llvm-project/commit/cc6def4b7521676fd339936d027e48928e0ba398
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M libc/src/stdio/printf_core/core_structs.h
Log Message:
-----------
[libc] Special case PPC double double for print (#136614)
Summary:
We use the storage class for `long double` in the printing
implementations. We don't fully support the PPC double double type,
which that maps to, but we can stub out just the support needed for the
print interface to works. This required using the internal interface for
storage type, but it should be good enough.
Fixes: https://github.com/llvm/llvm-project/issues/136596
Commit: ecb0daa72c442caeb4e295e1076d54c5e18101b2
https://github.com/llvm/llvm-project/commit/ecb0daa72c442caeb4e295e1076d54c5e18101b2
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/utils/TableGen/DecoderEmitter.cpp
Log Message:
-----------
[NFC][LLVM][TableGen] Eliminate inheritance from std::vector (#136573)
Commit: 79151244d6a501c027add60734ddfe4c609e75bb
https://github.com/llvm/llvm-project/commit/79151244d6a501c027add60734ddfe4c609e75bb
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Log Message:
-----------
[DAG] narrowExtractedVectorLoad - reuse existing SDLoc. NFC (#136870)
Commit: 2e389cb9aae0e9734fc8e16f6ebc6edb392d79a9
https://github.com/llvm/llvm-project/commit/2e389cb9aae0e9734fc8e16f6ebc6edb392d79a9
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M flang/test/Semantics/OpenACC/acc-data.f90
M llvm/include/llvm/Frontend/OpenACC/ACC.td
Log Message:
-----------
[Flang][OpenACC] Make async clause on data consistent with elsewhere (#136866)
in #136610 we agreed that all async clauses on compute constructs should
act as 'only 1 per device-type-group'. On `data`, it has the same
specification language, and the same real requirements, so it seems
sensible to make it work the same way.
Commit: 8abc917fe04140b6c6088a67e0398f637efde808
https://github.com/llvm/llvm-project/commit/8abc917fe04140b6c6088a67e0398f637efde808
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/test/Transforms/InstCombine/and-fcmp.ll
Log Message:
-----------
[InstCombine] Do not fold logical is_finite test (#136851)
This patch disables the fold for logical is_finite test (i.e., `and
(fcmp ord x, 0), (fcmp u* x, inf) -> fcmp o* x, inf`).
It is still possible to allow this fold for several logical cases (e.g.,
`stripSignOnlyFPOps(RHS0)` does not strip any operations). Since this
patch has no real-world impact, I decided to disable this fold for all
logical cases.
Alive2: https://alive2.llvm.org/ce/z/aH4LC7
Closes https://github.com/llvm/llvm-project/issues/136650.
Commit: 24c860547e8e595f8bf8d87b52544e2aff243f2e
https://github.com/llvm/llvm-project/commit/24c860547e8e595f8bf8d87b52544e2aff243f2e
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
Log Message:
-----------
AMDGPU/MC: Fix emitting absolute expressions (#136789)
When absolute MCExprs appear in normal instruction operands, we have to
emit them like a normal inline constant or literal. More generally, an
MCExpr that happens to have an absolute evaluation should be treated
exactly like an immediate operand here.
No test; I found this downstream, and I don't think it can be triggered
upstream yet.
Fixes: 16238669 ("[AMDGPU][MC] Support UC_VERSION_* constants. (#95618)")
Commit: 2f0cd0c68ef027f87f34f04141c083212fda2806
https://github.com/llvm/llvm-project/commit/2f0cd0c68ef027f87f34f04141c083212fda2806
Author: Mingming Liu <mingmingl at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/lib/ProfileData/InstrProf.cpp
M llvm/lib/ProfileData/InstrProfWriter.cpp
Log Message:
-----------
[NFCI] Move ProfOStream from InstrProfWriter.cpp to InstrProf.h/cpp (#136791)
ProfOStream is a wrapper class for output stream, and used by
InstrProfWriter.cpp to serialize various profiles, like PGO profiles and
MemProf.
This change proposes to move it into InstrProf.h/cpp. After this is in,
InstrProfWriter can dispatch serialization of various formats into
methods like `obj->serialize()`, and the serialization code could be
move out of InstrProfWriter.cpp into individual classes (each in a
smaller cpp file). One example is that we can gradually move
writeMemprof [1] into llvm/*/ProfileData/MemProf.h/cpp, where a couple
of classes already have `serialize/deserialize` methods.
[1]
https://github.com/llvm/llvm-project/blob/85b35a90770b6053f91d79ca685cdfa4bf6499a4/llvm/lib/ProfileData/InstrProfWriter.cpp#L774-L791
Commit: 1da856a685cf427ab1f5b810125c41e7859ed362
https://github.com/llvm/llvm-project/commit/1da856a685cf427ab1f5b810125c41e7859ed362
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndexSet.h
Log Message:
-----------
[lldb] Fix typo in ManualDWARFIndexSet.h
operator== wasn't used in production code, but the bad definition made
the tests vacuosly pass.
Commit: a83b4a2dc9706d9e898f3462b5c2ff5ed05589d2
https://github.com/llvm/llvm-project/commit/a83b4a2dc9706d9e898f3462b5c2ff5ed05589d2
Author: Justin Bogner <mail at justinbogner.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/Analysis/DXILResource.h
M llvm/lib/Target/DirectX/CMakeLists.txt
A llvm/lib/Target/DirectX/DXILForwardHandleAccesses.cpp
A llvm/lib/Target/DirectX/DXILForwardHandleAccesses.h
M llvm/lib/Target/DirectX/DirectX.h
M llvm/lib/Target/DirectX/DirectXPassRegistry.def
M llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/alloca.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/ambiguous.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/buffer-O0.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/cbuffer-access.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/undominated.ll
M llvm/test/CodeGen/DirectX/llc-pipeline.ll
Log Message:
-----------
[DirectX] Implement the ForwardHandleAccesses pass (#135378)
This pass attempts to forward resource handle creation to accesses of
the handle global. This avoids dependence on optimizations like CSE and
GlobalOpt for correctness of DXIL.
Fixes #134574.
Commit: ea5449ddd5d03da034eccb80e5ba1e44ee02e243
https://github.com/llvm/llvm-project/commit/ea5449ddd5d03da034eccb80e5ba1e44ee02e243
Author: erichkeane <ekeane at nvidia.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M clang/test/CIR/CodeGenOpenACC/data.c
M clang/test/SemaOpenACC/data-construct-async-clause.c
Log Message:
-----------
[OpenACC][CIR] Implement 'async'/'if' lowering for 'data' construct
These two are trivial, and work the same as the compute construct
versions of these, so this adds tests to do so, and adds them to the
implementation.
Commit: d7215c0ee2e4bca1ce87b956335ef6a2cddaf16f
https://github.com/llvm/llvm-project/commit/d7215c0ee2e4bca1ce87b956335ef6a2cddaf16f
Author: Jannick Kremer <jannick.kremer at mailbox.org>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/tools/libclang/CIndex.cpp
M clang/unittests/libclang/LibclangTest.cpp
Log Message:
-----------
[libclang/C++] Fix clang_File_isEqual for in-memory files (#135773)
Add tests for `clang_File_isEqual` (on-disk and in-memory)
Commit: 83c309b90550aa768ff9aa11b70898ee2c56b71e
https://github.com/llvm/llvm-project/commit/83c309b90550aa768ff9aa11b70898ee2c56b71e
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/include/clang/Sema/ScopeInfo.h
M clang/include/clang/Sema/SemaCUDA.h
M clang/lib/Sema/SemaCUDA.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaOverload.cpp
A clang/test/CodeGenCUDA/lambda-constexpr-capture.cu
Log Message:
-----------
[CUDA][HIP] capture possible ODR-used var (#136645)
In a lambda function, a call of a function may
resolve to host and device functions with different
signatures. Especially, a constexpr local variable may
be passed by value by the device function and
passed by reference by the host function, which
will cause the constexpr variable captured by
the lambda function in host compilation but
not in the device compilation. The discrepancy
in the lambda captures will violate ODR and
causes UB for kernels using these lambdas.
This PR fixes the issue by identifying
discrepancy of ODR/non-ODR usages of constexpr
local variables passed to host/device functions
and conservatively capture them.
Fixes: https://github.com/llvm/llvm-project/issues/132068
Commit: 1b6cbaa7b64f54b127d139d653468e213bae007e
https://github.com/llvm/llvm-project/commit/1b6cbaa7b64f54b127d139d653468e213bae007e
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/PrimType.h
M clang/test/AST/ByteCode/literals.cpp
Log Message:
-----------
[clang][bytecode] Refine diagnostics for volatile reads (#136857)
Differentiate between a volarile read via a lvalue-to-rvalue cast of a
volatile qualified subexpression and a read from a pointer with a
volatile base object.
Commit: 6dbc01e8015816e904687c03f0ea8afac817781d
https://github.com/llvm/llvm-project/commit/6dbc01e8015816e904687c03f0ea8afac817781d
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
M llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AMDGPU/fpext-free.ll
M llvm/test/CodeGen/AMDGPU/fpow.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/function-args.ll
M llvm/test/CodeGen/AMDGPU/function-returns.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.wave32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/lrint.ll
M llvm/test/CodeGen/AMDGPU/lround.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/strict_fpext.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
M llvm/test/CodeGen/AMDGPU/vector_rebroadcast.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vopc_dpp.mir
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
Log Message:
-----------
[AMDGPU][True16][CodeGen] update GFX11Plus codegen test with true16 flag (#135078)
This is a NFC patch.
This patch run a bulk update on CodeGen tests that are impacted by the
true16 features. This patch applies:
1. duplicate GFX11plus runlines and apply them with
"+mattr=+real-true16" and "+mattr=-real-true16"
2. update the test with the update script
For some GISEL runlines, the current CodeGen do not fully support the
true16 version. Still update the runlines, but comment out the failing
one, and added a "FIXME-TRUE16" comment to that test for easier
tracking. These test will be fixed in the following patches.
This is in a transition state that we support both
"+real-true16/-real-true16" in our code base. We plan to move to
"+real-true16" as default, and finally remove "-real-true16" mode and
test lines.
Commit: 1041d54bd4f693c1ac03077680ece67e03c99e22
https://github.com/llvm/llvm-project/commit/1041d54bd4f693c1ac03077680ece67e03c99e22
Author: John Harrison <harjohn at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/Handler/CancelRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/DisconnectRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/NextRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
M lldb/tools/lldb-dap/Protocol/ProtocolBase.h
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
M lldb/tools/lldb-dap/Transport.cpp
Log Message:
-----------
[lldb-dap] Updating the 'next' request handler use well structured types (#136642)
This updates the 'next' request to use well structured types. While
working on this I also simplified the 'RequestHandler' implementation to
better handle void responses by allowing requests to return a
'llvm::Error' instead of an 'llvm::Expected<std::monostate>'. This makes
it easier to write and understand request handles that have simple ack
responses.
Commit: 060f3f0dd1614b624b527e871019970e4303de11
https://github.com/llvm/llvm-project/commit/060f3f0dd1614b624b527e871019970e4303de11
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/include/clang/Frontend/CompilerInstance.h
M clang/include/clang/Lex/DependencyDirectivesScanner.h
M clang/include/clang/Lex/Preprocessor.h
M clang/include/clang/Lex/PreprocessorOptions.h
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningFilesystem.h
M clang/lib/Frontend/CompilerInstance.cpp
M clang/lib/Lex/PPLexerChange.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
M clang/unittests/Lex/PPDependencyDirectivesTest.cpp
Log Message:
-----------
[clang][deps] Make dependency directives getter thread-safe (#136178)
This PR fixes two issues in one go:
1. The dependency directives getter (a `std::function`) was being stored
in `PreprocessorOptions`. This goes against the principle where the
options classes are supposed to be value-objects representing the `-cc1`
command line arguments. This is fixed by moving the getter directly to
`CompilerInstance` and propagating it explicitly.
2. The getter was capturing the `ScanInstance` VFS. That's fine in
synchronous implicit module builds where the same VFS instance is used
throughout, but breaks down once you try to build modules asynchronously
(which forces the use of separate VFS instances). This is fixed by
explicitly passing a `FileManager` into the getter and extracting the
right instance of the scanning VFS out of it.
Commit: 385b07b5038ff65f084446a92849e54fd86bd3a7
https://github.com/llvm/llvm-project/commit/385b07b5038ff65f084446a92849e54fd86bd3a7
Author: Paul Kirth <paulkirth at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang-tools-extra/clang-doc/Serialize.cpp
Log Message:
-----------
[clang-doc][NFC] Remove else after return (#136443)
Commit: 0f5965fa9c67969e4de7374362b6af49bf400b3b
https://github.com/llvm/llvm-project/commit/0f5965fa9c67969e4de7374362b6af49bf400b3b
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/test/CIR/CodeGen/struct.c
M clang/test/CIR/CodeGen/struct.cpp
M clang/test/CIR/CodeGen/typedef.c
M clang/test/CIR/CodeGen/union.c
M clang/test/CIR/IR/struct.cir
Log Message:
-----------
[CIR] Introduce type aliases for records (#136387)
This introduces MLIR aliases for ClangIR record types. These are used in
the incubator and having skipped over them upstream is causing the tests
to diverge.
Commit: 3c9027c1d7aac0c1e54af13182f1b8f58d376115
https://github.com/llvm/llvm-project/commit/3c9027c1d7aac0c1e54af13182f1b8f58d376115
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/Serialization/ModuleManager.cpp
M clang/test/Modules/explicit-build.cpp
Log Message:
-----------
[clang][Modules] Clarify error message when size check fails in lookupModuleFile
Commit: dbb8434ff7b9bb414e2222cb8d9cddac599eadc6
https://github.com/llvm/llvm-project/commit/dbb8434ff7b9bb414e2222cb8d9cddac599eadc6
Author: Peter Collingbourne <peter at pcc.me.uk>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Log Message:
-----------
SelectionDAG: Add missing AddNodeIDCustom case for MDNodeSDNode.
Without this we ended up never deduplicating MDNodeSDNodes.
Reviewers: arsenm
Reviewed By: arsenm
Pull Request: https://github.com/llvm/llvm-project/pull/136805
Commit: 3b48e2a7508ab090b1b7c6a68f87e3eddad5473d
https://github.com/llvm/llvm-project/commit/3b48e2a7508ab090b1b7c6a68f87e3eddad5473d
Author: John Harrison <harjohn at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/tools/lldb-dap/Handler/RequestHandler.cpp
Log Message:
-----------
[lldb-dap] Ensure we acquire the SB API lock while handling requests. (#137026)
Acquiring the lock for the target should help ensure consistency with
other background operations, like the thread monitoring events that can
trigger run commands from a different thread.
Commit: 213424b94792d730510a12046abfc05e0262c985
https://github.com/llvm/llvm-project/commit/213424b94792d730510a12046abfc05e0262c985
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/source/Utility/ArchSpec.cpp
M lldb/unittests/Utility/ArchSpecTest.cpp
M llvm/include/llvm/BinaryFormat/MachO.h
Log Message:
-----------
Add MachO RISC-V CPU type and CPU subtype to llvm & lldb (#136785)
Add the enum values for MachO RISC-V CPU type and CPU subtype to
llvm and use in LLDB's ArchSpec.
Commit: bdf21ca8ac8a30ad1ace6732f05c11e812aca535
https://github.com/llvm/llvm-project/commit/bdf21ca8ac8a30ad1ace6732f05c11e812aca535
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
Log Message:
-----------
[LV] Fix missing entry in willGenerateVectors (#136712)
willGenerateVectors switches on opcodes of a recipe, but Histogram is
missing in the switch statement, which could cause a crash in some
cases. The crash was initially observed when developing another patch.
Commit: 98eb4761c8640968a922dab417dfa42ef2621c43
https://github.com/llvm/llvm-project/commit/98eb4761c8640968a922dab417dfa42ef2621c43
Author: alx32 <103613512+alx32 at users.noreply.github.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/test/tools/dsymutil/ARM/stmt-seq-macho.test
Log Message:
-----------
Fix stmt-seq-macho.test for little endian platforms (#137017)
The test YAML was created on a little-endian system, so its data is
stored in little-endian order. When the test runs on a big-endian host,
yaml2obj defaults to the host’s byte order, misreading the file as
big-endian and causing a failure.
This change explicitly marks the YAML as little-endian, guaranteeing
that yaml2obj always uses the correct byte order, no matter which
machine runs the test.
The reason that during creation, obj2yaml doesn't specify the endianness
is because the endianness is set as an optional parameter and therefore
it won't be specified if it matches the platform default. Ref:
https://github.com/llvm/llvm-project/blob/d7215c0ee2e4bca1ce87b956335ef6a2cddaf16f/llvm/lib/ObjectYAML/MachOYAML.cpp#L105
Commit: d3e1fd62aaa7c929952f9e7985c81f05af89476c
https://github.com/llvm/llvm-project/commit/d3e1fd62aaa7c929952f9e7985c81f05af89476c
Author: Matthias Springer <me at m-sp.org>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/test/Dialect/LLVMIR/canonicalize.mlir
Log Message:
-----------
[mlir][LLVM] Improve `llvm.extractvalue` folder (#136861)
Continue the traversal on the SSA chain of the inserted value for
additional folding opportunities.
Commit: 5bb4cf9d9189c41de50adffd960eb2188140eb9c
https://github.com/llvm/llvm-project/commit/5bb4cf9d9189c41de50adffd960eb2188140eb9c
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/hdr/CMakeLists.txt
A libc/hdr/offsetof_macros.h
M libc/include/llvm-libc-types/CMakeLists.txt
M libc/include/llvm-libc-types/jmp_buf.h
M libc/include/setjmp.yaml
M libc/src/setjmp/CMakeLists.txt
A libc/src/setjmp/linux/CMakeLists.txt
A libc/src/setjmp/linux/sigsetjmp_epilogue.cpp
M libc/src/setjmp/setjmp_impl.h
A libc/src/setjmp/siglongjmp.cpp
A libc/src/setjmp/siglongjmp.h
A libc/src/setjmp/sigsetjmp.h
A libc/src/setjmp/sigsetjmp_epilogue.h
M libc/src/setjmp/x86_64/CMakeLists.txt
M libc/src/setjmp/x86_64/setjmp.cpp
A libc/src/setjmp/x86_64/sigsetjmp.cpp
M libc/test/src/setjmp/CMakeLists.txt
A libc/test/src/setjmp/sigsetjmp_test.cpp
Log Message:
-----------
[libc] implement sigsetjmp/siglongjmp for x86-64 (#136072)
Commit: a0fce0ba31277b6cbdb335a9529477415a01760d
https://github.com/llvm/llvm-project/commit/a0fce0ba31277b6cbdb335a9529477415a01760d
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/plugin_config.bzl
Log Message:
-----------
[bazel] Use non_arc_srcs instead of passing -fno-objc-arc (#137037)
This is the recommended way in bazel to differentiate between files that
require arc and those that require it be disabled. This matters
depending on the toolchain since the order of these flags may not have
been correct and we were relying on overwriting the default.
Commit: b8e420e424b41f67019155055f4f600ba0454189
https://github.com/llvm/llvm-project/commit/b8e420e424b41f67019155055f4f600ba0454189
Author: Finn Plummer <canadienfinn at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Parse/ParseHLSLRootSignature.h
M clang/lib/Parse/ParseHLSLRootSignature.cpp
M clang/unittests/Parse/ParseHLSLRootSignatureTest.cpp
M llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h
Log Message:
-----------
Reland "[HLSL][RootSignature] Implement initial parsing of the descriptor table clause params" (#136740)
This pr relands #133800.
It addresses the compilation error of using a shadowed name `Register`
for both the struct name and the data member holding this type:
`Register Register`. It resolves the issues my renaming the data members
called `Register` to `Reg`.
This issue was not caught as the current pre-merge checks do not include
a build of `llvm;clang` using the gcc/g++ compilers and this is not
erroneous with clang/clang++.
Second part of #126569
---------
Co-authored-by: Finn Plummer <finnplummer at microsoft.com>
Commit: bc1198719e206b2b6928ac437cb59107b45662d6
https://github.com/llvm/llvm-project/commit/bc1198719e206b2b6928ac437cb59107b45662d6
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/runtimes/CMakeLists.txt
Log Message:
-----------
[Offload] Fix missing dependency on `clang-nvlink-wrapper' (#137033)
Summary:
It's possible that this won't be built in time for the runtimes build.
Add this as a dependency. We will also need to make this future proof
and loop over all the enabled targets, but that's a later update.
Commit: 3fbbe9b8d08957f901d92f04becfe4352ccc2261
https://github.com/llvm/llvm-project/commit/3fbbe9b8d08957f901d92f04becfe4352ccc2261
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Add exit phi operands during initial construction (NFC). (#136455)
Add incoming exit phi operands during the initial VPlan construction.
This ensures all users are added to the initial VPlan and is also needed
in preparation to retaining exiting edges during initial construction.
PR: https://github.com/llvm/llvm-project/pull/136455
Commit: a05aeda30534fe30dfcccebb61b78489847e5192
https://github.com/llvm/llvm-project/commit/a05aeda30534fe30dfcccebb61b78489847e5192
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefMemberChecker.cpp
M clang/test/Analysis/Checkers/WebKit/unchecked-members.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-members.cpp
Log Message:
-----------
[RawPtrRefMemberChecker] Member variable checker should allow T* in smart pointer classes (#136503)
This PR fixes member variable checker to allow the usage of T* in smart
pointer classes. e.g. alpha.webkit.NoUncheckedPtrMemberChecker should
allow T* to appear within RefPtr.
Commit: f07511a0e0d2ac9bee9ae12a9ad68e279e352634
https://github.com/llvm/llvm-project/commit/f07511a0e0d2ac9bee9ae12a9ad68e279e352634
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M libc/src/setjmp/CMakeLists.txt
M libc/src/setjmp/x86_64/sigsetjmp.cpp
Log Message:
-----------
[libc] build fix for sigsetjmp (#137047)
This PR fixes the build failure due to the `sigsetjmp` implementation.
1. Use a most relaxed input constraint to fix `clang` build.
2. Avoid create alias target if os directory for `sigsetjmp_epilogue`
does not exist.
Commit: 563ab56497104199b9fd57df9bd162f2b02cbe92
https://github.com/llvm/llvm-project/commit/563ab56497104199b9fd57df9bd162f2b02cbe92
Author: Ely Ronnen <elyronnen at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/include/lldb/API/SBExecutionContext.h
M lldb/include/lldb/API/SBInstructionList.h
M lldb/source/API/SBInstructionList.cpp
M lldb/tools/lldb-dap/Handler/SourceRequestHandler.cpp
Log Message:
-----------
[lldb-dap] Show load addresses in disassembly (#136755)
Improves the lldb-dap disassembly by showing load addresses in
disassembly, same as in a regular LLDB `disassemble` command by default.
Before:
After:
Commit: 0fdb908e39b22a3c630bb6b727d71748df96f8ac
https://github.com/llvm/llvm-project/commit/0fdb908e39b22a3c630bb6b727d71748df96f8ac
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M flang/lib/Optimizer/Dialect/CUF/CUFToLLVMIRTranslation.cpp
Log Message:
-----------
[flang][cuda][NFC] Update binary name (#137034)
Name was changed in https://github.com/llvm/llvm-project/pull/135478
Commit: ff36508d2189ca9e414262f2c7a3b3a1d4974108
https://github.com/llvm/llvm-project/commit/ff36508d2189ca9e414262f2c7a3b3a1d4974108
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
Log Message:
-----------
[VPlan] Remove redundant setting of parent in createLoopRegion (NFC).
The regions parents will be set when the parents are set after creating
the parent region.
Commit: 112014ba67792e00ff719d640a5fddb79d78674d
https://github.com/llvm/llvm-project/commit/112014ba67792e00ff719d640a5fddb79d78674d
Author: Shafik Yaghmour <shafik.yaghmour at intel.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/Sema/SemaExprCXX.cpp
Log Message:
-----------
[Clang][NFC] Use temporary instead of one use local variable when creating APValue (#137029)
Static analysis flagged this code b/c we should have been using
std::move when passing by value since the value is not used anymore. In
this case the simpler fix is just to use a temporary value as many of
the other cases where we simply use MakeIntValue to then create an
APValue result from it.
Commit: 71f2c1e2045abaa4c5dcf47edfd1adbc407e7563
https://github.com/llvm/llvm-project/commit/71f2c1e2045abaa4c5dcf47edfd1adbc407e7563
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Use early exit in ::extractLastLaneOfFirstOperand (NFC).
Reduce indent level, as suggested in
https://github.com/llvm/llvm-project/pull/136455.
Commit: f4189817df9b32903d0704028c8d2ea9b0ea5908
https://github.com/llvm/llvm-project/commit/f4189817df9b32903d0704028c8d2ea9b0ea5908
Author: Henrich Lauko <xlauko at mail.muni.cz>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
Log Message:
-----------
[CIR] Create CIR_TypedAttr common class (#136852)
Introduce common base class for attributes with single type parameter.
This mirrors incubator changes introduced in https://github.com/llvm/clangir/pull/1583
Commit: ff6a23d65eccba0991244c4127506452e1030393
https://github.com/llvm/llvm-project/commit/ff6a23d65eccba0991244c4127506452e1030393
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
A llvm/test/CodeGen/RISCV/zalasr-offset-folding.ll
Log Message:
-----------
[RISCV] Return false for Zalasr load/store in isWorthFoldingAdd. (#136799)
The Zalasr load/store don't support reg-imm addressing modes so they
can't fold an ADDI.
Commit: cef9ed56f8c19258f8805512e58627c5bc79bf98
https://github.com/llvm/llvm-project/commit/cef9ed56f8c19258f8805512e58627c5bc79bf98
Author: Dave Lee <davelee.com at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp
Log Message:
-----------
[lldb] Fix typo in tagged-pointer syntax string (NFC) (#137069)
Commit: 6f5b98b3247969eb85135141bdae4a2d6aeb284a
https://github.com/llvm/llvm-project/commit/6f5b98b3247969eb85135141bdae4a2d6aeb284a
Author: Ely Ronnen <elyronnen at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/include/lldb/Utility/CompletionRequest.h
M lldb/packages/Python/lldbsuite/test/lldbtest.py
M lldb/source/API/SBCommandInterpreter.cpp
M lldb/source/Commands/CommandCompletions.cpp
M lldb/test/API/commands/expression/completion/TestExprCompletion.py
Log Message:
-----------
[lldb] returning command completions up to a maximum (#135565)
- Adding `max_return_elements` field to `CompletionRequest`.
- adding maximum checks to `SymbolCompleter` and `SourceFileCompleter`.
Fixes #135553
Commit: ee617f195a2677abd274e4047246fed3a1501b77
https://github.com/llvm/llvm-project/commit/ee617f195a2677abd274e4047246fed3a1501b77
Author: Guy David <49722543+guy-david at users.noreply.github.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
Log Message:
-----------
[NFC] [AArch64] Simplify offset scaling in ldst-opt (#137044)
Commit: cd826d6e840ed33ad88458c862da5f9fcc6e908c
https://github.com/llvm/llvm-project/commit/cd826d6e840ed33ad88458c862da5f9fcc6e908c
Author: Reid Kleckner <rnk at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGDebugInfo.h
M clang/lib/CodeGen/CodeGenModule.cpp
R clang/test/CodeGenCXX/debug-info-dtor-implicit-args.cpp
Log Message:
-----------
Revert "[Clang,debuginfo] added vtt parameter in destructor DISubroutineType (#130674)"
This reverts commit 27c1aa9b9cf9e0b14211758ff8f7d3aaba24ffcf.
See comments on PR. After this change, Clang now asserts like this:
clang: ../llvm/include/llvm/IR/Metadata.h:1435: const MDOperand &llvm::MDNode::getOperand(unsigned int) const: Assertion `I < getNumOperands() && "Out of range"' failed.
...
#8 0x000055f345c4e4cb clang::CodeGen::CGDebugInfo::getOrCreateInstanceMethodType()
#9 0x000055f345c5ba4f clang::CodeGen::CGDebugInfo::EmitFunctionDecl()
#10 0x000055f345b52519 clang::CodeGen::CodeGenModule::EmitExternalFunctionDeclaration()
This is due to pre-existing jankiness in the way BPF emits extra
declarations for debug info, but we should rollback and then fix forward.
Commit: dd17cf4480fc55c38813769a46fb2807397d8f72
https://github.com/llvm/llvm-project/commit/dd17cf4480fc55c38813769a46fb2807397d8f72
Author: Dave Lee <davelee.com at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/include/lldb/Interpreter/CommandObject.h
Log Message:
-----------
[lldb] Minor improvements to AddNamesMatchingPartialString (NFC) (#136760)
The primary changes are:
1. Avoid allocating a temporary `std::string` each time in the loop
2. Use `starts_with` instead of `find(...) == 0`
Commit: 0e0a1665fa340b9f1934d12aff818064aaf289ef
https://github.com/llvm/llvm-project/commit/0e0a1665fa340b9f1934d12aff818064aaf289ef
Author: Reid Kleckner <rnk at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/CodeGen/CodeGenModule.cpp
Log Message:
-----------
Revert unintentional diff from cd826d6e840ed33ad88458c862da5f9fcc6e908c
This is part of a forthcoming fix for issues observed in #91310, and was
unintentionally committed as part of the VTT type changes revert
Commit: b6f32ad8b03dccaba0db7ded9d561ee83e4530ab
https://github.com/llvm/llvm-project/commit/b6f32ad8b03dccaba0db7ded9d561ee83e4530ab
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
M llvm/test/CodeGen/NVPTX/LoadStoreVectorizer.ll
M llvm/test/CodeGen/NVPTX/and-or-setcc.ll
M llvm/test/CodeGen/NVPTX/atomics.ll
M llvm/test/CodeGen/NVPTX/bf16-instructions.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions-approx.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/convert-fp-i8.ll
M llvm/test/CodeGen/NVPTX/convert-sm100.ll
M llvm/test/CodeGen/NVPTX/convert-sm100a.ll
M llvm/test/CodeGen/NVPTX/convert-sm80.ll
M llvm/test/CodeGen/NVPTX/convert-sm90.ll
M llvm/test/CodeGen/NVPTX/copysign.ll
M llvm/test/CodeGen/NVPTX/distributed-shared-cluster.ll
M llvm/test/CodeGen/NVPTX/div.ll
M llvm/test/CodeGen/NVPTX/f16-abs.ll
M llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/f32-ex2.ll
M llvm/test/CodeGen/NVPTX/f32-lg2.ll
M llvm/test/CodeGen/NVPTX/fabs-intrinsics.ll
M llvm/test/CodeGen/NVPTX/fexp2.ll
M llvm/test/CodeGen/NVPTX/flog2.ll
M llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
M llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll
M llvm/test/CodeGen/NVPTX/fma-relu-instruction-flag.ll
M llvm/test/CodeGen/NVPTX/fp-contract.ll
M llvm/test/CodeGen/NVPTX/frem.ll
M llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
M llvm/test/CodeGen/NVPTX/intrinsics.ll
M llvm/test/CodeGen/NVPTX/ldg-invariant.ll
M llvm/test/CodeGen/NVPTX/ldu-ldg.ll
M llvm/test/CodeGen/NVPTX/load-store-scalars.ll
M llvm/test/CodeGen/NVPTX/load-store-vectors.ll
M llvm/test/CodeGen/NVPTX/math-intrins.ll
M llvm/test/CodeGen/NVPTX/misched_func_call.ll
M llvm/test/CodeGen/NVPTX/param-add.ll
M llvm/test/CodeGen/NVPTX/rcp-opt.ll
M llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
M llvm/test/CodeGen/NVPTX/redux-sync-f32.ll
M llvm/test/CodeGen/NVPTX/reg-types.ll
M llvm/test/CodeGen/NVPTX/st-param-imm.ll
M llvm/test/CodeGen/NVPTX/surf-read-cuda.ll
M llvm/test/CodeGen/NVPTX/tex-read-cuda.ll
M llvm/test/CodeGen/NVPTX/variadics-backend.ll
M llvm/test/DebugInfo/NVPTX/debug-info.ll
Log Message:
-----------
[NVPTX] Switch to untyped float registers (#137011)
Register types in PTX are simply syntactic sugar and emitting them has
added lots of unnecessary complexity to the NVPTX backend. This change
takes the first step to their removal by using ".b" registers instead of
".f" in all cases. This should shake out any potential issues or bugs in
ptxas preventing full removal and pre-fetches many of the required test
updates.
Commit: 9a8f90dba3f8c25cbb3525a482053d3abcd3fddc
https://github.com/llvm/llvm-project/commit/9a8f90dba3f8c25cbb3525a482053d3abcd3fddc
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
A llvm/include/llvm/ProfileData/IndexedMemProfData.h
M llvm/lib/ProfileData/CMakeLists.txt
A llvm/lib/ProfileData/IndexedMemProfData.cpp
M llvm/lib/ProfileData/InstrProfWriter.cpp
Log Message:
-----------
[memprof] Move writeMemProf to a separate file (#137051)
This patch moves writeMemProf and its subroutines to a separate file.
The intent is as follows:
- Reduce the size of InstrProfWriter.cpp.
- Move the subroutines to a separate file because they don't interact
with anything else in InstrProfWriter.cpp.
Remarks:
- The new file is named IndexedMemProfData.cpp without "Writer" in the
name so that we can move the reader code to this file in the future.
- This patch just moves code without changing the function signatures
for now. It might make sense to implement a class encompassing
"serialize" and "deserialize" methods for IndexedMemProfData, but
that's left to subsequent patches.
Commit: d72f1f92f469a5d0ee28dc89f72977634d90d111
https://github.com/llvm/llvm-project/commit/d72f1f92f469a5d0ee28dc89f72977634d90d111
Author: GeorgeHuyubo <113479859+GeorgeHuyubo at users.noreply.github.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
Log Message:
-----------
Bug fix in FindModuleUUID (#137075)
In some core file, we are seeing that it's not always the case that the
ELF header would exist in the first region in NT_FILES section.
Therefore the FindModuleUUID is not able to find the module UUID by just
returning the first entry with path matching.
This fix change the behavior to continue search the NT_FILE entries
until finding a valid UUID with path matching.
Co-authored-by: George Hu <georgehuyubo at gmail.com>
Commit: 0d00b6bc3b459122de47d16c5153887063f4ea4b
https://github.com/llvm/llvm-project/commit/0d00b6bc3b459122de47d16c5153887063f4ea4b
Author: gulfemsavrun <gulfem at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/hdr/CMakeLists.txt
R libc/hdr/offsetof_macros.h
M libc/include/llvm-libc-types/CMakeLists.txt
M libc/include/llvm-libc-types/jmp_buf.h
M libc/include/setjmp.yaml
M libc/src/setjmp/CMakeLists.txt
R libc/src/setjmp/linux/CMakeLists.txt
R libc/src/setjmp/linux/sigsetjmp_epilogue.cpp
M libc/src/setjmp/setjmp_impl.h
R libc/src/setjmp/siglongjmp.cpp
R libc/src/setjmp/siglongjmp.h
R libc/src/setjmp/sigsetjmp.h
R libc/src/setjmp/sigsetjmp_epilogue.h
M libc/src/setjmp/x86_64/CMakeLists.txt
M libc/src/setjmp/x86_64/setjmp.cpp
R libc/src/setjmp/x86_64/sigsetjmp.cpp
M libc/test/src/setjmp/CMakeLists.txt
R libc/test/src/setjmp/sigsetjmp_test.cpp
Log Message:
-----------
Revert "[libc] build fix for sigsetjmp (#137047)" (#137077)
This reverts commit f07511a0e0d2ac9bee9ae12a9ad68e279e352634.
This reverts commit 5bb4cf9d9189c41de50adffd960eb2188140eb9c.
It caused a CMake configuration issue.
Commit: 6388a7acf7e31fdc7b9c168bd6ce0f4d25c98cd0
https://github.com/llvm/llvm-project/commit/6388a7acf7e31fdc7b9c168bd6ce0f4d25c98cd0
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
Log Message:
-----------
[RISCV] Check the extension type for atomic loads in isel patterns. (#137019)
Previously we ignored the extension type and only used the memory type.
The extension type on RISC-V today can only be nonextload, extload, or
sextload. It is ok to treat extload as the same as sextload so ignoring
the extension type is fine.
For #136502, we want to support zextload as well so we will need to
disambiguate based on the extension type.
I wanted to use IsAtomic/IsZeroExtLoad/IsSignExtLoad/IsAnyExtLoad flags
from PatFrags to autogenerate the predicates, but those aren't hooked up
properly in tablegen for ISD::ATOMIC_LOAD. Fixing that will impact other
targets as almost all of them also ignore the extension type.
Commit: 0547e84181ff10b24d6363bbfc97f168fe245397
https://github.com/llvm/llvm-project/commit/0547e84181ff10b24d6363bbfc97f168fe245397
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/IPO/FunctionAttrs.cpp
M llvm/test/Transforms/FunctionAttrs/initializes.ll
Log Message:
-----------
[FunctionAttrs] Bail if initializes range overflows 64-bit signed int (#137053)
Otherwise the range doesn't make sense since we interpret it as signed.
Fixes #134115
Commit: f75295f7982ee893473db6c3dc59886e02cd728c
https://github.com/llvm/llvm-project/commit/f75295f7982ee893473db6c3dc59886e02cd728c
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/ProfileData/BUILD.gn
Log Message:
-----------
[gn build] Port 9a8f90dba3f8
Commit: 4f36ada1e205df08ad4377df88729f8defb36558
https://github.com/llvm/llvm-project/commit/4f36ada1e205df08ad4377df88729f8defb36558
Author: Bob Wilson <bob.wilson at apple.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/test/Preprocessor/print-header-json.c
M clang/tools/driver/driver.cpp
Log Message:
-----------
[Clang] Fix crash when -header-include-filtering is not specified (#136232)
If you specify -header-include-format=json, the only filtering option
currently supported is -header-include-filtering=only-direct-system. If
you specify some other filtering option, Clang gives an error message.
But, if you do not specify the filtering option at all, Clang crashes
when producing the error message, since it tries to get the value of the
unused option.
Commit: 239718055d7260caa3e6631e82d68ac27e01c1f4
https://github.com/llvm/llvm-project/commit/239718055d7260caa3e6631e82d68ac27e01c1f4
Author: Robert O'Callahan <rocallahan at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/source/Commands/CommandObjectProcess.cpp
M lldb/source/Commands/Options.td
A lldb/test/API/commands/process/reverse-continue/Makefile
A lldb/test/API/commands/process/reverse-continue/TestReverseContinue.py
A lldb/test/API/commands/process/reverse-continue/TestReverseContinueNotSupported.py
A lldb/test/API/commands/process/reverse-continue/main.c
M llvm/docs/ReleaseNotes.md
Log Message:
-----------
[lldb] Implement CLI support for reverse-continue (#132783)
This introduces the options "-F/--forward" and "-R/--reverse" to
`process continue`.
These only work if you're running with a gdbserver backend that supports
reverse execution, such as rr. For testing we rely on the fake
reverse-execution functionality in `lldbreverse.py`.
Commit: 55160e6a89820f219eaa218fa02da2006213ed2c
https://github.com/llvm/llvm-project/commit/55160e6a89820f219eaa218fa02da2006213ed2c
Author: Henrik G. Olsson <hnrklssn at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/AST/ExprConstant.cpp
M clang/test/AST/ByteCode/cxx20.cpp
M clang/test/SemaCXX/constant-expression-cxx11.cpp
Log Message:
-----------
[ConstEval] Fix crash when comparing strings past the end (#137078)
When `ArePotentiallyOverlappingStringLiterals`, added in
https://github.com/llvm/llvm-project/pull/109208, compares string
literals it drops the front of the string with the greatest offset from
its base pointer. The number of characters dropped is equal to the
difference between the two strings' offsets from their base pointers.
This would trigger an assert when the resulting offset is past the end
of the object. Not only are one-past-the-end pointers legal constructs,
the compiler should not crash even when faced with illegal constructs.
rdar://149865910
Commit: de2f9395e6617e58e168fa3b2886f85109849787
https://github.com/llvm/llvm-project/commit/de2f9395e6617e58e168fa3b2886f85109849787
Author: Adrian Prantl <aprantl at apple.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/source/Plugins/ExpressionParser/Clang/ClangModulesDeclVendor.cpp
Log Message:
-----------
[lldb] Quote module name in error message (#137083)
rdar://149554634
Commit: 93705c3a76e9b00137be84fbc6ef3b4af5fcc031
https://github.com/llvm/llvm-project/commit/93705c3a76e9b00137be84fbc6ef3b4af5fcc031
Author: Henrik G. Olsson <hnrklssn at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/AST/ExprConstant.cpp
M clang/test/AST/ByteCode/cxx20.cpp
M clang/test/SemaCXX/constant-expression-cxx11.cpp
Log Message:
-----------
Revert "[ConstEval] Fix crash when comparing strings past the end" (#137088)
Reverts llvm/llvm-project#137078
Commit: 6ba704a7f4e72ba088fa19c7622e42b9c460da47
https://github.com/llvm/llvm-project/commit/6ba704a7f4e72ba088fa19c7622e42b9c460da47
Author: John Harrison <harjohn at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/tools/lldb-dap/Handler/NextRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
M lldb/tools/lldb-dap/Handler/StepInRequestHandler.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
Log Message:
-----------
[lldb-dap] Migrate 'stepIn' request to well structured types. (#137071)
Migrates the 'stepIn' request handler to have well structured types
instead of raw json values.
I also noticed in the 'next' request handler we were not passing the
'RunMode' flag. Updated the 'next' request handler as well.
Commit: fc7fee8360b3e69777fa1c5c3c563728b1a2836f
https://github.com/llvm/llvm-project/commit/fc7fee8360b3e69777fa1c5c3c563728b1a2836f
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
M llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
M llvm/test/CodeGen/RISCV/xqccmp-additional-stack.ll
M llvm/test/CodeGen/RISCV/xqccmp-callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
M llvm/test/CodeGen/RISCV/xqccmp-with-float.ll
M llvm/test/CodeGen/RISCV/zcmp-additional-stack.ll
M llvm/test/CodeGen/RISCV/zcmp-with-float.ll
Log Message:
-----------
Revert "[RISCV] Allow spilling to unused Zcmp Stack (#125959)" (#137060)
This reverts commit 50cdf6cbc5035345507bb4d23fcb0292272754eb.
This patch causes miscompiles with vector and produces some odd code for
ilp32e.
Commit: 905f1d8068a5bc1149732b46afc3f5dd780aa5d9
https://github.com/llvm/llvm-project/commit/905f1d8068a5bc1149732b46afc3f5dd780aa5d9
Author: Muzammil <55665739+Muzammiluddin-Syed-ECE at users.noreply.github.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/GPU/Transforms/Passes.h
M mlir/lib/Dialect/GPU/Transforms/SubgroupReduceLowering.cpp
M mlir/test/Dialect/GPU/subgroup-reduce-lowering.mlir
M mlir/test/lib/Dialect/GPU/TestGpuRewrite.cpp
Log Message:
-----------
[mlir][AMDGPU] Implement gpu.subgroup_reduce with DPP intrinsics on AMD GPUs (#133204)
When performing cross-lane reductions using subgroup_reduce ops across
contiguous lanes on AMD GPUs, lower to Data Parallel Primitives (DPP)
ops when possible. This reduces latency on applicable devices.
See related [Issue](https://github.com/iree-org/iree/issues/20007)
To do:
- Improve lowering to subgroup_reduce in compatible matvecs (these get
directly lowered to gpu.shuffles in an earlier pass)
---------
Signed-off-by: Muzammiluddin Syed <muzasyed at amd.com>
Commit: 0400b8e8fd2ff66c8faab1fa818dec8199d969ce
https://github.com/llvm/llvm-project/commit/0400b8e8fd2ff66c8faab1fa818dec8199d969ce
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/test/Driver/fsanitize.c
M clang/test/Driver/sanitizer-ld.c
Log Message:
-----------
[NFC][CFI] Add CFI minimal runtime tests (#137093)
Commit: 9ad219372a31ec362b8ea462d694b8b819127235
https://github.com/llvm/llvm-project/commit/9ad219372a31ec362b8ea462d694b8b819127235
Author: Evgenii Kudriashov <evgenii.kudriashov at intel.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/test/CodeGen/X86/extractelement-load.ll
Log Message:
-----------
[X86][NFC] Precommit test for #136520
Commit: adab66f7a5b1f0f9ee00f42cf0ac517ba2b58e90
https://github.com/llvm/llvm-project/commit/adab66f7a5b1f0f9ee00f42cf0ac517ba2b58e90
Author: Jorge Gorbe Moya <jgorbe at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Add missing deps after 905f1d8068a5bc1149732b46afc3f5dd780aa5d9
Commit: b45225fd0c756d969f1188baaef374dffd561aa2
https://github.com/llvm/llvm-project/commit/b45225fd0c756d969f1188baaef374dffd561aa2
Author: Jim Lin <jim at andestech.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/utils/vim/syntax/llvm.vim
Log Message:
-----------
[Utils][vim] Add missing highlights for disjoint (#136801)
This patch adds the `disjoint` as keyword.
Commit: 5981be76925c2d6ee5b33029332beae254addb46
https://github.com/llvm/llvm-project/commit/5981be76925c2d6ee5b33029332beae254addb46
Author: Jim Lin <jim at andestech.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/test/Driver/riscv-cpus.c
M clang/test/Misc/target-invalid-cpu-note/riscv.c
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/RISCVProcessors.td
Log Message:
-----------
[RISCV] Add Andes A45/AX45 processor definition (#136832)
Andes A45/AX45 are 32/64bit in-order dual-issue 8-stage pipeline
linux-capable CPU implementing the RV[32|64]IMAFDC_Zba_Zbb_Zbs ISA
extensions. They are developed by Andes Technology
https://www.andestech.com, a RISC-V IP provider.
The overviews for A45/AX45:
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-a45/
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45/
Scheduling model will be implemented in a later PR.
Commit: a68c8e831452febc82ffb4091134aeb87ca52c2b
https://github.com/llvm/llvm-project/commit/a68c8e831452febc82ffb4091134aeb87ca52c2b
Author: Cedric <14017092+douyixuan at users.noreply.github.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/Vector/invalid.mlir
Log Message:
-----------
[mlir][vector] Fix parser of vector.transfer_read (#133721)
This PR adds a check in the parser to prevent a crash when
vector.transfer_read fails to create minor identity permutation. map.
Fixes #132851
a.mlir
```
module {
func.func @test_vector.transfer_read(%arg1: memref<?xindex>) -> vector<3x4xi32> {
%c3_i32 = arith.constant 3 : i32
%0 = vector.transfer_read %arg1[%c3_i32, %c3_i32], %c3_i32 : memref<?xindex>, vector<3x4xi32>
return %0 : vector<3x4xi32>
}
}
```
Commit: 178cdbf746bbc49ad18b5e83a95514ddd42f764c
https://github.com/llvm/llvm-project/commit/178cdbf746bbc49ad18b5e83a95514ddd42f764c
Author: Jorge Gorbe Moya <jgorbe at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
[bazel] Add missing deps in mlir/test/BUILD.bazel after 905f1d8068a5bc1149732b46afc3f5dd780aa5d9
Commit: 30fec128e8cc515392521628771510b347411c28
https://github.com/llvm/llvm-project/commit/30fec128e8cc515392521628771510b347411c28
Author: Muzammil <55665739+Muzammiluddin-Syed-ECE at users.noreply.github.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/lib/Dialect/GPU/CMakeLists.txt
Log Message:
-----------
[mlir][AMDGPU] Add missing dependency (#137107)
Add missing deps after
https://github.com/llvm/llvm-project/commit/905f1d8068a5bc1149732b46afc3f5dd780aa5d9
---------
Signed-off-by: Muzammiluddin Syed <muzasyed at amd.com>
Commit: ea0dbee80813edf1c8a57d1c1bfd7fadee71d3fa
https://github.com/llvm/llvm-project/commit/ea0dbee80813edf1c8a57d1c1bfd7fadee71d3fa
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/ProfileData/IndexedMemProfData.cpp
M llvm/lib/ProfileData/InstrProfReader.cpp
Log Message:
-----------
[memprof] Move IndexedMemProfReader::deserialize to IndexedemProfData.cpp (NFC) (#137089)
This patch moves IndexedMemProfReader::deserialize and its subroutines
to IndexedMemProfData.cpp, building on:
commit 9a8f90dba3f8c25cbb3525a482053d3abcd3fddc
Author: Kazu Hirata <kazu at google.com>
Date: Wed Apr 23 15:39:45 2025 -0700
The intent is as follows:
- Reduce the size of InstrProfReader.cpp.
- Move the subroutines to a separate file because they don't interact
with anything else in InstrProfReader.cpp.
Commit: de1af6b7271c6f4fc67848a849cf8fa6000d2b97
https://github.com/llvm/llvm-project/commit/de1af6b7271c6f4fc67848a849cf8fa6000d2b97
Author: Henrik G. Olsson <hnrklssn at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/AST/ExprConstant.cpp
M clang/test/AST/ByteCode/cxx20.cpp
M clang/test/SemaCXX/constant-expression-cxx11.cpp
Log Message:
-----------
Eval string one past end reland (#137091)
Relands #137078 after updating clang/test/AST/ByteCode/cxx20.cpp to
account for diagnostic outputs that differ between Linux and macOS.
Commit: 0975c09c671aca48c25b1f5952a675931ae93702
https://github.com/llvm/llvm-project/commit/0975c09c671aca48c25b1f5952a675931ae93702
Author: Oliver Hunt <oliver at apple.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
A clang/test/Modules/Inputs/PR137102/module.modulemap
A clang/test/Modules/Inputs/PR137102/type_aware_destroying_new_delete.h
A clang/test/Modules/type-aware-destroying-new-and-delete-modules.cpp
A clang/test/PCH/Inputs/type_aware_destroying_new_delete.h
A clang/test/PCH/type-aware-destroying-new-and-delete-pch.cpp
Log Message:
-----------
[clang][p2719] Module deserialization does not restore allocator flags (#137102)
When serializing and deserializing a FunctionDecl we don't recover
whether or not the decl was a type aware allocator or destroying delete,
because in the final PR that information was placed in a side table in
ASTContext.
In principle it should be possible to re-do the semantic checks to
determine what these flags should be when deserializing, but it seems
like the most robust path is simply recording the flags directly in the
serialized AST.
Commit: e6466420505d9940fda087f30a500fb03e5507b5
https://github.com/llvm/llvm-project/commit/e6466420505d9940fda087f30a500fb03e5507b5
Author: Bruno Cardoso Lopes <bruno.cardoso at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/test/Dialect/LLVMIR/invalid.mlir
M mlir/test/Dialect/LLVMIR/module-roundtrip.mlir
M mlir/test/Target/LLVMIR/Import/module-flags.ll
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[MLIR][LLVM] Allow strings in module flag value (#136793)
Expand support a bit beyond integers.
Next step is to support more complex metadata values (e.g. !"CG Profile"
and !"ProfileSummary"), but that's a bit more complex and deserves it
own PR.
Commit: cb8495c0fcf32592c6fcd23429b702dccb57d2eb
https://github.com/llvm/llvm-project/commit/cb8495c0fcf32592c6fcd23429b702dccb57d2eb
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/Driver/SanitizerArgs.cpp
M clang/test/Driver/fsanitize.c
M clang/test/Driver/sanitizer-ld.c
Log Message:
-----------
[Driver][CFI] Add missing '-' into error message (#137097)
Co-authored-by: Jim Lin <jim at andestech.com>
Commit: cd92d8db34afd95335697f85a527028fa8309d18
https://github.com/llvm/llvm-project/commit/cd92d8db34afd95335697f85a527028fa8309d18
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/test/Format/lit.local.cfg
Log Message:
-----------
[clang-format][NFC] Reformat clang/test/Format/lit.local.cfg with black
Commit: cb96a3dc07b0a26023633ae91fab9b4213730236
https://github.com/llvm/llvm-project/commit/cb96a3dc07b0a26023633ae91fab9b4213730236
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
A llvm/test/Transforms/PGOProfile/memprof-dump-matched-alloc-site.ll
M llvm/test/Transforms/PGOProfile/memprof-dump-matched-call-sites.ll
M llvm/test/Transforms/PGOProfile/memprof.ll
Log Message:
-----------
[memprof] Dump the number of matched frames (#137082)
This patch teaches readMemprof to dump the number of frames for each
allocation site match. This information helps us analyze what part of
the call stack in the MemProf profile has matched the IR.
Aside from updating existing test cases, this patch adds one more test
case, memprof-dump-matched-alloc-site.ll, because none of the existing
test cases has the number of frames greater than one.
Commit: 77fe6aaeaaf2b16e021675e92e543dafd18bbc0b
https://github.com/llvm/llvm-project/commit/77fe6aaeaaf2b16e021675e92e543dafd18bbc0b
Author: Wenju He <wenju.he at intel.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M libclc/cmake/modules/AddLibclc.cmake
Log Message:
-----------
[libclc] only check filename part of the source for avoiding duplication (#135710)
llvm-diff shows this PR has no changes to amdgcn--amdhsa.bc.
Motivation is that in our downstream the same category of target
built-ins, e.g. math, are organized in several different folders. For
example, in target SOURCES we have math-common/cos.cl, while in generic
SOURCES it is math/cos.cl. Based on current check rule that compares
both folder name and base filename, target math-common/cos.cl won't
override math/cos.cl when collecting source files from SOURCES files in
cmake function libclc_configure_lib_source.
With this PR, we allow folder name to be different in the process.
A notable change of this PR is that two entries in SOURCES with the same
base filename must not implements the same built-in.
Commit: 31c7997a4acb838c94d5ab40baaf154556532ad9
https://github.com/llvm/llvm-project/commit/31c7997a4acb838c94d5ab40baaf154556532ad9
Author: Thurston Dang <thurston at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/CodeGen/CGClass.cpp
M clang/lib/CodeGen/CGExpr.cpp
Log Message:
-----------
[cfi] Fix one -fno-sanitize-merge case, and add two TODOs (#135438)
-fno-sanitize-merge (introduced in
https://github.com/llvm/llvm-project/pull/120464) nearly works for CFI:
code that calls EmitCheck will already check the merge options. This
patch fixes one EmitTrapCheck call, which did not check the merge
options, and for two other EmitTrapChecks, adds two TODOs that explain
why it is difficult to fix them.
Commit: 096ab51de03437e38f97a48b8f2d453fb903414a
https://github.com/llvm/llvm-project/commit/096ab51de03437e38f97a48b8f2d453fb903414a
Author: Jason Molenda <jmolenda at apple.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/Process/Utility/CMakeLists.txt
A lldb/source/Plugins/Process/Utility/RegisterContextDarwin_riscv32.cpp
A lldb/source/Plugins/Process/Utility/RegisterContextDarwin_riscv32.h
A lldb/test/API/macosx/riscv32-corefile/Makefile
A lldb/test/API/macosx/riscv32-corefile/TestRV32MachOCorefile.py
A lldb/test/API/macosx/riscv32-corefile/create-empty-riscv-corefile.cpp
Log Message:
-----------
[lldb][MachO] MachO corefile support for riscv32 binaries (#137092)
Add support for reading a macho corefile with CPU_TYPE_RISCV and the
riscv32 general purpose register file. I added code for the floating
point and exception registers too, but haven't exercised this. If we
start putting the full CSR register bank in a riscv corefile, it'll be
in separate 4k byte chunks, but I don't have a corefile to test against
that so I haven't written the code to read it.
The RegisterContextDarwin_riscv32 is copied & in the style of the other
RegisterContextDarwin classes; it's not the first choice I would make
for representing this, but it wasn't worth changing for this cputype.
rdar://145014653
Commit: 054ee17f88fcd4dd8d646740b975ef1d2f4ea3aa
https://github.com/llvm/llvm-project/commit/054ee17f88fcd4dd8d646740b975ef1d2f4ea3aa
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn
Log Message:
-----------
[gn build] Port 096ab51de034
Commit: dbb0605f87d8b10171fba6291dd184f5fbf17683
https://github.com/llvm/llvm-project/commit/dbb0605f87d8b10171fba6291dd184f5fbf17683
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Log Message:
-----------
[SelectionDAG] Add NewSDValueDbgMsg to getAtomic.
Commit: fb0000b6624a5f2df25d10e3667111e96dd1abd5
https://github.com/llvm/llvm-project/commit/fb0000b6624a5f2df25d10e3667111e96dd1abd5
Author: Ebuka Ezike <yerimyah1 at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M lldb/include/lldb/Interpreter/OptionValueEnumeration.h
M lldb/source/Interpreter/OptionValueEnumeration.cpp
M lldb/test/API/commands/settings/TestSettings.py
Log Message:
-----------
[lldb][lldb-dap] Add ToJSON for OptionValueEnumeration (#137007)
This automatically enables reading enum settings in the SB API
Commit: de81b852fd8d2b654e1c7112f198026aa272c6b3
https://github.com/llvm/llvm-project/commit/de81b852fd8d2b654e1c7112f198026aa272c6b3
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/sve-varargs-caller-broken.ll
M llvm/test/CodeGen/AArch64/sve-varargs.ll
Log Message:
-----------
[AArch64] Allow variadic calls with SVE argument if it is named. (#136833)
The following case used to work:
void foo(svint32_t a, ...);
void bar(svint32_t a) { foo(a); }
but 6c9086d13fa7e1069e75ed2d139aae30ee3863c8 introduced a regression
that wasn't caught by the existing test `sve-varargs.ll` because the
call in the test wasn't a tail call and therefore skipped the code-path
with the `report_fatal_error`.
Commit: 45a3056a4b3b05d2d1bce7a96437dddead60c071
https://github.com/llvm/llvm-project/commit/45a3056a4b3b05d2d1bce7a96437dddead60c071
Author: Kiran Chandramohan <kiran.chandramohan at arm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
A flang/docs/FortranStandardsSupport.md
M flang/docs/index.md
Log Message:
-----------
[Flang] Add a Fortran Standards Support doc (#132195)
Commit: 7af555e524b5cddc338bf73b87d8b666611cefbc
https://github.com/llvm/llvm-project/commit/7af555e524b5cddc338bf73b87d8b666611cefbc
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/ARM/popcnt.ll
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
M llvm/test/CodeGen/RISCV/pr56457.ll
M llvm/test/CodeGen/RISCV/pr95271.ll
M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/RISCV/sextw-removal.ll
M llvm/test/CodeGen/Thumb2/mve-ctpop.ll
Log Message:
-----------
[ARM][RISCV] Partially revert #101786 (#137120)
The change as is breaks the Linux kernel build as pointed out in the
comments.
Commit: 886f1199f07bbcc385e35b90b9e620cbc8d76068
https://github.com/llvm/llvm-project/commit/886f1199f07bbcc385e35b90b9e620cbc8d76068
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Log Message:
-----------
[AMDGPU] Use variadic isa<>. NFC. (#137016)
Commit: bea110db3ed1fa1215bb8e22d2057019fcbd2d16
https://github.com/llvm/llvm-project/commit/bea110db3ed1fa1215bb8e22d2057019fcbd2d16
Author: Hampus Adolfsson <15944368+HampusAdolfsson at users.noreply.github.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang-tools-extra/clangd/XRefs.cpp
M clang-tools-extra/clangd/unittests/CallHierarchyTests.cpp
Log Message:
-----------
[clangd] Strip invalid fromRanges for outgoing calls (#134657)
`CallHierarchyOutgoingCall::fromRanges` are interpreted as ranges in the
same file as the item for which 'outgoingCalls' was called.
It's possible for outgoing calls to be in a different file than that
item if the item is just a declaration (e.g. in a header file). Now,
such calls are dropped instead of being returned to the client.
This is the same as the change made in #111616, but now for outgoing
calls.
Fixes clangd/clangd#2350
---------
Co-authored-by: Nathan Ridge <zeratul976 at hotmail.com>
Commit: 15bb1db4a98309f8769fa6d53a52eae62a61fbb2
https://github.com/llvm/llvm-project/commit/15bb1db4a98309f8769fa6d53a52eae62a61fbb2
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll
M llvm/test/Transforms/LoopVectorize/X86/pr51366-sunk-instruction-used-outside-of-loop.ll
M llvm/test/Transforms/LoopVectorize/X86/small-size.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll
Log Message:
-----------
[VPlan] Remove ILV::sinkScalarOperands. (#136023)
Remove legacy ILV sinkScalarOperands, which is superseded by the
sinkScalarOperands VPlan transforms.
There are a few cases that aren't handled by VPlan's sinkScalarOperands,
because the recipes doesn't support replicating. Those are pointer
inductions and blends.
We could probably improve this further, by allowing replication for more
recipes, but I don't think the extra complexity is warranted.
Depends on https://github.com/llvm/llvm-project/pull/136021.
PR: https://github.com/llvm/llvm-project/pull/136023
Commit: 0c61b24337236a0f67be54c26e12c98e9aecef5b
https://github.com/llvm/llvm-project/commit/0c61b24337236a0f67be54c26e12c98e9aecef5b
Author: Oleksandr "Alex" Zinenko <git at ozinenko.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M flang/lib/Optimizer/CodeGen/LowerRepackArrays.cpp
M flang/lib/Optimizer/HLFIR/Transforms/InlineElementals.cpp
M flang/lib/Optimizer/HLFIR/Transforms/InlineHLFIRAssign.cpp
M flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
M flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/AssumedRankOpConversion.cpp
M flang/lib/Optimizer/Transforms/ConstantArgumentGlobalisation.cpp
M flang/lib/Optimizer/Transforms/SimplifyFIROperations.cpp
M flang/lib/Optimizer/Transforms/StackArrays.cpp
M mlir/include/mlir/Transforms/GreedyPatternRewriteDriver.h
M mlir/include/mlir/Transforms/Passes.td
M mlir/lib/Dialect/Affine/TransformOps/AffineTransformOps.cpp
M mlir/lib/Dialect/Affine/Transforms/AffineDataCopyGeneration.cpp
M mlir/lib/Dialect/Affine/Transforms/SimplifyAffineStructures.cpp
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/lib/Dialect/Affine/Utils/Utils.cpp
M mlir/lib/Dialect/Arith/Transforms/IntRangeOptimizations.cpp
M mlir/lib/Dialect/Bufferization/Transforms/BufferDeallocationSimplification.cpp
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp
M mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp
M mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
M mlir/lib/Dialect/Transform/IR/TransformOps.cpp
M mlir/lib/Reducer/ReductionTreePass.cpp
M mlir/lib/Transforms/Canonicalizer.cpp
M mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
M mlir/test/lib/Dialect/Affine/TestAffineDataCopy.cpp
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
Log Message:
-----------
[mlir] add a fluent API to GreedyRewriterConfig (#137122)
This is similar to other configuration objects used across MLIR.
Rename some fields to better reflect that they are no longer booleans.
Reland 04d261101b4f229189463136a794e3e362a793af / #132253.
Commit: e268f71c5900f13207a7cd942f856f5852233d9e
https://github.com/llvm/llvm-project/commit/e268f71c5900f13207a7cd942f856f5852233d9e
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[VPlan] Remove unneeded early continue. (NFC)
As suggested in
https://github.com/llvm/llvm-project/pull/136455, now unreachable exit
blocks won't have any phi nodes.
Commit: a3d05e89873654dd1b27979b2bfd82ddd4859ba7
https://github.com/llvm/llvm-project/commit/a3d05e89873654dd1b27979b2bfd82ddd4859ba7
Author: anjenner <161845516+anjenner at users.noreply.github.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.AFLCustomIRMutator.opt.ll
Log Message:
-----------
Remove an incorrect assert in MFMASmallGemmSingleWaveOpt. (#130131)
This assert was failing in a fuzzing test. I consulted with @jrbyrnes
who said:
The MFMASmallGemmSingleWaveOpt::apply() method is invoked if and only if
the user has inserted an intrinsic llvm.amdgcn.iglp.opt(i32 1) into
their source code. This intrinsic applies a highly specialized DAG
mutation to result in specific scheduling for a specific set of kernels.
These assertions are really just confirming that the characteristics of
the kernel match what is expected (i.e. The kernels are similar to the
ones this DAG mutation strategy were designed against).
However, if we apply this DAG mutation to kernels for which is was not
designed, then we may not find the types of instructions we are looking
for, and may end up with empty caches.
I think it should be fine to just return false if the cache is empty
instead of the assert.
Commit: 03c2862404a9ab19940f87f8fb2dbe01818ab439
https://github.com/llvm/llvm-project/commit/03c2862404a9ab19940f87f8fb2dbe01818ab439
Author: Yuzhiy <44502685+Yuzhiy05 at users.noreply.github.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M libcxx/include/__ranges/to.h
M libcxx/test/libcxx/ranges/range.utility/range.utility.conv/to.static_assert.verify.cpp
Log Message:
-----------
[libc++][ranges] Reject non-class types in ranges::to (#135802)
This patch adds `static_assert` using `is_class_v` and `is_union_v` to
reject no-class type template parameters.
Fixes #132133
---------
Co-authored-by: A. Jiang <de34 at live.cn>
Commit: a2f00e1f8f124667339b94ffa144c0ff0d6ae3b3
https://github.com/llvm/llvm-project/commit/a2f00e1f8f124667339b94ffa144c0ff0d6ae3b3
Author: Luke Lau <luke at igalia.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
Log Message:
-----------
[RISCV] Add fixed-length patterns for disjoint or patterns for vwadd[u].v{v,x} (#136824)
This is the fixed-length equivalent of #136716.
The pattern we need to match is ({s,z}ext_vl (or_vl disjoint a, b)).
This only allows or_vls with an undef passthru, which allows us to
ignore its mask and vl and just take it from the {s,z}ext_vl.
A riscv_or_vl_is_add_oneuse PatFrag is added to mirror or_is_add in
RISCVInstrInfo.td.
Commit: 3883b27ba8a85c0228d5e49cb59d127d14dd0f8d
https://github.com/llvm/llvm-project/commit/3883b27ba8a85c0228d5e49cb59d127d14dd0f8d
Author: Luke Lau <luke at igalia.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
Log Message:
-----------
[VPlan] Fix typo in assertion. NFC (#137009)
Commit: be044976b6c27a5553d7e83d60f64c4a72c0de52
https://github.com/llvm/llvm-project/commit/be044976b6c27a5553d7e83d60f64c4a72c0de52
Author: SivanShani-Arm <sivan.shani at arm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsAArch64.def
M clang/lib/Headers/arm_acle.h
M clang/test/CodeGen/AArch64/gcs.c
Log Message:
-----------
[AArch64] Update __gcsss intrinsic to match revised ACLE specification (#136850)
The original __gcsss intrinsic was implemented based on:
https://github.com/ARM-software/acle/pull/260
with the signature: const void *__gcsss(const void *)
Per the updated specification in:
https://github.com/ARM-software/acle/pull/364
both const qualifiers have been removed. This commit updates the
signature accordingly to: void *__gcsss(void *)
This aligns the implementation with the latest ACLE definition.
Commit: 59b26abbbe89994c2ffd50a933654be247b68aaf
https://github.com/llvm/llvm-project/commit/59b26abbbe89994c2ffd50a933654be247b68aaf
Author: Camsyn <camsyn at foxmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
A compiler-rt/test/tsan/stack_race3.cpp
M llvm/lib/Transforms/Instrumentation/SanitizerBinaryMetadata.cpp
M llvm/lib/Transforms/Instrumentation/ThreadSanitizer.cpp
M llvm/test/Instrumentation/ThreadSanitizer/capture.ll
Log Message:
-----------
[TSan, SanitizerBinaryMetadata] Analyze the capture status for `alloca` rather than arbitrary `Addr` (#132756)
This PR is based on my last PR #132752 (the first commit of this PR),
but addressing a different issue.
This commit addresses the limitation in `PointerMayBeCaptured` analysis
when dealing with derived pointers (e.g. arr+1) as described in issue
#132739.
The current implementation of `PointerMayBeCaptured` may miss captures
of the underlying `alloca` when analyzing derived pointers, leading to
some FNs in TSan, as follows:
```cpp
void *Thread(void *a) {
((int*)a)[1] = 43;
return 0;
}
int main() {
int Arr[2] = {41, 42};
pthread_t t;
pthread_create(&t, 0, Thread, &Arr[0]);
// Missed instrumentation here due to the FN of PointerMayBeCaptured
Arr[1] = 43;
barrier_wait(&barrier);
pthread_join(t, 0);
}
```
Refer to this [godbolt page](https://godbolt.org/z/n67GrxdcE) to get the
compilation result of TSan.
Even when `PointerMayBeCaptured` working correctly, it should backtrack
to the original `alloca` firstly during analysis, causing redundancy to
the outer's `findAllocaForValue`.
```cpp
const AllocaInst *AI = findAllocaForValue(Addr);
// Instead of Addr, we should check whether its base pointer is captured.
if (AI && !PointerMayBeCaptured(Addr, true)) ...
```
Key changes:
Directly analyze the capture status of the underlying `alloca` instead
of derived pointers to ensure accurate capture detection
```cpp
const AllocaInst *AI = findAllocaForValue(Addr);
// Instead of Addr, we should check whether its base pointer is captured.
if (AI && !PointerMayBeCaptured(AI, true)) ...
```
Commit: 1ec22fae7e2c72b763b1c5ee6b743c59b5a4064c
https://github.com/llvm/llvm-project/commit/1ec22fae7e2c72b763b1c5ee6b743c59b5a4064c
Author: Jonas Paulsson <paulson1 at linux.ibm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZInstrFP.td
M llvm/test/CodeGen/SystemZ/fp-abs-01.ll
M llvm/test/CodeGen/SystemZ/fp-abs-02.ll
M llvm/test/CodeGen/SystemZ/fp-abs-03.ll
M llvm/test/CodeGen/SystemZ/fp-abs-04.ll
M llvm/test/CodeGen/SystemZ/fp-mul-08.ll
M llvm/test/CodeGen/SystemZ/fp-mul-10.ll
M llvm/test/CodeGen/SystemZ/fp-neg-01.ll
M llvm/test/CodeGen/SystemZ/fp-neg-02.ll
Log Message:
-----------
[SystemZ] Handle f16 load positive/negative/complement without libcalls. (#136286)
This can be done directly with the (64-bit) target instruction as only the sign bit
is changed.
Commit: 55066b83612b6bcc8c38ef6a84e5230ad116730f
https://github.com/llvm/llvm-project/commit/55066b83612b6bcc8c38ef6a84e5230ad116730f
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
A clang/test/AST/ByteCode/i686.cpp
Log Message:
-----------
[clang][bytecode] Compute pointer differences as 64bit integers (#137128)
And only convert to the target type after that.
Commit: 94a14f9f0d884eebb87fb3003229ffee5f95d1c8
https://github.com/llvm/llvm-project/commit/94a14f9f0d884eebb87fb3003229ffee5f95d1c8
Author: Jonas Paulsson <paulson1 at linux.ibm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.h
M llvm/lib/Target/SystemZ/SystemZInstrFP.td
M llvm/test/CodeGen/SystemZ/fp-copysign-01.ll
M llvm/test/CodeGen/SystemZ/fp-copysign-02.ll
M llvm/test/CodeGen/SystemZ/fp-copysign-03.ll
Log Message:
-----------
[SystemZ] Add DAGCombine for FCOPYSIGN to remove rounding. (#136131)
Add a DAGCombine for FCOPYSIGN that removes the rounding which is never
needed as the sign bit is already in the correct place. This helps in particular the
rounding to f16 case which needs a libcall.
Also remove the roundings for other FP VTs and simplify the CPSDR
patterns correspondingly.
fp-copysign-03.ll test updated, now also covering the other FP VT
combinations.
Commit: e98a61dc326c1b564461c0ae4fc693be5113d540
https://github.com/llvm/llvm-project/commit/e98a61dc326c1b564461c0ae4fc693be5113d540
Author: Tai Ly <tai.ly at arm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/verifier.mlir
Log Message:
-----------
[mlir][tosa] Add verifier check for Concat Op (#136047)
This adds verifier check for Concat Op
to make sure the sum of concatenated axis dimensions is equal to the
output's axis dimension
add tests in verifier.mlir
also moved existing concat verifier checks to verifier.mlir
Signed-off-by: Tai Ly <tai.ly at arm.com>
Commit: 66461dbb3b8d107fae2d50049205ddb8c192049c
https://github.com/llvm/llvm-project/commit/66461dbb3b8d107fae2d50049205ddb8c192049c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
Log Message:
-----------
SPIRV: Set NoPHIs property after rewriting them (#136327)
There should be no PHIs after selection, as OpPhi is used
instead. This hopefully avoids errors in #135277.
Commit: c6c08462ee3e8fc3d9cf9a69bb51175be49d5d3c
https://github.com/llvm/llvm-project/commit/c6c08462ee3e8fc3d9cf9a69bb51175be49d5d3c
Author: Jannick Kremer <jannick.kremer at mailbox.org>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/bindings/python/clang/cindex.py
A clang/bindings/python/tests/cindex/INPUTS/a.inc
A clang/bindings/python/tests/cindex/INPUTS/b.inc
A clang/bindings/python/tests/cindex/INPUTS/testfile.c
M clang/bindings/python/tests/cindex/test_file.py
M clang/docs/ReleaseNotes.rst
Log Message:
-----------
[libclang/python] Add equality comparison operators for File (#130383)
This covers the `File` interface changes added by #120590
---------
Co-authored-by: Mathias Stearn <redbeard0531 at gmail.com>
Co-authored-by: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Commit: 82c25d27501996683f30eb92dabf8a11925b7a62
https://github.com/llvm/llvm-project/commit/82c25d27501996683f30eb92dabf8a11925b7a62
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/test/AST/ByteCode/i686.cpp
Log Message:
-----------
[clang][bytecode] Disable i686 test
The array is too big and we don't have array fillers yet, see
e.g. https://lab.llvm.org/buildbot/#/builders/154/builds/15255
Commit: 88083a0c42e69e5967737e088ac6e5b1d12343f0
https://github.com/llvm/llvm-project/commit/88083a0c42e69e5967737e088ac6e5b1d12343f0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
Log Message:
-----------
[X86] SimplifyDemandedVectorEltsForTargetNode - handle 512-bit X86ISD::VPERMI with lower half demanded elts (#137139)
512-bit X86ISD::VPERMI nodes handle the lower/upper 256-bits separately - so if we don't demand the upper half elements, we can just use the 256-bit variant.
Commit: ebceb732d5afa7b97b73b34ce078a58c654ff0a0
https://github.com/llvm/llvm-project/commit/ebceb732d5afa7b97b73b34ce078a58c654ff0a0
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/Vector/canonicalize.mlir
Log Message:
-----------
[mlir][vector] Update the folder for vector.{insert|extract} (#136579)
This is a minor follow-up to #135498. It ensures that operations like
the following are not treated as out-of-bounds accesses and can be
folded correctly (*):
```mlir
%c_neg_1 = arith.constant -1 : index
%0 = vector.insert %value_to_store, %dest[%c_neg_1] : vector<5xf32> into vector<4x5xf32>
%1 = vector.extract %src[%c_neg_1, 0] : f32 from vector<4x5xf32>
```
In addition to adding tests for the case above, this PR also relocates
the tests from #135498 to be alongside existing tests for the
`vector.{insert|extract}` folder, and reformats them to follow:
* https://mlir.llvm.org/getting_started/TestingGuide/
For example:
* The "no_fold" prefix is now used to label negative tests.
* Redundant check lines have been removed (e.g., CHECK: vector.insert
is sufficient to verify that folding did not occur).
(*) As per https://mlir.llvm.org/docs/Dialects/Vector/#vectorinsert-vectorinsertop,
these are poison values.
Commit: 427b6448a3af009e57c0142d6d8af83318b45093
https://github.com/llvm/llvm-project/commit/427b6448a3af009e57c0142d6d8af83318b45093
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrGISel.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/lower-neon-vector-fcmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vector-fcmp.mir
M llvm/test/CodeGen/AArch64/arm64-zip.ll
M llvm/test/CodeGen/AArch64/select_cc.ll
Log Message:
-----------
Revert "[LLVM][ISel][AArch64 Remove AArch64ISD::FCM##z nodes. (#135817)"
This reverts commit 15d8b3cae9debc2bd7d27ca92ff599ba9fb30da5.
Commit: e37c236597137bae4f6728e163e9f81a1d9aff18
https://github.com/llvm/llvm-project/commit/e37c236597137bae4f6728e163e9f81a1d9aff18
Author: Christian Sigg <csigg at google.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] Remove unnecessary dependencies. (#136999)
Commit: d664c42baaed7f47a80f73a3974afd6e2593e41a
https://github.com/llvm/llvm-project/commit/d664c42baaed7f47a80f73a3974afd6e2593e41a
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M libclc/generic/include/clc/clc.h
R libclc/generic/include/clc/clcmacros.h
Log Message:
-----------
[libclc] Remove unnecessary clcmacros.h (#137149)
The macros defined by this file (not to be confused with clcmacro.h)
don't appear necessary for building libclc.
The language version macros should be handled by clang, and there are no
uses of NULL or kernel_exec in the source code.
Commit: 6900e9026516963ae625b28dded2cdf0bd16e590
https://github.com/llvm/llvm-project/commit/6900e9026516963ae625b28dded2cdf0bd16e590
Author: jeremyd2019 <github at jdrake.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/TargetParser/Triple.cpp
M llvm/unittests/TargetParser/TripleTest.cpp
Log Message:
-----------
[LLVM][TargetParser] Handle -msys targets the same as -cygwin. (#136817)
MSYS2 uses i686-pc-msys and x86_64-pc-msys as target, and is a fork of
Cygwin. There's an effort underway to try to switch as much as possible
to use -pc-cygwin targets, but the -msys target will be hanging around
for the forseeable future.
Commit: 15321d2c9e686b382262339fa17c5445b1b2609f
https://github.com/llvm/llvm-project/commit/15321d2c9e686b382262339fa17c5445b1b2609f
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaObjC.cpp
M clang/lib/Sema/SemaObjCProperty.cpp
M clang/lib/Sema/SemaOverload.cpp
A clang/test/Sema/implicit-void-ptr-cast.c
Log Message:
-----------
[C] Add (new) -Wimplicit-void-ptr-cast to -Wc++-compat (#136855)
This introduces a new diagnostic group (-Wimplicit-void-ptr-cast),
grouped under -Wc++-compat, which diagnoses implicit conversions from
void * to another pointer type in C. It's a common source of
incompatibility with C++ and is something GCC diagnoses (though GCC does
not have a specific warning group for this).
Fixes #17792
Commit: 2edade28245b1fc2b7cb0b39804894f8fdcfb7ff
https://github.com/llvm/llvm-project/commit/2edade28245b1fc2b7cb0b39804894f8fdcfb7ff
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M libclc/generic/include/clc/shared/vload.h
M libclc/generic/include/clc/shared/vstore.h
M libclc/generic/lib/shared/vload.cl
M libclc/generic/lib/shared/vload_half.inc
M libclc/generic/lib/shared/vstore.cl
M libclc/generic/lib/shared/vstore_half.inc
Log Message:
-----------
[libclc][NFC] Clang-format vload/vstore code
Commit: acc335bfa7b00ab19bf9832870aaf207f587b48b
https://github.com/llvm/llvm-project/commit/acc335bfa7b00ab19bf9832870aaf207f587b48b
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/test/CodeGen/X86/build-vector-128.ll
M llvm/test/CodeGen/X86/build-vector-256.ll
M llvm/test/CodeGen/X86/build-vector-512.ll
Log Message:
-----------
[X86] Add build vector test patterns with only 2 unique scalars
Based off test coverage for #135753 - these should be lowered to BLEND(BROADCAST(X),BROADCAST(Y))
Commit: 5d136f90a9806daf6d9ac905734a27974fc8f1b7
https://github.com/llvm/llvm-project/commit/5d136f90a9806daf6d9ac905734a27974fc8f1b7
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Manage instruction metadata in VPlan. (#135272)
Add a new helper to manage IR metadata that can be progated to generated
instructions for recipes.
This helps to remove a number of remaining uses of getUnderlyingInstr
during VPlan execution.
PR: https://github.com/llvm/llvm-project/pull/135272
Commit: f218cd28d4b762846a84a24817396465b824710d
https://github.com/llvm/llvm-project/commit/f218cd28d4b762846a84a24817396465b824710d
Author: Luke Lau <luke at igalia.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
Log Message:
-----------
[IA] Remove unused argument. NFC
Commit: dde00f5e22e81ac88b37d1502d2383985a58329d
https://github.com/llvm/llvm-project/commit/dde00f5e22e81ac88b37d1502d2383985a58329d
Author: Tejas Vipin <alissxlace at proton.me>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
R libc/test/src/math/performance_testing/BinaryOpSingleOutputPerf.h
M libc/test/src/math/performance_testing/CMakeLists.txt
A libc/test/src/math/performance_testing/PerfTest.h
R libc/test/src/math/performance_testing/SingleInputSingleOutputPerf.h
M libc/test/src/math/performance_testing/ceilf_perf.cpp
M libc/test/src/math/performance_testing/cosf_perf.cpp
M libc/test/src/math/performance_testing/exp10f16_perf.cpp
M libc/test/src/math/performance_testing/exp2f16_perf.cpp
M libc/test/src/math/performance_testing/exp2f_perf.cpp
M libc/test/src/math/performance_testing/expf16_perf.cpp
M libc/test/src/math/performance_testing/expf_perf.cpp
M libc/test/src/math/performance_testing/expm1f_perf.cpp
M libc/test/src/math/performance_testing/fabsf_perf.cpp
M libc/test/src/math/performance_testing/floorf_perf.cpp
M libc/test/src/math/performance_testing/fmod_perf.cpp
M libc/test/src/math/performance_testing/fmodf128_perf.cpp
M libc/test/src/math/performance_testing/fmodf16_perf.cpp
M libc/test/src/math/performance_testing/fmodf_perf.cpp
M libc/test/src/math/performance_testing/fmodl_perf.cpp
M libc/test/src/math/performance_testing/fmul_perf.cpp
M libc/test/src/math/performance_testing/fmull_perf.cpp
M libc/test/src/math/performance_testing/hypot_perf.cpp
M libc/test/src/math/performance_testing/hypotf16_perf.cpp
M libc/test/src/math/performance_testing/hypotf_perf.cpp
M libc/test/src/math/performance_testing/log10f_perf.cpp
M libc/test/src/math/performance_testing/log1pf_perf.cpp
M libc/test/src/math/performance_testing/log2f_perf.cpp
M libc/test/src/math/performance_testing/logbf_perf.cpp
M libc/test/src/math/performance_testing/logf_perf.cpp
M libc/test/src/math/performance_testing/max_min_funcs_perf.cpp
M libc/test/src/math/performance_testing/misc_basic_ops_perf.cpp
M libc/test/src/math/performance_testing/nearbyintf_perf.cpp
M libc/test/src/math/performance_testing/nearest_integer_funcs_perf.cpp
M libc/test/src/math/performance_testing/rintf_perf.cpp
M libc/test/src/math/performance_testing/roundf_perf.cpp
M libc/test/src/math/performance_testing/sinf_perf.cpp
M libc/test/src/math/performance_testing/sqrtf128_perf.cpp
M libc/test/src/math/performance_testing/sqrtf_perf.cpp
M libc/test/src/math/performance_testing/truncf_perf.cpp
Log Message:
-----------
[libc][math] Improve performance test framework (#134501)
- Merges `BinaryOpSingleOutputPerf.h` and
`SingleInputSingleOutputPerf.h` files into a unified `PerfTest.h` and
update all performance tests to use this.
- Improve the output printed to log file for tests.
- Removes unused `run_diff` method and redundant `run_perf` call in
`BINARY_INPUT_SINGLE_OUTPUT_PERF_EX` (previously
`BINARY_OP_SINGLE_OUTPUT_PERF_EX`)
- Change `BINARY_INPUT_SINGLE_OUTPUT_PERF_EX` and
`SINGLE_INPUT_SINGLE_OUTPUT_PERF` to not define `main`
Commit: 06d48769825c656bff97c05d398ce3ec77acfb36
https://github.com/llvm/llvm-project/commit/06d48769825c656bff97c05d398ce3ec77acfb36
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Replace checking IR loop with checking VPlan predecessors (NFC).
Update check to use VPEarlyExitBlock's predecessors, which removes a
dependence on underlying IR and is more in line with the comment below.
Commit: 79144643b6b82f05fd0cee8916a2162b14bfd9fd
https://github.com/llvm/llvm-project/commit/79144643b6b82f05fd0cee8916a2162b14bfd9fd
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/test/Transforms/PhaseOrdering/X86/blendv-select.ll
Log Message:
-----------
[PhaseOrdering][X86] blendv-select.ll - add test coverage for #66513
Commit: e35cc2d387e170d0e1f6ef647f17423262feb1ea
https://github.com/llvm/llvm-project/commit/e35cc2d387e170d0e1f6ef647f17423262feb1ea
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
Log Message:
-----------
[lldb][TypeSystemClang][NFC] Clean up TypeSystemClang::DeclGetMangledName to LLVM-style
Will make upcoming changes in this area easier to read.
Commit: bcdafc107e1fb68893036cfba14e761c7b37b0e9
https://github.com/llvm/llvm-project/commit/bcdafc107e1fb68893036cfba14e761c7b37b0e9
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M lldb/test/API/commands/process/reverse-continue/TestReverseContinueNotSupported.py
Log Message:
-----------
[lldb] Disable reverse continue command test on Windows
The new test added in https://github.com/llvm/llvm-project/pull/132783
is timing out on our Windows on Arm bot
https://lab.llvm.org/buildbot/#/builders/141/builds/8149
Disable it there while I figure out the problem.
Commit: 8b2d269db22d253ef07a48ef433bc94dc70f2c75
https://github.com/llvm/llvm-project/commit/8b2d269db22d253ef07a48ef433bc94dc70f2c75
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
A llvm/test/CodeGen/X86/buildvec-widen-dotproduct.ll
Log Message:
-----------
[X86] Add extended test coverage for #135010
Commit: d7f3c3129344b133859d89d962fcdd5058702f72
https://github.com/llvm/llvm-project/commit/d7f3c3129344b133859d89d962fcdd5058702f72
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrGISel.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/lower-neon-vector-fcmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-const-vector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vector-fcmp.mir
M llvm/test/CodeGen/AArch64/arm64-zip.ll
M llvm/test/CodeGen/AArch64/select_cc.ll
Log Message:
-----------
Reapply "[LLVM][ISel][AArch64 Remove AArch64ISD::FCM##z nodes. (#135817)"
This reverts commit 427b6448a3af009e57c0142d6d8af83318b45093.
Original patch has been updated to include a fix to esnure
AArch64InstructionSelector::emitConstantVector supports all the cases
where isBuildVectorAllOnes returns true.
Commit: ecdd3fd71f41f600623e93bad08f9e41b1d0d8cc
https://github.com/llvm/llvm-project/commit/ecdd3fd71f41f600623e93bad08f9e41b1d0d8cc
Author: Karthika Devi C <quic_kartc at quicinc.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M polly/lib/CodeGen/BlockGenerators.cpp
M polly/lib/CodeGen/CodeGeneration.cpp
M polly/lib/CodeGen/IslExprBuilder.cpp
M polly/lib/CodeGen/IslNodeBuilder.cpp
M polly/lib/CodeGen/LoopGenerators.cpp
M polly/lib/CodeGen/LoopGeneratorsGOMP.cpp
M polly/lib/CodeGen/LoopGeneratorsKMP.cpp
M polly/lib/CodeGen/PerfMonitor.cpp
Log Message:
-----------
[RemoveDI][Polly] Use iterators instead of instruction pointers to SetInsertPoint (#135336)
As part of the effort to transition to using Debug Records instead of
Debug intrinsics, some API/argument changes are necessary to achieve the
desired behavior from Debug Records. This particular fix involves
passing iterators instead of instruction pointers to the SetInsertPoint
function. While this is crucial in certain areas, it may be more than
needed in others, but it does not cause any harm.
Commit: 224cd50e005a9215e8c528d5ce68d4fcdfcdb98f
https://github.com/llvm/llvm-project/commit/224cd50e005a9215e8c528d5ce68d4fcdfcdb98f
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
A llvm/test/Transforms/GlobalOpt/X86/preserve-dbgloc-of-load-store-to-bool.ll
Log Message:
-----------
[DebugInfo][GlobalOpt] Preserve source locs for optimized loads (#134828)
Some optimizations in globalopt simplify uses of a global value to uses
of a generated global bool value; in some cases where this happens, the
newly-generated instructions would not have the original source
location(s) of the instructions they replaced propagated to them; this
patch properly preserves those source locations.
Found using https://github.com/llvm/llvm-project/pull/107279.
Commit: 57530c23a53b5e003d389437637f61c5b9814e22
https://github.com/llvm/llvm-project/commit/57530c23a53b5e003d389437637f61c5b9814e22
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
A llvm/test/Transforms/GlobalOpt/malloc-promote-atomic.ll
Log Message:
-----------
[GlobalOpt] Do not promote malloc if there are atomic loads/stores (#137158)
When converting a malloc stored to a global into a global, we will
introduce an i1 flag to track whether the global has been initialized.
In case of atomic loads/stores, this will result in verifier failures,
because atomic ops on i1 are illegal. Even if we changed this to i8, I
don't think it is a good idea to change atomic types in that way.
Instead, bail out of the transform is we encounter any atomic
loads/stores of the global.
Fixes https://github.com/llvm/llvm-project/issues/137152.
Commit: f572a5951a664d57e909928d5595285212ad6884
https://github.com/llvm/llvm-project/commit/f572a5951a664d57e909928d5595285212ad6884
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
A llvm/test/Transforms/VectorCombine/pr132563.ll
Log Message:
-----------
[VectorCombine] Ensure canScalarizeAccess handles cases where the index type can't represent all inbounds values
Fixes #132563
Commit: 2dfe68a306b33048346d30ca141605be991e5302
https://github.com/llvm/llvm-project/commit/2dfe68a306b33048346d30ca141605be991e5302
Author: Josep Pinot <josep.pinot at bsc.es>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M openmp/runtime/src/kmp_tasking.cpp
Log Message:
-----------
[NFC][OpenMP] Fix task record/replay comments (#137178)
Commit: 10ea5eedb1d13760e4caf0bd983ce7778cff0426
https://github.com/llvm/llvm-project/commit/10ea5eedb1d13760e4caf0bd983ce7778cff0426
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/test/CodeGen/X86/pr40891.ll
Log Message:
-----------
[X86] pr40891.ll - add X64 test coverage
Commit: 139e30e2158dcb83db82e59df6ec48894eac0129
https://github.com/llvm/llvm-project/commit/139e30e2158dcb83db82e59df6ec48894eac0129
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
R libclc/amdgpu/lib/SOURCES_3.9
R libclc/amdgpu/lib/SOURCES_4.0
R libclc/amdgpu/lib/SOURCES_5.0
R libclc/amdgpu/lib/shared/vload_half_helpers.ll
R libclc/amdgpu/lib/shared/vstore_half_helpers.ll
M libclc/generic/lib/shared/vload.cl
M libclc/generic/lib/shared/vstore.cl
M libclc/generic/lib/shared/vstore_half.inc
R libclc/ptx/lib/SOURCES_3.9
R libclc/ptx/lib/SOURCES_4.0
R libclc/ptx/lib/SOURCES_5.0
R libclc/ptx/lib/shared/vload_half_helpers.ll
R libclc/ptx/lib/shared/vstore_half_helpers.ll
Log Message:
-----------
[libclc] Remove (vload|vstore)_half helpers (#137181)
These were only being used when compiling with versions of clang older
than clang 6. As such they were essentially unsupported and untested.
This somewhat simplifies the codebase, producing fewer helper functions
in the final builtins library. It also avoids typed pointer IR.
There's no change to any of the targets' bytecode other than removing
these helper functions.
Commit: e3eee9e81ec2a42d1f78d8a4e52f4b4ee8927436
https://github.com/llvm/llvm-project/commit/e3eee9e81ec2a42d1f78d8a4e52f4b4ee8927436
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/test/CodeGen/X86/vector-trunc.ll
Log Message:
-----------
[X86] vector-trunc.ll - replace stores to ptr undef with real ptr values
Prevents some unnecessary codegen changes in an upcoming patch
Commit: ed866d994c3b074cb1b7a380b1ce9169dde3362c
https://github.com/llvm/llvm-project/commit/ed866d994c3b074cb1b7a380b1ce9169dde3362c
Author: Evgenii Kudriashov <evgenii.kudriashov at intel.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/extractelement-load.ll
Log Message:
-----------
[X86][Combine] Ensure single use chain in extract-load combine (#136520)
The problem is that `SrcBC = peekThroughBitcasts(Src)` doesn't ensure
single use chain. It results in the situation when a cast may have
multiple users and instead of replacing a load we introduce a new one.
The situation is worsened by the fact that we've replaced the token from
the original load and its correct memory order now is not guaranteed.
Commit: 52a96491e1e4e0d033e39fad87f49ccd871df41d
https://github.com/llvm/llvm-project/commit/52a96491e1e4e0d033e39fad87f49ccd871df41d
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/lib/Basic/Targets/SPIR.h
A clang/test/CodeGenCUDASPIRV/printf.cu
Log Message:
-----------
[clang][SPIR-V] Addrspace of opencl_global should always be 1 (#136753)
This fixes a CUDA SPIR-V regression introduced in
https://github.com/llvm/llvm-project/pull/134399.
---------
Signed-off-by: Sarnie, Nick <nick.sarnie at intel.com>
Commit: 3e605b1e1d85f6767bbc2a91d3916688118040cd
https://github.com/llvm/llvm-project/commit/3e605b1e1d85f6767bbc2a91d3916688118040cd
Author: zhijian lin <zhijian at ca.ibm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
A llvm/test/CodeGen/PowerPC/vsx-fma-m-early.ll
Log Message:
-----------
[NFC] Add a pre-commit test case for #111696 (#136730)
Add a pre- commit test case for Patch
https://github.com/llvm/llvm-project/pull/111696
Test ppc-vsx-fma-mutate pass work with
-schedule-ppc-vsx-fma-mutation-early not hoist the instruction
`xxspltiw vs2, 1170469888` out the loop.
---------
Co-authored-by: Amy Kwan <amy.kwan1 at ibm.com>
Commit: d859cb68836191cfa469d0c951134b53ee31298e
https://github.com/llvm/llvm-project/commit/d859cb68836191cfa469d0c951134b53ee31298e
Author: erichkeane <ekeane at nvidia.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/lib/Sema/SemaOpenACCClause.cpp
Log Message:
-----------
[OpenACC] Fix variable dereference found by static analysis
Reported here: https://github.com/llvm/llvm-project/issues/137116
Fixes: 137116
Commit: 9ae7aa79b1e151c3af12b9ffec0e2fdeacde5cc9
https://github.com/llvm/llvm-project/commit/9ae7aa79b1e151c3af12b9ffec0e2fdeacde5cc9
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/test/AST/ByteCode/records.cpp
Log Message:
-----------
[clang][bytecode] Diagnose comparing pointers to fields... (#137159)
... with different access specifiers.
Commit: 0fcc9ffafd35e4567e6bc90f46b8c75f501dddf9
https://github.com/llvm/llvm-project/commit/0fcc9ffafd35e4567e6bc90f46b8c75f501dddf9
Author: Kajetan Puchalski <kajetan.puchalski at arm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M flang/CMakeLists.txt
M llvm/CMakeLists.txt
Log Message:
-----------
[CMake] Support using precompiled headers with ccache in flang (#136856)
In order for precompiled headers to work with ccache, a specific flag
needs to be passed to the compiler and ccache's sloppiness configuration
option needs to be set appropriately.
Due to issues with configuring CMake on certain Windows platforms, set
the required ccache option only on non-Windows systems for the time
being.
-----
Signed-off-by: Kajetan Puchalski <kajetan.puchalski at arm.com>
Commit: d43ce3504891edde937d68f6158dfacfa76de77a
https://github.com/llvm/llvm-project/commit/d43ce3504891edde937d68f6158dfacfa76de77a
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/utils/TableGen/GlobalISelEmitter.cpp
Log Message:
-----------
[TableGen][GISel] Allow isTrivialOperatorNode to import patterns with isStore and a memory VT. (#137080)
This removes the need to explicitly set isTruncStore on truncstorei8 and
other similar PatFrags that include truncstore in their frags DAG.
This allows some new patterns to be imported for AMDGPU as you can see
in the changed test.
The extra isTruncStore were added in ae2b36e8bdfa6, along with some
other tablegen changes to look for MemoryVT along with isTruncStore. I
did not remove the code, because I'm not sure if any out of tree users
have become dependent on it. It's no longer exercised in tree.
Commit: 4f5cfa81dcbd51d5416022d1872b04a9f376331b
https://github.com/llvm/llvm-project/commit/4f5cfa81dcbd51d5416022d1872b04a9f376331b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast.gfx6.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/cc-update.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs-r600.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernel-argument-alignment.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/lower-kernargs.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
Log Message:
-----------
AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)
These were added to the migration from v4 to v5 and should be removed
now
that the default has changed.
Commit: 72cc868c65b0641f23d1fb0518a8503c73ecdb5a
https://github.com/llvm/llvm-project/commit/72cc868c65b0641f23d1fb0518a8503c73ecdb5a
Author: Shafik Yaghmour <shafik.yaghmour at intel.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/lib/Serialization/ASTReader.cpp
Log Message:
-----------
[Clang][NFC] Move temp variable back into the source (#137095)
Static analysis flagged this code b/c we are copying the temp variable
back in when we could move it instead.
Commit: b278aa31979f22409ee73d413a739394366fe2ff
https://github.com/llvm/llvm-project/commit/b278aa31979f22409ee73d413a739394366fe2ff
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
Log Message:
-----------
[RISCV] Make xrivosvizip interleave2 and deinterleave2 undef safe (#136733)
We're duplicating uses here, so we need to freeze the inputs.
---------
Co-authored-by: Luke Lau <luke_lau at icloud.com>
Commit: a903c7b7f5d1cb8d72c170d494d94dc251fc7204
https://github.com/llvm/llvm-project/commit/a903c7b7f5d1cb8d72c170d494d94dc251fc7204
Author: RolandF77 <55763885+RolandF77 at users.noreply.github.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsPowerPC.td
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
M llvm/test/CodeGen/PowerPC/dmr-enable.ll
Log Message:
-----------
[PowerPC] Intrinsics and tests for dmr insert/extract (#135653)
Add some intrinsics and LIT tests for PPC dmr insert/extract
instructions.
Commit: 2ca071b1decf006a31385c75478b57013964e49a
https://github.com/llvm/llvm-project/commit/2ca071b1decf006a31385c75478b57013964e49a
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/Target/AArch64/AArch64InstrAtomics.td
M llvm/lib/Target/BPF/BPFInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/GlobalISelEmitter.cpp
Log Message:
-----------
[TableGen][RISCV][AArch64][GISel] Properly implement isAnyExtLoad/isSignExtLoad/isZeroExtLoad for IsAtomic in SelectionDAG. (#137096)
Support isAnyExtLoad() for IsAtomic in GISel.
Modify atomic_load_az* to check for extload or zextload. And rename to
atomic_load_azext*
Add atomic_load_asext* and use in RISC-V. I used "asext" rather than
"as" so it wouldn't be confused with the word "as".
Commit: feaa5aa840dcda69bd4133536142be882f696114
https://github.com/llvm/llvm-project/commit/feaa5aa840dcda69bd4133536142be882f696114
Author: Akira Hatanaka <ahatanak at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/lib/AST/ExprConstant.cpp
M clang/test/SemaCXX/constexpr-vectors-access-elements.cpp
Log Message:
-----------
Fix a crash in constant evaluation of ExtVectorElementExprs (#136771)
Handle the case where the base expression is a pointer to a vector type.
rdar://149223362
Commit: c7fbabaf87f9411fbcc48a33efaa76f0f03135e9
https://github.com/llvm/llvm-project/commit/c7fbabaf87f9411fbcc48a33efaa76f0f03135e9
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/test/CodeGenCXX/mangle-template.cpp
Log Message:
-----------
[clang] fix typo in CHECK line
Commit: 0ab330b344dc6333907542bb6267a9bd13e94b07
https://github.com/llvm/llvm-project/commit/0ab330b344dc6333907542bb6267a9bd13e94b07
Author: Eric Astor <epastor at google.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/MC/MCParser/MasmParser.cpp
M llvm/test/tools/llvm-ml/macro_function.asm
Log Message:
-----------
[ms] [llvm-ml] Add support for `@CatStr` built-in function symbol (#130781)
MASM supports some built-in macro-type functions.
We start our support for these with `@CatStr`, one of the more commonly used.
Commit: 72b2d4d758501ab9bf203e82be5b612f48c863b4
https://github.com/llvm/llvm-project/commit/72b2d4d758501ab9bf203e82be5b612f48c863b4
Author: stma247 <184293860+stma247 at users.noreply.github.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
A llvm/test/tools/llvm-cov/branch-export-lcov-unify-instances.test
M llvm/test/tools/llvm-cov/branch-export-lcov.test
M llvm/tools/llvm-cov/CodeCoverage.cpp
M llvm/tools/llvm-cov/CoverageExporterLcov.cpp
M llvm/tools/llvm-cov/CoverageViewOptions.h
Log Message:
-----------
[llvm-cov] Fix branch counts of template functions (second attempt) (#135074)
This PR is a second attempt for issue #111743 to finish reverted PR
#113925.
Added option "--unify-instantiations" to llvm-cov export to combine branch execution counts of C++ template instantiations. Fix non-deterministic behavior.
Commit: fe90b9dac76dd3efcb24f747007c68ee2bc27630
https://github.com/llvm/llvm-project/commit/fe90b9dac76dd3efcb24f747007c68ee2bc27630
Author: Camsyn <camsyn at foxmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M compiler-rt/lib/asan/asan_report.cpp
Log Message:
-----------
[ASan] Limits the conditions of the deadlock patch (#137127)
PR #131756 introduced a patch to fix a deadlock between LSan and ASan.
The relevant deadlock only occurs when LSan is enabled and
`dl_iterate_phdr` is used for Stop-the-World, i.e., under the condition
`CAN_SANITIZE_LEAKS && (SANITIZER_LINUX || SANITIZER_NETBSD)`.
Therefore, this commit also sets the effective condition of this patch
to the above condition, avoiding unnecessary problems in other
environments, e.g., stack overflow on MSVC/Windows.
Commit: e329b6c530f30bc645ea188cd25068c6759eb16a
https://github.com/llvm/llvm-project/commit/e329b6c530f30bc645ea188cd25068c6759eb16a
Author: Finn Plummer <canadienfinn at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/include/clang/Parse/ParseHLSLRootSignature.h
M clang/lib/Parse/ParseHLSLRootSignature.cpp
Log Message:
-----------
[NFC][RootSignatures] Conform to new std::optional calling conventions (#136747)
- It was determined to define the parsing methods much more inline with
a recursive descent parser to follow the EBNF notation better
- As part of this change, we decided to go with a calling convention to
the parse.* methods of returning an optional rather than a bool and a
reference to the parsed struct
This is a clean-up task from
https://github.com/llvm/llvm-project/pull/133800
Commit: 565a075909046f74c2fbb7713419518464599a4e
https://github.com/llvm/llvm-project/commit/565a075909046f74c2fbb7713419518464599a4e
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M flang-rt/lib/cuda/allocator.cpp
M flang-rt/unittests/Runtime/CUDA/Allocatable.cpp
Log Message:
-----------
[flang][cuda][rt] Track asynchronous allocation stream for deallocation (#137073)
When an asynchronous allocation is made, we call `cudaMallocAsync` with
a stream. For deallocation, we need to call `cudaFreeAsync` with the
same stream. in order to achieve that, we need to track the allocation
and their respective stream.
This patch adds a simple sorted array of asynchronous allocations. A
binary search is performed to retrieve the allocation when deallocation
is needed.
Commit: e78b763568e47e685926614195c3075afa35668c
https://github.com/llvm/llvm-project/commit/e78b763568e47e685926614195c3075afa35668c
Author: Scott Linder <scott.linder at amd.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/difile_absolute_filenames.ll
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/difile_absolute_filenames.ll.expected
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.globals.expected
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.transitiveglobals.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/difile_absolute_filenames.test
M llvm/utils/UpdateTestChecks/common.py
Log Message:
-----------
update_test_checks: Relax DIFile filename checks (#135692)
Avoid baking in absolute paths in check lines generated for DIFile
metadata. Generated test checks cannot be sensitive to absolute paths
anyway, as those vary with the environment, but there could be
situations where some sensitivity to partial paths is required for
certain tests. This implementation just assumes such tests aren't worth
the effort to support, but it could be supported in the future.
This is most useful for update_cc_test_checks with debug info enabled,
where the test writer cannot manipulate the paths within the generated
IR directly.
Commit: 2de936b6eb38e7a37224a97c2a22aa79b9dfb9dc
https://github.com/llvm/llvm-project/commit/2de936b6eb38e7a37224a97c2a22aa79b9dfb9dc
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
M mlir/test/Dialect/Vector/vector-emulate-narrow-type-unaligned.mlir
M mlir/test/Dialect/Vector/vector-emulate-narrow-type.mlir
Log Message:
-----------
[mlir][vector] Fix emulation of "narrow" type `vector.store` (#133231)
Below are two examples of "narrow" `vector.stores`. The first example
does not require partial stores and hence no RMW stores. This is
currently emulated correctly.
```mlir
func.func @example_1(%arg0: vector<4xi2>) {
%0 = memref.alloc() : memref<13xi2>
%c4 = arith.constant 4 : index
vector.store %arg0, %0[%c4] : memref<13xi2>, vector<4xi2>
return
}
```
The second example requires a partial (and hence RMW) store due to the
offset pointing outside the emulated type boundary (`%c3`).
```mlir
func.func @example_2(%arg0: vector<4xi2>) {
%0 = memref.alloc() : memref<13xi2>
%c3 = arith.constant 3 : index
vector.store %arg0, %0[%c3] : memref<13xi2>, vector<4xi2>
return
}
```
This is currently incorrectly emulated as a single "full" store (note
that the offset is incorrect) instead of partial stores:
```mlir
func.func @example_2(%arg0: vector<4xi2>) {
%alloc = memref.alloc() : memref<4xi8>
%0 = vector.bitcast %arg0 : vector<4xi2> to vector<1xi8>
%c0 = arith.constant 0 : index
vector.store %0, %alloc[%c0] : memref<4xi8>, vector<1xi8>
return
}
```
The incorrect emulation stems from this simplified (i.e. incomplete)
calculation of the front padding:
```cpp
std::optional<int64_t> foldedNumFrontPadElems =
isDivisibleInSize ? 0
: getConstantIntValue(linearizedInfo.intraDataOffset);
```
Since `isDivisibleInSize` is `true` (i8 / i2 = 4):
* front padding is set to `0` and, as a result,
* the input offset (`%c3`) is ignored, and
* we incorrectly assume that partial stores won't be needed.
Note that in both examples we are storing `vector<4xi2>` into
`memref<13xi2>` (note _different_ trailing dims) and hence partial
stores might in fact be required. The condition above is updated to:
```cpp
std::optional<int64_t> foldedNumFrontPadElems =
(isDivisibleInSize && trailingDimsMatch)
? 0
: getConstantIntValue(linearizedInfo.intraDataOffset);
```
This change ensures that the input offset is properly taken into
account, which fixes the issue. It doesn't affect `@example1`.
Additional comments are added to clarify the current logic.
Commit: 7a276c8acfc3977de8c3ceb0af67fcf603834946
https://github.com/llvm/llvm-project/commit/7a276c8acfc3977de8c3ceb0af67fcf603834946
Author: Dave Lee <davelee.com at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCTypeEncodingParser.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCTypeEncodingParser.h
Log Message:
-----------
[lldb] Fix logic error in AppleObjCTypeEncodingParser (#137067)
Fixes parsing of an ObjC type encoding such as `{?="a""b"}`. Parsing of such a type
encoding would lead to an assert. This was observed when running `language objc
class-table dump`.
The function `ReadQuotedString` consumes the closing quote, however one of its two
callers (`ReadStructElement`) was also consuming a quote. For the above type encoding,
where two quoted strings occur back to back, the parser would unintentionally consume
the opening quote of the second quoted string - leaving the remaining text with an
unbalanced quote.
This changes fixes `ReadStructElement` to not consume a quote after calling
`ReadQuotedString`.
For callers to know whether a string was successfully parsed, `ReadQuotedString` now
returns an optional string.
Commit: 8832a5950f3b62331842ecb2f3a68f33732822eb
https://github.com/llvm/llvm-project/commit/8832a5950f3b62331842ecb2f3a68f33732822eb
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/lib/Frontend/CompilerInstance.cpp
Log Message:
-----------
[clang] Enable making the module build stack thread-safe (#137059)
This PR makes another piece of the
`CompilerInstance::cloneForModuleCompile()` result thread-safe: the
module build stack. This data structure is used to detect cyclic
dependencies between modules. The problem is that it uses
`FullSourceLoc` which refers to the `SourceManager` of the parent
`CompilerInstance`: if two threads happen to execute `CompilerInstance`s
cloned from the same parent concurrently, and both discover a dependency
cycle, they may concurrently access the parent `SourceManager` when
emitting the diagnostic, creating a data race.
In this PR, we prevent this by keeping the stack empty and moving the
responsibility of cycle detection to the client. The client can recreate
the same module build stack externally and ensure thread-safety by
enforcing mutual exclusion.
Commit: 1143a04f349c4081a1a2d2503046f6ca422aa338
https://github.com/llvm/llvm-project/commit/1143a04f349c4081a1a2d2503046f6ca422aa338
Author: Vladislav Dzhidzhoev <vdzhidzhoev at accesssoftek.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/test/DebugInfo/Generic/inline-scopes.ll
A llvm/test/DebugInfo/Generic/lexical-block-abstract-origin.ll
M llvm/test/DebugInfo/X86/lexical-block-file-inline.ll
M llvm/test/DebugInfo/X86/missing-abstract-variable.ll
Log Message:
-----------
[DebugInfo][DWARF] Emit DW_AT_abstract_origin for concrete/inlined DW_TAG_lexical_blocks (#136205)
During the discussion under
https://github.com/llvm/llvm-project/pull/119001, it was noticed that
concrete DW_TAG_lexical_blocks should refer to corresponding abstract
DW_TAG_lexical_blocks by having DW_AT_abstract_origin, to avoid
ambiguity. This behavior is implemented in GCC
(https://godbolt.org/z/Khrzdq1Wx), but not in LLVM.
Fixes https://github.com/llvm/llvm-project/issues/49297.
Commit: 3e7e23d7d0eecf30dbb8adfae175696262e0b08e
https://github.com/llvm/llvm-project/commit/3e7e23d7d0eecf30dbb8adfae175696262e0b08e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/test/Headers/__clang_hip_cmath.hip
M clang/test/Headers/__clang_hip_math.hip
Log Message:
-----------
clang/HIP: Add tests that shows fpmath metadata ends up on sqrt calls (#136413)
Make sure the builtin header sqrts work with
-fno-hip-f32-correctly-rounded-divide-sqrt, and we end up with
properly annotated sqrt intrinsic callsites.
Commit: 6e3b16bec3a3384d8d2deb23d770d1d6a7357c50
https://github.com/llvm/llvm-project/commit/6e3b16bec3a3384d8d2deb23d770d1d6a7357c50
Author: David Green <david.green at arm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-shift-imm.mir
M llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll
Log Message:
-----------
[AArch64][GlobalISel] Fix EXTRACT_SUBREG reg classes in patterns to generate MULL. (#136083)
This fixes the GISel warning "Skipped pattern: EXTRACT_SUBREG child #0
could not be coerced to a register class" by ensuring the register class
is correct for the EXTRACT_SUBREG patterns. This most notably allows
UMADDL / SMADDL patterns to be imported (many still do not work as a
PatLeaf on a child cannot be generated at the moment).
Commit: 2bc6f9d4b6ff1d838f1c2d50cacbab6ba2f20bc9
https://github.com/llvm/llvm-project/commit/2bc6f9d4b6ff1d838f1c2d50cacbab6ba2f20bc9
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/utils/TableGen/ClangAttrEmitter.cpp
M clang/utils/TableGen/NeonEmitter.cpp
M llvm/docs/TableGen/BackGuide.rst
M llvm/include/llvm/TableGen/Record.h
M llvm/lib/TableGen/DetailedRecordsBackend.cpp
M llvm/lib/TableGen/JSONBackend.cpp
M llvm/lib/TableGen/Record.cpp
M llvm/lib/TableGen/SetTheory.cpp
M llvm/lib/TableGen/TGParser.cpp
M llvm/utils/TableGen/CallingConvEmitter.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/TableGen/SearchableTableEmitter.cpp
M mlir/lib/Tools/tblgen-lsp-server/TableGenServer.cpp
M mlir/tools/mlir-tblgen/OmpOpGen.cpp
M mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp
M mlir/tools/mlir-tblgen/TosaUtilsGen.cpp
Log Message:
-----------
[TableGen] Only store direct superclasses in Record (#123072)
In Record only store the direct superclasses instead of all
superclasses. getSuperClasses recurses to find all superclasses when
necessary.
This gives a small reduction in memory usage. On lib/Target/X86/X86.td I
measured about 2.0% reduction in total bytes allocated (measured by
valgrind) and 1.3% reduction in peak memory usage (measured by
/usr/bin/time -v).
---------
Co-authored-by: Min-Yih Hsu <min at myhsu.dev>
Commit: d6bb786705d0fe76d62010457eac0f8f05af7009
https://github.com/llvm/llvm-project/commit/d6bb786705d0fe76d62010457eac0f8f05af7009
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Utils/Local.cpp
A llvm/test/Transforms/SimplifyCFG/X86/debugloc-invoke-to-call-br.ll
Log Message:
-----------
[DebugInfo] Propagate source loc from invoke to replacement branch (#137206)
An existing transformation replaces invoke instructions with a call to
the invoked function and a branch to the destination; when this happens,
we propagate the invoke's source location to the call but not to the
branch. This patch updates this behaviour to propagate to the branch as
well.
Found using https://github.com/llvm/llvm-project/pull/107279.
Commit: 92dc18b6df043d788d77b4a98e5afa3954a44cb0
https://github.com/llvm/llvm-project/commit/92dc18b6df043d788d77b4a98e5afa3954a44cb0
Author: Vladislav Dzhidzhoev <vdzhidzhoev at accesssoftek.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
A llvm/test/DebugInfo/AArch64/lexical-block-abstract-origin.ll
R llvm/test/DebugInfo/Generic/lexical-block-abstract-origin.ll
Log Message:
-----------
[DebugInfo] Fix build failure introduced by 1143a04f.
Move test to AArch64 directory.
Commit: 10f6c3e2702c6ab6751861e894741d23b902cb65
https://github.com/llvm/llvm-project/commit/10f6c3e2702c6ab6751861e894741d23b902cb65
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/X86/combine-pmuldq.ll
M llvm/test/CodeGen/X86/masked_store_trunc.ll
M llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll
M llvm/test/CodeGen/X86/masked_store_trunc_usat.ll
M llvm/test/CodeGen/X86/pr40891.ll
M llvm/test/CodeGen/X86/psubus.ll
M llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll
M llvm/test/CodeGen/X86/vector-trunc-nowrap.ll
M llvm/test/CodeGen/X86/vector-trunc-packus.ll
M llvm/test/CodeGen/X86/vector-trunc-ssat.ll
M llvm/test/CodeGen/X86/vector-trunc-usat.ll
M llvm/test/CodeGen/X86/vector-trunc.ll
Log Message:
-----------
[DAG] visitCONCAT_VECTORS - relax legality checks (#137210)
We can fold combineConcatVectorOfConcatVectors/combineConcatVectorOfExtracts until after vector legalization
Commit: f427890a1dcd7759240568f189df8fbbcf23669c
https://github.com/llvm/llvm-project/commit/f427890a1dcd7759240568f189df8fbbcf23669c
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/phi-comparator.ll
Log Message:
-----------
[SLP]Fix PHI comparator to make it follow weak strict ordering restriction
Fixes #137164
Commit: 5f9164978b218fa65c53a59e91ea01831735f7a4
https://github.com/llvm/llvm-project/commit/5f9164978b218fa65c53a59e91ea01831735f7a4
Author: higher-performance <higher.performance.github at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M libcxx/include/__tree
Log Message:
-----------
Optimize std::__tree::__assign_multi to insert the provided range at the end of the tree every time (#131030)
This improves performance for the copy-assignment operators of associative containers such as `std::map`.
This optimization already exists in other places in the codebase, and seems to have been missed here.
Commit: a7a74b349d508e0cc0de53d90a695e3675f54b6a
https://github.com/llvm/llvm-project/commit/a7a74b349d508e0cc0de53d90a695e3675f54b6a
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/PhaseOrdering/AArch64/slpordering.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/loadorder.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/transpose-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/transpose.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
M llvm/test/Transforms/SLPVectorizer/vectorize-reorder-alt-shuffle.ll
Log Message:
-----------
[SLP]Improve reordering of the alternate nodes
Better to preserve the original order of the alternate nodes to avoid
inter-lane shuffling, select/insert subvector patterns provide better
perf.
Reviewers: RKSimon, hiraditya
Reviewed By: RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/136329
Commit: a9d93ecf1f8d2cfe3f77851e0df179b386cff353
https://github.com/llvm/llvm-project/commit/a9d93ecf1f8d2cfe3f77851e0df179b386cff353
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/lib/CodeGen/BackendUtil.cpp
M llvm/docs/HowToUpdateDebugInfo.rst
M llvm/include/llvm/IR/DebugLoc.h
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/DebugLoc.cpp
M llvm/lib/Transforms/Utils/Debugify.cpp
Log Message:
-----------
[DLCov] Implement DebugLoc coverage tracking (#107279)
This is part of a series of patches that tries to improve DILocation bug
detection in Debugify; see the review for more details. This is the patch
that adds the main feature, adding a set of `DebugLoc::get<Kind>`
functions that can be used for instructions with intentionally empty
DebugLocs to prevent Debugify from treating them as bugs, removing the
currently-pervasive false positives and allowing us to use Debugify (in
its original DI preservation mode) to reliably detect existing bugs and
regressions. This patch does not add uses of these functions, except for
once in Clang before optimizations, and in
`Instruction::dropLocation()`, since that is an obvious case that
immediately removes a set of false positives.
Commit: 7cce38beea2d79d77ae5e87674d3b790efa60b5f
https://github.com/llvm/llvm-project/commit/7cce38beea2d79d77ae5e87674d3b790efa60b5f
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
Log Message:
-----------
[VPlan] Remove dead SE argument from handleUncountableEarlyExit (NFC).
ScalarEvolution is not used by the function, remove the dead arg.
Commit: c8dc3ed9c464580273c2d91b8ec769d4f0193a1b
https://github.com/llvm/llvm-project/commit/c8dc3ed9c464580273c2d91b8ec769d4f0193a1b
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M flang/lib/Optimizer/Transforms/CUFGPUToLLVMConversion.cpp
M flang/test/Fir/CUDA/cuda-gpu-launch-func.mlir
Log Message:
-----------
[flang][cuda] Convert gpu.launch_func with result (#137231)
We cannot use `replaceOp` because the newly created operation has not
the same number of results.
Commit: f261f1406d4870410d3c9e61903e65ffd427d8ec
https://github.com/llvm/llvm-project/commit/f261f1406d4870410d3c9e61903e65ffd427d8ec
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
A llvm/test/CodeGen/RISCV/atomic-load-zext.ll
Log Message:
-----------
[SelectionDAG][RISCV] Teach computeKnownBits to use range metadata for atomic_load. (#137119)
And teach SelectionDAGBuilder to get the range metadata in
visitAtomicLoad.
This allows us to recognize that sign extending a byte load of a
boolean value from memory will produce zeros for the extended bits.
This allow us to remove an AND on RISC-V.
Tests copied from #136502 with range metadata added to i1 cases.
Some of the test effects overlap with #136502, but that patch can't
handle the acquire or seq_cst cases with the Zalasr extension. We
only have sign extending versions of those loads.
Commit: dd9f92c8862a08c4a632edfd5f254b08c225b412
https://github.com/llvm/llvm-project/commit/dd9f92c8862a08c4a632edfd5f254b08c225b412
Author: David Blaikie <dblaikie at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/test/DebugInfo/Generic/inline-scopes.ll
M llvm/test/DebugInfo/X86/lexical-block-file-inline.ll
M llvm/test/DebugInfo/X86/missing-abstract-variable.ll
Log Message:
-----------
Revert "[DebugInfo][DWARF] Emit DW_AT_abstract_origin for concrete/inlined DW_TAG_lexical_blocks" (#137237)
Reverts llvm/llvm-project#136205
Breaks buildbots, probably something about needing to restrict the test
to running on a specific target or the like - I haven't looked closely.
Co-authored-by: Vladislav Dzhidzhoev <dzhidzhoev at gmail.com>
Commit: f12fb2ff74ee2a1a5d7d4ae6ecc7dd1ee7b622cb
https://github.com/llvm/llvm-project/commit/f12fb2ff74ee2a1a5d7d4ae6ecc7dd1ee7b622cb
Author: Ashley Coleman <ascoleman at microsoft.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/include/llvm/Analysis/DXILResource.h
M llvm/lib/Analysis/DXILResource.cpp
M llvm/test/Analysis/DXILResource/buffer-frombinding.ll
M llvm/unittests/Target/DirectX/UniqueResourceFromUseTests.cpp
Log Message:
-----------
[HLSL] Analyze updateCounter usage (#135669)
Fixes https://github.com/llvm/llvm-project/issues/135667
Analyze and annotate `ResourceInfo` with the derived direction of calls
to updateCounter (if any).
This change only sets the value. Any diagnostics that should be raised
must be done somewhere else.
Commit: 73ddbd3c094274cfb7412d7c0fc99c170325217a
https://github.com/llvm/llvm-project/commit/73ddbd3c094274cfb7412d7c0fc99c170325217a
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
A clang/test/CodeGen/cfi-icall-trap-recover-runtime.c
A clang/test/CodeGenCXX/cfi-vcall-trap-recover-runtime.cpp
Log Message:
-----------
[NFC][CFI] Add tests for different reporting settings (#137225)
1. Trap
2. Abort from runtime
3. Recover from runtime
4. Abort from minimal runtime
5. Recover from minimal runtime
They already work as expected.
Commit: 3c3992269c65d4a4269c8617d162daa02f7731f8
https://github.com/llvm/llvm-project/commit/3c3992269c65d4a4269c8617d162daa02f7731f8
Author: Finn Plummer <canadienfinn at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/include/clang/Parse/ParseHLSLRootSignature.h
M clang/lib/Parse/ParseHLSLRootSignature.cpp
M clang/unittests/Parse/ParseHLSLRootSignatureTest.cpp
M llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h
Log Message:
-----------
[HLSL][RootSignature] Add parsing of ShaderVisibility to DescriptorTable (#136751)
- Defines `parseShaderVisiblity` to establish how single enums will be
parsed
- Adds unit testing of the visiblity enum
Part three of implementing #126569
Commit: 1636f4af7bccf466d8e5cd4c0cfdf2f7ca99b060
https://github.com/llvm/llvm-project/commit/1636f4af7bccf466d8e5cd4c0cfdf2f7ca99b060
Author: Jeffrey Byrnes <jeffrey.byrnes at amd.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/include/llvm/Analysis/CmpInstAnalysis.h
M llvm/lib/Analysis/CmpInstAnalysis.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
Log Message:
-----------
[CmpInstAnalysis] Decompose icmp eq (and x, C) C2 (#136367)
This type of decomposition is used in multiple places already. Adding it
to `CmpInstAnalysis` reduces code duplication.
Commit: 37b135cc8f079483a3a969a79898e1d3933d0067
https://github.com/llvm/llvm-project/commit/37b135cc8f079483a3a969a79898e1d3933d0067
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/test/Transforms/Attributor/issue87856.ll
Log Message:
-----------
Attributor: Don't rely on use_empty for constants (#137218)
This allows inferring noalias on a null argument parameter. This
avoids a non-NFC diff in a future change.
Commit: 4ed8bfd0c3949dbf4e3042bd35eb274373e55cf7
https://github.com/llvm/llvm-project/commit/4ed8bfd0c3949dbf4e3042bd35eb274373e55cf7
Author: Peter Collingbourne <peter at pcc.me.uk>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/LiveRangeShrink.cpp
Log Message:
-----------
LiveRangeShrink: Early exit when encountering a code motion barrier.
Without this, we end up with quadratic behavior affecting functions with
large numbers of code motion barriers, such as CFI jump tables.
As a drive-by cleanup, remove a redundant store to SawStore in this
pass as it is also done by isSafeToMove.
Reviewers: arsenm
Reviewed By: arsenm
Pull Request: https://github.com/llvm/llvm-project/pull/136806
Commit: c007c465403ecfea7c390a2b05e555c3b6d90a88
https://github.com/llvm/llvm-project/commit/c007c465403ecfea7c390a2b05e555c3b6d90a88
Author: Steffi Stumpos <stumposs12 at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/test/CodeGen/NVPTX/st-param-imm.ll
Log Message:
-----------
[NVPTX] Support BFloat Store Parameter (#137074)
Before this patch, the instruction selector assumed that if the Memory
Type is not {f16, v2f16, f32, f64} then the node type must be a
ConstantSDNode when in fact if the memory type is bf16 then the node
type is ConstantFPSDNode.
Commit: bea3b9214ea74d0678094e660c0b56893f5c9c2f
https://github.com/llvm/llvm-project/commit/bea3b9214ea74d0678094e660c0b56893f5c9c2f
Author: Vladislav Dzhidzhoev <vdzhidzhoev at accesssoftek.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/test/DebugInfo/Generic/inline-scopes.ll
M llvm/test/DebugInfo/X86/lexical-block-file-inline.ll
M llvm/test/DebugInfo/X86/missing-abstract-variable.ll
Log Message:
-----------
Revert "Revert "[DebugInfo][DWARF] Emit DW_AT_abstract_origin for concrete/inlined DW_TAG_lexical_blocks"" (#137243)
Reverts llvm/llvm-project#137237, as the problem was fixed with
92dc18b6df043d788d77b4a98e5afa3954a44cb0.
Commit: 63f5c6ae0b71189e717aca7aa4ef16d856de7e32
https://github.com/llvm/llvm-project/commit/63f5c6ae0b71189e717aca7aa4ef16d856de7e32
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/Complex/IR/ComplexOps.td
Log Message:
-----------
[mlir][complex][NFC] Fix typo in PowOp (#137240)
Commit: 425b9539684be00f3c8ccde54dbab18ce9bc8ebd
https://github.com/llvm/llvm-project/commit/425b9539684be00f3c8ccde54dbab18ce9bc8ebd
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
M clang/test/AST/ByteCode/cxx11.cpp
M clang/test/SemaCXX/constant-expression-p2280r4.cpp
Log Message:
-----------
[clang][bytecode] Emit diagnostics from GetGlobalUnchecked (#137203)
If the global is uninitialized.
Commit: 9f74d517f13a4f1f5ca340d15c8d858f3784ec5c
https://github.com/llvm/llvm-project/commit/9f74d517f13a4f1f5ca340d15c8d858f3784ec5c
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M compiler-rt/test/ubsan_minimal/CMakeLists.txt
M compiler-rt/test/ubsan_minimal/lit.common.cfg.py
M compiler-rt/test/ubsan_minimal/lit.site.cfg.py.in
Log Message:
-----------
[NFC][UBSAN] Fix minimal UBSAN test names (#137244)
Same approach as in Asan.
Now it's going to print:
```
Failed Tests (2):
UBSan-Minimal-i386-linux :: TestCases/icall.c
UBSan-Minimal-x86_64-linux :: TestCases/icall.c
```
Before it was:
```
Failed Tests (2):
UBSan-Minimal-x86_64 :: TestCases/icall.c
UBSan-Minimal-x86_64 :: TestCases/icall.c
```
Commit: a7e53124eb1376b0f04a1f6d7d40a596532905b6
https://github.com/llvm/llvm-project/commit/a7e53124eb1376b0f04a1f6d7d40a596532905b6
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
A clang/test/Analysis/Checkers/WebKit/unchecked-call-arg.cpp
Log Message:
-----------
[alpha.webkit.UncheckedCallArgsChecker] Checker fails to recognize CanMakeCheckedPtrBase (#136500)
This PR fixes the bug that alpha.webkit.UncheckedCallArgsChecker did not
recognize CanMakeCheckedPtrBase due to getAsCXXRecordDecl returning
nullptr for it in hasPublicMethodInBase. Manually grab getTemplatedDecl
out of TemplateSpecializationType then CXXRecordDecl to workaround this
bug in clang frontend.
Commit: 8baa212b7aef800a0f7d9abad529a3976bef9d50
https://github.com/llvm/llvm-project/commit/8baa212b7aef800a0f7d9abad529a3976bef9d50
Author: Justin Bogner <mail at justinbogner.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/DirectX/DXILResourceAccess.cpp
M llvm/test/CodeGen/DirectX/ResourceAccess/load_typedbuffer.ll
Log Message:
-----------
[DirectX] Handle <1 x ...> loads in DXILResourceAccess (#137076)
We can end up with loads of single element vectors when we have scalar
values, because the vectorizer may introduce these to use ops like
shufflevector in some cases. Make sure we're maintaining the correct
type when translating these into resource load operations.
Fixes #136409.
Commit: 5d0afacd1bda42350efcd6ad567c70ec5c9d19d6
https://github.com/llvm/llvm-project/commit/5d0afacd1bda42350efcd6ad567c70ec5c9d19d6
Author: Amir Ayupov <aaupov at fb.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/lib/Profile/DataAggregator.cpp
Log Message:
-----------
[BOLT][NFCI] Emit uniform diagnostics in DataAggregator (#136530)
DataAggregator supports reading different kinds of profile data:
- perf data: branch records or IP samples,
- pre-aggregated branch data.
Make profile quality reporting uniform across all kinds of input:
- out-of-range and mismatching samples,
- samples in cold code in BAT mode (profiled BOLTed binary).
Test Plan: NFCI
Commit: 08efca9c2c2b9005a0390965a2bad9ef208e4db4
https://github.com/llvm/llvm-project/commit/08efca9c2c2b9005a0390965a2bad9ef208e4db4
Author: jeremyd2019 <github at jdrake.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/cmake/modules/AddLLVM.cmake
M llvm/tools/llvm-config/BuildVariables.inc.in
M llvm/tools/llvm-config/CMakeLists.txt
M llvm/tools/llvm-config/llvm-config.cpp
M llvm/tools/llvm-shlib/CMakeLists.txt
Log Message:
-----------
[LLVM][Cygwin] Fix shared library name (#136599)
Treat Cygwin like WIN32 in llvm-shlib for naming the library.
Don't create shlib symlinks on Cygwin, they don't help anything there,
but teach llvm_install_library_symlink that Cygwin's shared libraries
live in BINDIR like WIN32.
Add a new variable to llvm-config's BuildVariables to have CMake's
shared library prefix, to avoid having to patch between "cyg" and
"msys-" on MSYS2.
Commit: 855418a000ea156f6833ea377fba0c3e8070d4f2
https://github.com/llvm/llvm-project/commit/855418a000ea156f6833ea377fba0c3e8070d4f2
Author: jeremyd2019 <github at jdrake.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M .github/CODEOWNERS
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/lib/Core/MCPlusBuilder.cpp
M bolt/lib/Passes/ProfileQualityStats.cpp
M bolt/lib/Profile/DataAggregator.cpp
A bolt/test/X86/profile-quality-reporting-small-binary.s
M bolt/test/X86/profile-quality-reporting.test
M bolt/test/link_fdata.py
M bolt/unittests/Core/MCPlusBuilder.cpp
M clang-tools-extra/clang-doc/BitcodeWriter.cpp
M clang-tools-extra/clang-doc/HTMLGenerator.cpp
M clang-tools-extra/clang-doc/Serialize.cpp
M clang-tools-extra/clangd/IncludeCleaner.cpp
M clang-tools-extra/clangd/InlayHints.cpp
M clang-tools-extra/clangd/InlayHints.h
M clang-tools-extra/clangd/SystemIncludeExtractor.cpp
M clang-tools-extra/clangd/XRefs.cpp
M clang-tools-extra/clangd/unittests/CallHierarchyTests.cpp
M clang-tools-extra/clangd/unittests/InlayHintTests.cpp
M clang-tools-extra/clangd/unittests/XRefsTests.cpp
M clang/bindings/python/clang/cindex.py
A clang/bindings/python/tests/cindex/INPUTS/a.inc
A clang/bindings/python/tests/cindex/INPUTS/b.inc
A clang/bindings/python/tests/cindex/INPUTS/testfile.c
M clang/bindings/python/tests/cindex/test_file.py
M clang/docs/ReleaseNotes.rst
M clang/docs/StandardCPlusPlusModules.rst
M clang/include/clang/AST/Type.h
M clang/include/clang/Basic/AddressSpaces.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/BuiltinHeaders.def
M clang/include/clang/Basic/BuiltinsAArch64.def
M clang/include/clang/Basic/BuiltinsARM.def
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/arm_sme.td
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/Dialect/IR/CIRTypes.td
M clang/include/clang/CIR/Dialect/IR/CIRTypesDetails.h
M clang/include/clang/CIR/MissingFeatures.h
M clang/include/clang/Driver/Distro.h
M clang/include/clang/Driver/Options.td
M clang/include/clang/Frontend/CompilerInstance.h
M clang/include/clang/Lex/DependencyDirectivesScanner.h
M clang/include/clang/Lex/Preprocessor.h
M clang/include/clang/Lex/PreprocessorOptions.h
M clang/include/clang/Parse/ParseHLSLRootSignature.h
M clang/include/clang/Parse/Parser.h
M clang/include/clang/Sema/AnalysisBasedWarnings.h
M clang/include/clang/Sema/ScopeInfo.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/SemaARM.h
M clang/include/clang/Sema/SemaCUDA.h
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningFilesystem.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpState.cpp
M clang/lib/AST/ByteCode/InterpState.h
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/AST/ByteCode/PrimType.h
M clang/lib/AST/Decl.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/ItaniumCXXABI.cpp
M clang/lib/AST/RecordLayoutBuilder.cpp
M clang/lib/AST/Type.cpp
M clang/lib/AST/TypePrinter.cpp
M clang/lib/Basic/DiagnosticIDs.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/AVR.h
M clang/lib/Basic/Targets/DirectX.h
M clang/lib/Basic/Targets/NVPTX.cpp
M clang/lib/Basic/Targets/NVPTX.h
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/Basic/Targets/SystemZ.h
M clang/lib/Basic/Targets/TCE.h
M clang/lib/Basic/Targets/WebAssembly.h
M clang/lib/Basic/Targets/X86.h
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenRecordLayout.h
M clang/lib/CIR/CodeGen/CIRGenStmt.cpp
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.h
M clang/lib/CIR/CodeGen/CIRGenValue.h
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/IR/CIRMemorySlot.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/CodeGen/CGClass.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGDebugInfo.h
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/Targets/ARM.cpp
M clang/lib/CodeGen/Targets/DirectX.cpp
M clang/lib/Driver/Distro.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/SanitizerArgs.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Format/FormatTokenLexer.cpp
M clang/lib/Format/FormatTokenLexer.h
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Frontend/CompilerInstance.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Frontend/HeaderIncludeGen.cpp
M clang/lib/Headers/arm_acle.h
M clang/lib/Index/IndexBody.cpp
M clang/lib/Lex/PPLexerChange.cpp
M clang/lib/Parse/ParseExpr.cpp
M clang/lib/Parse/ParseHLSLRootSignature.cpp
M clang/lib/Parse/Parser.cpp
M clang/lib/Sema/AnalysisBasedWarnings.cpp
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaARM.cpp
M clang/lib/Sema/SemaCUDA.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaObjC.cpp
M clang/lib/Sema/SemaObjCProperty.cpp
M clang/lib/Sema/SemaOpenACCClause.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/Serialization/ModuleManager.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefMemberChecker.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
M clang/test/AST/ByteCode/c.c
M clang/test/AST/ByteCode/cxx11.cpp
M clang/test/AST/ByteCode/cxx20.cpp
M clang/test/AST/ByteCode/cxx23.cpp
M clang/test/AST/ByteCode/cxx26.cpp
A clang/test/AST/ByteCode/i686.cpp
M clang/test/AST/ByteCode/literals.cpp
M clang/test/AST/ByteCode/records.cpp
M clang/test/AST/HLSL/OutArgExpr.hlsl
M clang/test/AST/HLSL/StructuredBuffers-AST.hlsl
M clang/test/AST/HLSL/TypedBuffers-AST.hlsl
M clang/test/AST/ast-dump-recovery.cpp
M clang/test/AST/new-unknown-type.cpp
A clang/test/Analysis/Checkers/WebKit/unchecked-call-arg.cpp
M clang/test/Analysis/Checkers/WebKit/unchecked-members.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-members.cpp
M clang/test/Analysis/Checkers/WebKit/unretained-call-args-arc.mm
M clang/test/Analysis/Checkers/WebKit/unretained-call-args.mm
M clang/test/Analysis/Checkers/WebKit/unretained-local-vars-arc.mm
M clang/test/Analysis/Checkers/WebKit/unretained-local-vars.mm
A clang/test/Analysis/pragma-diag-control.cpp
M clang/test/CIR/CodeGen/binop.cpp
M clang/test/CIR/CodeGen/struct.c
M clang/test/CIR/CodeGen/struct.cpp
M clang/test/CIR/CodeGen/typedef.c
M clang/test/CIR/CodeGen/union.c
M clang/test/CIR/CodeGenOpenACC/data.c
M clang/test/CIR/CodeGenOpenACC/init.c
M clang/test/CIR/CodeGenOpenACC/kernels.c
M clang/test/CIR/CodeGenOpenACC/parallel.c
M clang/test/CIR/CodeGenOpenACC/serial.c
M clang/test/CIR/CodeGenOpenACC/set.c
M clang/test/CIR/CodeGenOpenACC/shutdown.c
A clang/test/CIR/IR/stack-save-restore.cir
M clang/test/CIR/IR/struct.cir
A clang/test/CIR/Lowering/select.cir
A clang/test/CIR/Lowering/stack-save-restore.cir
M clang/test/CodeGen/AArch64/gcs.c
A clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
R clang/test/CodeGen/Inputs/cuda.h
A clang/test/CodeGen/arm-former-microsoft-intrinsics-header-warning.c
A clang/test/CodeGen/arm-former-microsoft-intrinsics.c
A clang/test/CodeGen/arm-interrupt-save-fp-attr-status-regs.c
A clang/test/CodeGen/arm-interrupt-save-fp-attr.c
M clang/test/CodeGen/arm-microsoft-intrinsics.c
A clang/test/CodeGen/arm64-former-microsoft-intrinsics-header-warning.c
A clang/test/CodeGen/arm64-former-microsoft-intrinsics.c
M clang/test/CodeGen/arm64-microsoft-intrinsics.c
M clang/test/CodeGen/avr/avr-inline-asm-constraints.c
M clang/test/CodeGen/avr/avr-unsupported-inline-asm-constraints.c
M clang/test/CodeGen/builtins-arm-microsoft.c
A clang/test/CodeGen/cfi-icall-trap-recover-runtime.c
R clang/test/CodeGen/nvptx-surface.cu
M clang/test/CodeGen/target-data.c
M clang/test/CodeGenCUDA/Inputs/cuda.h
M clang/test/CodeGenCUDA/builtins-sm90.cu
M clang/test/CodeGenCUDA/correctly-rounded-div.cu
A clang/test/CodeGenCUDA/lambda-constexpr-capture.cu
A clang/test/CodeGenCUDA/nvptx-surface.cu
M clang/test/CodeGenCUDA/offloading-entries.cu
M clang/test/CodeGenCUDA/profile-coverage-mapping.cu
M clang/test/CodeGenCUDA/propagate-attributes.cu
A clang/test/CodeGenCUDASPIRV/printf.cu
A clang/test/CodeGenCXX/cfi-vcall-trap-recover-runtime.cpp
R clang/test/CodeGenCXX/debug-info-dtor-implicit-args.cpp
M clang/test/CodeGenCXX/mangle-template.cpp
A clang/test/CodeGenDirectX/unsupported_intrinsic.hlsl
M clang/test/CodeGenHLSL/ArrayAssignable.hlsl
M clang/test/CodeGenHLSL/builtins/AppendStructuredBuffer-elementtype.hlsl
M clang/test/CodeGenHLSL/builtins/ConsumeStructuredBuffer-elementtype.hlsl
M clang/test/CodeGenHLSL/builtins/RWBuffer-subscript.hlsl
M clang/test/CodeGenHLSL/builtins/RWStructuredBuffer-elementtype.hlsl
M clang/test/CodeGenHLSL/builtins/StructuredBuffer-elementtype.hlsl
M clang/test/CodeGenHLSL/builtins/StructuredBuffers-subscripts.hlsl
M clang/test/Driver/Xclangas.s
M clang/test/Driver/cl-options.c
M clang/test/Driver/cxa-atexit.cpp
M clang/test/Driver/fsanitize.c
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Driver/riscv-cpus.c
M clang/test/Driver/sanitizer-ld.c
M clang/test/Format/lit.local.cfg
M clang/test/Headers/Inputs/include/stdint.h
M clang/test/Headers/__clang_hip_cmath.hip
M clang/test/Headers/__clang_hip_math.hip
M clang/test/Headers/ms-intrin.cpp
M clang/test/Misc/target-invalid-cpu-note/riscv.c
A clang/test/Modules/Inputs/PR137102/module.modulemap
A clang/test/Modules/Inputs/PR137102/type_aware_destroying_new_delete.h
M clang/test/Modules/explicit-build.cpp
A clang/test/Modules/type-aware-destroying-new-and-delete-modules.cpp
A clang/test/PCH/Inputs/type_aware_destroying_new_delete.h
A clang/test/PCH/type-aware-destroying-new-and-delete-pch.cpp
M clang/test/Parser/cxx-concepts-requires-clause.cpp
A clang/test/Parser/extern-template-attributes.cpp
A clang/test/Preprocessor/print-header-crash.modulemap
M clang/test/Preprocessor/print-header-json.c
M clang/test/Preprocessor/riscv-target-features.c
A clang/test/Sema/aarch64-sme2p2-instrinsics/acle_sme2p2_fp8_imm.cpp
M clang/test/Sema/arm-interrupt-attr.c
A clang/test/Sema/arm-interrupt-save-fp-attr.c
A clang/test/Sema/implicit-void-ptr-cast.c
M clang/test/SemaCXX/constant-expression-cxx11.cpp
M clang/test/SemaCXX/constant-expression-p2280r4.cpp
M clang/test/SemaCXX/constexpr-vectors-access-elements.cpp
A clang/test/SemaCXX/cxx20-c99-designator.cpp
M clang/test/SemaCXX/decltype.cpp
M clang/test/SemaCXX/windows-Wpadded-bitfield.cpp
M clang/test/SemaOpenACC/compute-construct-async-clause.c
M clang/test/SemaOpenACC/data-construct-async-clause.c
M clang/test/SemaTemplate/address_space-dependent.cpp
M clang/tools/driver/driver.cpp
M clang/tools/libclang/CIndex.cpp
M clang/unittests/AST/AttrTest.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/FormatTestJS.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M clang/unittests/Lex/PPDependencyDirectivesTest.cpp
M clang/unittests/Parse/ParseHLSLRootSignatureTest.cpp
M clang/unittests/libclang/LibclangTest.cpp
M clang/utils/TableGen/ClangAttrEmitter.cpp
M clang/utils/TableGen/NeonEmitter.cpp
M compiler-rt/lib/asan/asan_report.cpp
M compiler-rt/test/profile/AIX/pgo-lto-bcdtor-function-section.test
A compiler-rt/test/tsan/stack_race3.cpp
M compiler-rt/test/ubsan_minimal/CMakeLists.txt
M compiler-rt/test/ubsan_minimal/lit.common.cfg.py
M compiler-rt/test/ubsan_minimal/lit.site.cfg.py.in
M flang-rt/lib/cuda/allocator.cpp
M flang-rt/unittests/Runtime/CUDA/Allocatable.cpp
M flang/CMakeLists.txt
A flang/docs/FortranStandardsSupport.md
A flang/docs/OpenMPSupport.md
M flang/docs/index.md
M flang/examples/FeatureList/FeatureList.cpp
M flang/include/flang/Lower/DirectivesCommon.h
M flang/include/flang/Optimizer/Builder/DirectivesCommon.h
M flang/include/flang/Optimizer/Dialect/CUF/CUFOps.td
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Semantics/symbol.h
M flang/include/flang/Support/Fortran.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
M flang/lib/Optimizer/CodeGen/LowerRepackArrays.cpp
M flang/lib/Optimizer/CodeGen/TargetRewrite.cpp
M flang/lib/Optimizer/Dialect/CUF/CUFOps.cpp
M flang/lib/Optimizer/Dialect/CUF/CUFToLLVMIRTranslation.cpp
M flang/lib/Optimizer/HLFIR/Transforms/InlineElementals.cpp
M flang/lib/Optimizer/HLFIR/Transforms/InlineHLFIRAssign.cpp
M flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
M flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
M flang/lib/Optimizer/OpenACC/FIROpenACCTypeInterfaces.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/AssumedRankOpConversion.cpp
M flang/lib/Optimizer/Transforms/CUFGPUToLLVMConversion.cpp
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/lib/Optimizer/Transforms/ConstantArgumentGlobalisation.cpp
M flang/lib/Optimizer/Transforms/SimplifyFIROperations.cpp
M flang/lib/Optimizer/Transforms/StackArrays.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-acc-structure.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/rewrite-directives.cpp
A flang/test/Analysis/AliasAnalysis/alias-analysis-pack-array.fir
A flang/test/Driver/m32-option.f90
M flang/test/Fir/CUDA/cuda-gpu-launch-func.mlir
M flang/test/Fir/CUDA/cuda-launch.fir
M flang/test/Fir/CUDA/cuda-target-rewrite.mlir
M flang/test/Fir/OpenACC/openacc-mappable.fir
M flang/test/Lower/CUDA/cuda-kernel-loop-directive.cuf
M flang/test/Lower/OpenACC/acc-bounds.f90
M flang/test/Lower/OpenACC/acc-enter-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-enter-data.f90
A flang/test/Parser/OpenMP/cancel.f90
M flang/test/Semantics/OpenACC/acc-data.f90
M flang/test/Semantics/OpenACC/acc-kernels.f90
M flang/test/Semantics/OpenACC/acc-parallel.f90
M flang/test/Semantics/OpenACC/acc-serial.f90
M flang/test/Semantics/OpenMP/atomic-hint-clause.f90
M flang/test/Semantics/OpenMP/critical-hint-clause.f90
M libc/fuzzing/__support/CMakeLists.txt
R libc/fuzzing/__support/fake_heap.s
M libc/fuzzing/__support/freelist_heap_fuzz.cpp
M libc/src/math/generic/expm1f.cpp
M libc/src/stdio/printf_core/core_structs.h
M libc/test/src/__support/CMakeLists.txt
R libc/test/src/__support/fake_heap.s
M libc/test/src/__support/freelist_heap_test.cpp
R libc/test/src/math/performance_testing/BinaryOpSingleOutputPerf.h
M libc/test/src/math/performance_testing/CMakeLists.txt
A libc/test/src/math/performance_testing/PerfTest.h
R libc/test/src/math/performance_testing/SingleInputSingleOutputPerf.h
M libc/test/src/math/performance_testing/ceilf_perf.cpp
M libc/test/src/math/performance_testing/cosf_perf.cpp
M libc/test/src/math/performance_testing/exp10f16_perf.cpp
M libc/test/src/math/performance_testing/exp2f16_perf.cpp
M libc/test/src/math/performance_testing/exp2f_perf.cpp
M libc/test/src/math/performance_testing/expf16_perf.cpp
M libc/test/src/math/performance_testing/expf_perf.cpp
M libc/test/src/math/performance_testing/expm1f_perf.cpp
M libc/test/src/math/performance_testing/fabsf_perf.cpp
M libc/test/src/math/performance_testing/floorf_perf.cpp
M libc/test/src/math/performance_testing/fmod_perf.cpp
M libc/test/src/math/performance_testing/fmodf128_perf.cpp
M libc/test/src/math/performance_testing/fmodf16_perf.cpp
M libc/test/src/math/performance_testing/fmodf_perf.cpp
M libc/test/src/math/performance_testing/fmodl_perf.cpp
M libc/test/src/math/performance_testing/fmul_perf.cpp
M libc/test/src/math/performance_testing/fmull_perf.cpp
M libc/test/src/math/performance_testing/hypot_perf.cpp
M libc/test/src/math/performance_testing/hypotf16_perf.cpp
M libc/test/src/math/performance_testing/hypotf_perf.cpp
M libc/test/src/math/performance_testing/log10f_perf.cpp
M libc/test/src/math/performance_testing/log1pf_perf.cpp
M libc/test/src/math/performance_testing/log2f_perf.cpp
M libc/test/src/math/performance_testing/logbf_perf.cpp
M libc/test/src/math/performance_testing/logf_perf.cpp
M libc/test/src/math/performance_testing/max_min_funcs_perf.cpp
M libc/test/src/math/performance_testing/misc_basic_ops_perf.cpp
M libc/test/src/math/performance_testing/nearbyintf_perf.cpp
M libc/test/src/math/performance_testing/nearest_integer_funcs_perf.cpp
M libc/test/src/math/performance_testing/rintf_perf.cpp
M libc/test/src/math/performance_testing/roundf_perf.cpp
M libc/test/src/math/performance_testing/sinf_perf.cpp
M libc/test/src/math/performance_testing/sqrtf128_perf.cpp
M libc/test/src/math/performance_testing/sqrtf_perf.cpp
M libc/test/src/math/performance_testing/truncf_perf.cpp
M libclc/CMakeLists.txt
R libclc/amdgpu/lib/SOURCES_3.9
R libclc/amdgpu/lib/SOURCES_4.0
R libclc/amdgpu/lib/SOURCES_5.0
R libclc/amdgpu/lib/shared/vload_half_helpers.ll
R libclc/amdgpu/lib/shared/vstore_half_helpers.ll
M libclc/cmake/modules/AddLibclc.cmake
M libclc/generic/include/clc/clc.h
R libclc/generic/include/clc/clcmacros.h
M libclc/generic/include/clc/image/image.h
M libclc/generic/include/clc/shared/vload.h
M libclc/generic/include/clc/shared/vstore.h
M libclc/generic/lib/shared/vload.cl
M libclc/generic/lib/shared/vload_half.inc
M libclc/generic/lib/shared/vstore.cl
M libclc/generic/lib/shared/vstore_half.inc
R libclc/ptx/lib/SOURCES_3.9
R libclc/ptx/lib/SOURCES_4.0
R libclc/ptx/lib/SOURCES_5.0
R libclc/ptx/lib/shared/vload_half_helpers.ll
R libclc/ptx/lib/shared/vstore_half_helpers.ll
M libcxx/include/__ranges/to.h
M libcxx/include/__tree
M libcxx/test/libcxx/ranges/range.utility/range.utility.conv/to.static_assert.verify.cpp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array.pass.cpp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete.pass.cpp
M libcxxabi/test/test_demangle.pass.cpp
M lld/ELF/ICF.cpp
M lld/ELF/SymbolTable.cpp
M lld/ELF/SymbolTable.h
A lld/test/ELF/aarch64-got-merging-icf.s
M lld/test/ELF/icf-preemptible.s
M lldb/docs/resources/build.rst
M lldb/include/lldb/API/SBExecutionContext.h
M lldb/include/lldb/API/SBInstructionList.h
M lldb/include/lldb/Core/Debugger.h
M lldb/include/lldb/Core/FormatEntity.h
M lldb/include/lldb/Core/IOHandler.h
M lldb/include/lldb/Host/Config.h.cmake
M lldb/include/lldb/Host/Editline.h
M lldb/include/lldb/Interpreter/CommandInterpreter.h
M lldb/include/lldb/Interpreter/CommandObject.h
M lldb/include/lldb/Interpreter/OptionValueEnumeration.h
M lldb/include/lldb/Symbol/CompilerType.h
M lldb/include/lldb/Symbol/TypeSystem.h
M lldb/include/lldb/Target/Statistics.h
M lldb/include/lldb/Utility/CompletionRequest.h
M lldb/packages/Python/lldbsuite/test/lldbtest.py
M lldb/source/API/SBCommandInterpreter.cpp
M lldb/source/API/SBInstructionList.cpp
M lldb/source/Commands/CommandCompletions.cpp
M lldb/source/Commands/CommandObjectProcess.cpp
M lldb/source/Commands/Options.td
M lldb/source/Core/CoreProperties.td
M lldb/source/Core/DataFileCache.cpp
M lldb/source/Core/Debugger.cpp
M lldb/source/Core/FormatEntity.cpp
M lldb/source/Core/IOHandler.cpp
M lldb/source/Host/common/Editline.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Interpreter/OptionValueEnumeration.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangModulesDeclVendor.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxInitializerList.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxSpan.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxVariant.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxVector.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCTypeEncodingParser.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCTypeEncodingParser.h
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/Process/Utility/CMakeLists.txt
A lldb/source/Plugins/Process/Utility/RegisterContextDarwin_riscv32.cpp
A lldb/source/Plugins/Process/Utility/RegisterContextDarwin_riscv32.h
M lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.h
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
M lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp
M lldb/source/Plugins/SymbolFile/DWARF/CMakeLists.txt
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.h
A lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndexSet.cpp
A lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndexSet.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/Plugins/UnwindAssembly/x86/UnwindAssembly-x86.cpp
M lldb/source/Symbol/DWARFCallFrameInfo.cpp
M lldb/source/Symbol/Symtab.cpp
M lldb/source/Symbol/UnwindPlan.cpp
M lldb/source/Target/Statistics.cpp
M lldb/source/Target/Target.cpp
M lldb/source/Utility/ArchSpec.cpp
M lldb/test/API/commands/expression/completion/TestExprCompletion.py
A lldb/test/API/commands/process/reverse-continue/Makefile
A lldb/test/API/commands/process/reverse-continue/TestReverseContinue.py
A lldb/test/API/commands/process/reverse-continue/TestReverseContinueNotSupported.py
A lldb/test/API/commands/process/reverse-continue/main.c
M lldb/test/API/commands/settings/TestSettings.py
M lldb/test/API/commands/statistics/basic/TestStats.py
M lldb/test/API/functionalities/statusline/TestStatusline.py
A lldb/test/API/macosx/riscv32-corefile/Makefile
A lldb/test/API/macosx/riscv32-corefile/TestRV32MachOCorefile.py
A lldb/test/API/macosx/riscv32-corefile/create-empty-riscv-corefile.cpp
M lldb/test/API/terminal/TestEditline.py
R lldb/test/Shell/SymbolFile/DWARF/range-lower-then-low-pc.s
M lldb/test/Shell/SymbolFile/DWARF/x86/discontinuous-inline-function.s
M lldb/test/Shell/Unwind/Inputs/eh-frame-small-fde.s
M lldb/test/Shell/Unwind/eh-frame-small-fde.test
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/Handler/BreakpointLocationsHandler.cpp
M lldb/tools/lldb-dap/Handler/CancelRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/DisconnectRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/NextRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
M lldb/tools/lldb-dap/Handler/SourceRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/StepInRequestHandler.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolBase.h
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
M lldb/tools/lldb-dap/Transport.cpp
M lldb/unittests/Symbol/UnwindPlanTest.cpp
M lldb/unittests/SymbolFile/DWARF/DWARFIndexCachingTest.cpp
M lldb/unittests/Utility/ArchSpecTest.cpp
M llvm/CMakeLists.txt
M llvm/cmake/modules/AddLLVM.cmake
M llvm/docs/GitHub.rst
M llvm/docs/HowToUpdateDebugInfo.rst
M llvm/docs/InterfaceExportAnnotations.rst
M llvm/docs/LangRef.rst
M llvm/docs/NVPTXUsage.rst
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/docs/ResponseGuide.rst
M llvm/docs/SPIRVUsage.rst
M llvm/docs/TableGen/BackGuide.rst
M llvm/include/llvm/Analysis/CmpInstAnalysis.h
M llvm/include/llvm/Analysis/DXILResource.h
M llvm/include/llvm/Analysis/LazyBlockFrequencyInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/BinaryFormat/MachO.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/MachinePipeliner.h
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/Frontend/Directive/DirectiveBase.td
M llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h
M llvm/include/llvm/Frontend/OpenACC/ACC.td
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/Frontend/OpenMP/OMPDeviceConstants.h
M llvm/include/llvm/IR/DebugLoc.h
M llvm/include/llvm/IR/DiagnosticInfo.h
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/include/llvm/IR/IntrinsicsARM.td
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/IntrinsicsPowerPC.td
M llvm/include/llvm/IR/RuntimeLibcalls.def
M llvm/include/llvm/IR/Value.h
M llvm/include/llvm/InitializePasses.h
A llvm/include/llvm/ProfileData/IndexedMemProfData.h
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/include/llvm/Support/Caching.h
M llvm/include/llvm/Support/Compiler.h
M llvm/include/llvm/Support/InstructionCost.h
M llvm/include/llvm/Support/NVPTXAddrSpace.h
M llvm/include/llvm/TableGen/DirectiveEmitter.h
M llvm/include/llvm/TableGen/Record.h
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/include/llvm/Transforms/Utils/UnrollLoop.h
M llvm/lib/Analysis/AliasAnalysis.cpp
M llvm/lib/Analysis/Analysis.cpp
M llvm/lib/Analysis/AssumptionCache.cpp
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/BlockFrequencyInfo.cpp
M llvm/lib/Analysis/BranchProbabilityInfo.cpp
M llvm/lib/Analysis/CallGraph.cpp
M llvm/lib/Analysis/CmpInstAnalysis.cpp
M llvm/lib/Analysis/CostModel.cpp
M llvm/lib/Analysis/CtxProfAnalysis.cpp
M llvm/lib/Analysis/CycleAnalysis.cpp
M llvm/lib/Analysis/DXILMetadataAnalysis.cpp
M llvm/lib/Analysis/DXILResource.cpp
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/lib/Analysis/DomPrinter.cpp
M llvm/lib/Analysis/DominanceFrontier.cpp
M llvm/lib/Analysis/GlobalsModRef.cpp
M llvm/lib/Analysis/IRSimilarityIdentifier.cpp
M llvm/lib/Analysis/IVUsers.cpp
M llvm/lib/Analysis/InlineSizeEstimatorAnalysis.cpp
M llvm/lib/Analysis/LazyBlockFrequencyInfo.cpp
M llvm/lib/Analysis/LazyValueInfo.cpp
M llvm/lib/Analysis/LoopInfo.cpp
M llvm/lib/Analysis/LoopPass.cpp
M llvm/lib/Analysis/MemoryDependenceAnalysis.cpp
M llvm/lib/Analysis/MemorySSA.cpp
M llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
M llvm/lib/Analysis/OptimizationRemarkEmitter.cpp
M llvm/lib/Analysis/PhiValues.cpp
M llvm/lib/Analysis/PostDominators.cpp
M llvm/lib/Analysis/ProfileSummaryInfo.cpp
M llvm/lib/Analysis/RegionInfo.cpp
M llvm/lib/Analysis/RegionPrinter.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp
M llvm/lib/Analysis/ScopedNoAliasAA.cpp
M llvm/lib/Analysis/StackSafetyAnalysis.cpp
M llvm/lib/Analysis/StaticDataProfileInfo.cpp
M llvm/lib/Analysis/TargetLibraryInfo.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/TypeBasedAliasAnalysis.cpp
M llvm/lib/Analysis/UniformityAnalysis.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CGData/CodeGenData.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/CodeGen/LiveRangeShrink.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/PrologEpilogInserter.cpp
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/SplitKit.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/Debuginfod/Debuginfod.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/DebugLoc.cpp
M llvm/lib/IR/DiagnosticInfo.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/ProfDataUtils.cpp
M llvm/lib/IR/Value.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/LTO/LTOBackend.cpp
M llvm/lib/MC/MCParser/MasmParser.cpp
M llvm/lib/ProfileData/CMakeLists.txt
A llvm/lib/ProfileData/IndexedMemProfData.cpp
M llvm/lib/ProfileData/InstrProf.cpp
M llvm/lib/ProfileData/InstrProfReader.cpp
M llvm/lib/ProfileData/InstrProfWriter.cpp
M llvm/lib/Support/Caching.cpp
M llvm/lib/Support/SuffixTree.cpp
M llvm/lib/TableGen/DetailedRecordsBackend.cpp
M llvm/lib/TableGen/JSONBackend.cpp
M llvm/lib/TableGen/Record.cpp
M llvm/lib/TableGen/SetTheory.cpp
M llvm/lib/TableGen/TGParser.cpp
M llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrAtomics.td
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrGISel.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AArch64/CMakeLists.txt
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
M llvm/lib/Target/ARM/ARMCallingConv.td
M llvm/lib/Target/ARM/ARMFrameLowering.cpp
M llvm/lib/Target/ARM/ARMFrameLowering.h
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMInstrVFP.td
M llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
M llvm/lib/Target/ARM/ARMRegisterInfo.td
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/BPF/BPFISelLowering.h
M llvm/lib/Target/BPF/BPFInstrInfo.td
M llvm/lib/Target/BPF/BPFTargetTransformInfo.h
M llvm/lib/Target/DirectX/CMakeLists.txt
A llvm/lib/Target/DirectX/DXILForwardHandleAccesses.cpp
A llvm/lib/Target/DirectX/DXILForwardHandleAccesses.h
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/lib/Target/DirectX/DXILResourceAccess.cpp
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/DirectX/DirectX.h
M llvm/lib/Target/DirectX/DirectXPassRegistry.def
M llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.h
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.h
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
M llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.cpp
M llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h
M llvm/lib/Target/Mips/MipsTargetTransformInfo.cpp
M llvm/lib/Target/Mips/MipsTargetTransformInfo.h
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTX.h
M llvm/lib/Target/NVPTX/NVPTXAliasAnalysis.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp
M llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/NVPTX/NVPTXUtilities.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.h
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
M llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVSystemOperands.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
M llvm/lib/Target/SPIRV/SPIRVTargetTransformInfo.h
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/Sparc/SparcInstrVIS.td
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.h
M llvm/lib/Target/SystemZ/SystemZInstrFP.td
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
M llvm/lib/Target/VE/VETargetTransformInfo.h
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
M llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86LowerTileCopy.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/lib/Transforms/Coroutines/CoroElide.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/IPO/FunctionAttrs.cpp
M llvm/lib/Transforms/IPO/FunctionSpecialization.cpp
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/IPO/PartialInlining.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Instrumentation/SanitizerBinaryMetadata.cpp
M llvm/lib/Transforms/Instrumentation/ThreadSanitizer.cpp
M llvm/lib/Transforms/Scalar/ConstantHoisting.cpp
M llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
M llvm/lib/Transforms/Scalar/LoopDataPrefetch.cpp
M llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
M llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
M llvm/lib/Transforms/Scalar/NewGVN.cpp
M llvm/lib/Transforms/Scalar/Reassociate.cpp
M llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
M llvm/lib/Transforms/Utils/Debugify.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/MisExpect.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/runtimes/CMakeLists.txt
M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
M llvm/test/Analysis/CostModel/AArch64/vector-select.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-fadd.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-exact-vlen.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-permute.ll
M llvm/test/Analysis/CtxProfAnalysis/flatten-and-annotate.ll
M llvm/test/Analysis/CtxProfAnalysis/flatten-check-path.ll
M llvm/test/Analysis/CtxProfAnalysis/flatten-insert-icp-mdprof.ll
M llvm/test/Analysis/CtxProfAnalysis/flatten-zero-path.ll
M llvm/test/Analysis/CtxProfAnalysis/full-cycle.ll
M llvm/test/Analysis/CtxProfAnalysis/inline.ll
M llvm/test/Analysis/CtxProfAnalysis/load.ll
M llvm/test/Analysis/DXILResource/buffer-frombinding.ll
M llvm/test/Assembler/auto_upgrade_nvvm_intrinsics.ll
A llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/lower-neon-vector-fcmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-const-vector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vector-fcmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-shift-imm.mir
M llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll
M llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll
M llvm/test/CodeGen/AArch64/arm64-tbl.ll
M llvm/test/CodeGen/AArch64/arm64-zip.ll
M llvm/test/CodeGen/AArch64/fsh.ll
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/optimize-cond-branch.ll
M llvm/test/CodeGen/AArch64/select_cc.ll
A llvm/test/CodeGen/AArch64/sme2-intrinsics-mop4-fp8.ll
M llvm/test/CodeGen/AArch64/sve-extract-element.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/sve-varargs-caller-broken.ll
M llvm/test/CodeGen/AArch64/sve-varargs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
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M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
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M llvm/test/CodeGen/AMDGPU/add64-low-32-bits-known-zero.ll
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M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
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M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
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M llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
M llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
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M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
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M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/cc-update.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
M llvm/test/CodeGen/AMDGPU/constrained-shift.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll
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A llvm/test/CodeGen/AMDGPU/do-not-fold-copy.mir
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M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
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M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
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M llvm/test/CodeGen/AMDGPU/fminimum3.ll
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M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
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M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
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M llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
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M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
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M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/lower-kernargs.ll
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M llvm/test/CodeGen/AMDGPU/lround.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
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M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll
M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
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M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/ptrmask.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/sdag-print-divergence.ll
M llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
A llvm/test/CodeGen/AMDGPU/si-instr-info-vopc-exec.mir
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M llvm/test/CodeGen/AMDGPU/sub64-low-32-bits-known-zero.ll
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A llvm/test/CodeGen/AMDGPU/uniform-vgpr-to-sgpr-return.ll
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A llvm/test/CodeGen/NVPTX/addrspacecast-ptx64.ll
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A llvm/test/CodeGen/RISCV/atomic-load-zext.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
A llvm/test/CodeGen/RISCV/di-assignment-tracking-vector.ll
M llvm/test/CodeGen/RISCV/features-info.ll
A llvm/test/CodeGen/RISCV/fold-mem-offset.mir
M llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
A llvm/test/CodeGen/RISCV/pr101786.ll
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvqdotq.ll
M llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
M llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
M llvm/test/CodeGen/RISCV/xqccmp-additional-stack.ll
M llvm/test/CodeGen/RISCV/xqccmp-callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
M llvm/test/CodeGen/RISCV/xqccmp-with-float.ll
A llvm/test/CodeGen/RISCV/xqcia.ll
A llvm/test/CodeGen/RISCV/zalasr-offset-folding.ll
M llvm/test/CodeGen/RISCV/zcmp-additional-stack.ll
M llvm/test/CodeGen/RISCV/zcmp-with-float.ll
M llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
A llvm/test/CodeGen/SPARC/multiply-extension.ll
M llvm/test/CodeGen/SPARC/smulo-128-legalisation-lowering.ll
M llvm/test/CodeGen/SPARC/umulo-128-legalisation-lowering.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroup_matrix_multiply_accumulate/subgroup_matrix_multiply_accumulate_generic.ll
M llvm/test/CodeGen/SPIRV/pointers/getelementptr-downcast-struct.ll
M llvm/test/CodeGen/SPIRV/pointers/getelementptr-downcast-vector.ll
A llvm/test/CodeGen/SPIRV/pointers/store-struct.ll
M llvm/test/CodeGen/SystemZ/fp-abs-01.ll
M llvm/test/CodeGen/SystemZ/fp-abs-02.ll
M llvm/test/CodeGen/SystemZ/fp-abs-03.ll
M llvm/test/CodeGen/SystemZ/fp-abs-04.ll
M llvm/test/CodeGen/SystemZ/fp-copysign-01.ll
M llvm/test/CodeGen/SystemZ/fp-copysign-02.ll
M llvm/test/CodeGen/SystemZ/fp-copysign-03.ll
M llvm/test/CodeGen/SystemZ/fp-mul-08.ll
M llvm/test/CodeGen/SystemZ/fp-mul-10.ll
M llvm/test/CodeGen/SystemZ/fp-neg-01.ll
M llvm/test/CodeGen/SystemZ/fp-neg-02.ll
M llvm/test/CodeGen/Thumb2/mve-ctpop.ll
M llvm/test/CodeGen/VE/Vector/ticket-64420.ll
M llvm/test/CodeGen/X86/avx512-i1test.ll
M llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
M llvm/test/CodeGen/X86/bfloat.ll
M llvm/test/CodeGen/X86/build-vector-128.ll
M llvm/test/CodeGen/X86/build-vector-256.ll
M llvm/test/CodeGen/X86/build-vector-512.ll
A llvm/test/CodeGen/X86/buildvec-widen-dotproduct.ll
M llvm/test/CodeGen/X86/clobber_frame_ptr.ll
M llvm/test/CodeGen/X86/combine-fcopysign.ll
M llvm/test/CodeGen/X86/combine-pmuldq.ll
M llvm/test/CodeGen/X86/concat-fpext-v2bf16.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
M llvm/test/CodeGen/X86/extractelement-load.ll
M llvm/test/CodeGen/X86/ispow2.ll
M llvm/test/CodeGen/X86/jump_sign.ll
M llvm/test/CodeGen/X86/machine-trace-metrics-crash.ll
M llvm/test/CodeGen/X86/masked_store_trunc.ll
M llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll
M llvm/test/CodeGen/X86/masked_store_trunc_usat.ll
M llvm/test/CodeGen/X86/pr40891.ll
M llvm/test/CodeGen/X86/pr50254.ll
M llvm/test/CodeGen/X86/pr57673.ll
M llvm/test/CodeGen/X86/pr63108.ll
M llvm/test/CodeGen/X86/pr91005.ll
A llvm/test/CodeGen/X86/pr94829.ll
M llvm/test/CodeGen/X86/psubus.ll
M llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
M llvm/test/CodeGen/X86/shift-combine.ll
M llvm/test/CodeGen/X86/shuffle-combine-crash.ll
M llvm/test/CodeGen/X86/shuffle-half.ll
M llvm/test/CodeGen/X86/swifterror.ll
M llvm/test/CodeGen/X86/tailcall-cgp-dup.ll
M llvm/test/CodeGen/X86/vaargs-prolog-insert.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
M llvm/test/CodeGen/X86/vector-popcnt-128.ll
M llvm/test/CodeGen/X86/vector-popcnt-256-ult-ugt.ll
M llvm/test/CodeGen/X86/vector-popcnt-256.ll
M llvm/test/CodeGen/X86/vector-popcnt-512-ult-ugt.ll
M llvm/test/CodeGen/X86/vector-popcnt-512.ll
M llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
M llvm/test/CodeGen/X86/vector-trunc-nowrap.ll
M llvm/test/CodeGen/X86/vector-trunc-packus.ll
M llvm/test/CodeGen/X86/vector-trunc-ssat.ll
M llvm/test/CodeGen/X86/vector-trunc-usat.ll
M llvm/test/CodeGen/X86/vector-trunc.ll
M llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
A llvm/test/DebugInfo/AArch64/lexical-block-abstract-origin.ll
M llvm/test/DebugInfo/Generic/inline-scopes.ll
M llvm/test/DebugInfo/NVPTX/debug-info.ll
M llvm/test/DebugInfo/X86/lexical-block-file-inline.ll
M llvm/test/DebugInfo/X86/missing-abstract-variable.ll
A llvm/test/Instrumentation/MemorySanitizer/X86/avx512fp16-arith-intrinsics.ll
A llvm/test/Instrumentation/MemorySanitizer/X86/avx512fp16-arith-vl-intrinsics.ll
A llvm/test/Instrumentation/MemorySanitizer/X86/avx512fp16-intrinsics.ll
M llvm/test/Instrumentation/ThreadSanitizer/capture.ll
M llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
M llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
M llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/test/MC/RISCV/machine-csr-names.s
M llvm/test/MC/RISCV/rv32-machine-csr-names.s
M llvm/test/TableGen/VarLenDecoder.td
M llvm/test/TableGen/trydecode-emission.td
M llvm/test/TableGen/trydecode-emission2.td
M llvm/test/TableGen/trydecode-emission3.td
M llvm/test/TableGen/trydecode-emission4.td
M llvm/test/Transforms/Attributor/issue87856.ll
A llvm/test/Transforms/CodeGenPrepare/unfold-pow2-test-vec.ll
A llvm/test/Transforms/CodeGenPrepare/unfold-pow2-test.ll
M llvm/test/Transforms/CorrelatedValuePropagation/uscmp.ll
M llvm/test/Transforms/FunctionAttrs/initializes.ll
A llvm/test/Transforms/GlobalOpt/X86/preserve-dbgloc-of-load-store-to-bool.ll
A llvm/test/Transforms/GlobalOpt/malloc-promote-atomic.ll
M llvm/test/Transforms/InferAddressSpaces/NVPTX/isspacep.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-binop.ll
A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-shift.ll
M llvm/test/Transforms/InstCombine/and-fcmp.ll
M llvm/test/Transforms/InstCombine/clamp-to-minmax.ll
M llvm/test/Transforms/InstCombine/icmp.ll
A llvm/test/Transforms/InstCombine/max-min-canonicalize.ll
M llvm/test/Transforms/InstCombine/max_known_bits.ll
M llvm/test/Transforms/InstCombine/minmax-fold.ll
M llvm/test/Transforms/InstCombine/minmax-intrinsics.ll
M llvm/test/Transforms/InstCombine/sadd_sat.ll
M llvm/test/Transforms/InstCombine/select-min-max.ll
M llvm/test/Transforms/LoopVectorize/AArch64/blend-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-no-dotprod.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-intrinsic-calls.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/pr51366-sunk-instruction-used-outside-of-loop.ll
M llvm/test/Transforms/LoopVectorize/X86/small-size.ll
M llvm/test/Transforms/LoopVectorize/debugloc.ll
M llvm/test/Transforms/LoopVectorize/dereferenceable-info-from-assumption-constant-size.ll
M llvm/test/Transforms/LoopVectorize/float-induction.ll
M llvm/test/Transforms/LoopVectorize/if-pred-stores.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/load-deref-pred-align.ll
M llvm/test/Transforms/LoopVectorize/load-of-struct-deref-pred.ll
M llvm/test/Transforms/LoopVectorize/loop-form.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/select-cmp-multiuse.ll
M llvm/test/Transforms/LoopVectorize/select-cmp-predicated.ll
M llvm/test/Transforms/LoopVectorize/struct-return.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll
M llvm/test/Transforms/LoopVectorize/trip-count-expansion-may-introduce-ub.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing.ll
M llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll
M llvm/test/Transforms/LowerTypeTests/aarch64-jumptable.ll
M llvm/test/Transforms/LowerTypeTests/cfi-direct-call1.ll
M llvm/test/Transforms/LowerTypeTests/function-arm-thumb.ll
M llvm/test/Transforms/LowerTypeTests/function-thumb-bti.ll
M llvm/test/Transforms/LowerTypeTests/function.ll
M llvm/test/Transforms/LowerTypeTests/x86-jumptable.ll
A llvm/test/Transforms/MemProfContextDisambiguation/mergenodes.ll
A llvm/test/Transforms/MemProfContextDisambiguation/mergenodes2.ll
M llvm/test/Transforms/MemProfContextDisambiguation/overlapping-contexts.ll
M llvm/test/Transforms/MergeFunc/cfi-thunk-merging.ll
A llvm/test/Transforms/PGOProfile/memprof-dump-matched-alloc-site.ll
M llvm/test/Transforms/PGOProfile/memprof-dump-matched-call-sites.ll
M llvm/test/Transforms/PGOProfile/memprof.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/slpordering.ll
M llvm/test/Transforms/PhaseOrdering/X86/blendv-select.ll
A llvm/test/Transforms/Reassociate/canonicalize-made-change.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/loadorder.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/reused-scalar-repeated-in-node.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/transpose-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/transpose.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vectorizable-selects-uniform-cmps.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reductions.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/segmented-loads-simple.ll
M llvm/test/Transforms/SLPVectorizer/X86/full-match-with-poison-scalar.ll
M llvm/test/Transforms/SLPVectorizer/X86/full-matched-bv-with-subvectors.ll
M llvm/test/Transforms/SLPVectorizer/X86/matched-nodes-updated.ll
M llvm/test/Transforms/SLPVectorizer/X86/memory-runtime-checks.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi-extracts-bv-combined.ll
A llvm/test/Transforms/SLPVectorizer/X86/phi-comparator.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduced-val-vectorized-in-transform.ll
M llvm/test/Transforms/SLPVectorizer/X86/reorder-reused-masked-gather.ll
M llvm/test/Transforms/SLPVectorizer/icmp-altopcode-after-reordering.ll
M llvm/test/Transforms/SLPVectorizer/reordering-single-phi.ll
M llvm/test/Transforms/SLPVectorizer/vectorize-reorder-alt-shuffle.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/preserve-inbounds.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep.ll
A llvm/test/Transforms/SimplifyCFG/X86/debugloc-invoke-to-call-br.ll
A llvm/test/Transforms/VectorCombine/pr132563.ll
A llvm/test/Verifier/diassignid-vector-stores.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/nvptx-basic.ll.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/difile_absolute_filenames.ll
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/difile_absolute_filenames.ll.expected
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.globals.expected
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.transitiveglobals.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/difile_absolute_filenames.test
M llvm/test/tools/dsymutil/ARM/stmt-seq-macho.test
A llvm/test/tools/llvm-cov/branch-export-lcov-unify-instances.test
M llvm/test/tools/llvm-cov/branch-export-lcov.test
A llvm/test/tools/llvm-extract/extract-unnamed-bb.ll
M llvm/test/tools/llvm-ml/macro_function.asm
M llvm/tools/gold/gold-plugin.cpp
M llvm/tools/llvm-config/BuildVariables.inc.in
M llvm/tools/llvm-config/CMakeLists.txt
M llvm/tools/llvm-config/llvm-config.cpp
M llvm/tools/llvm-cov/CodeCoverage.cpp
M llvm/tools/llvm-cov/CoverageExporterLcov.cpp
M llvm/tools/llvm-cov/CoverageViewOptions.h
M llvm/tools/llvm-extract/llvm-extract.cpp
M llvm/tools/llvm-lto2/llvm-lto2.cpp
M llvm/tools/llvm-shlib/CMakeLists.txt
M llvm/unittests/Support/CMakeLists.txt
A llvm/unittests/Support/Caching.cpp
M llvm/unittests/Support/InstructionCostTest.cpp
M llvm/unittests/Target/DirectX/UniqueResourceFromUseTests.cpp
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
M llvm/unittests/TargetParser/TripleTest.cpp
M llvm/utils/TableGen/Basic/DirectiveEmitter.cpp
M llvm/utils/TableGen/CallingConvEmitter.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/TableGen/DecoderEmitter.cpp
M llvm/utils/TableGen/GlobalISelEmitter.cpp
M llvm/utils/TableGen/SearchableTableEmitter.cpp
M llvm/utils/UpdateTestChecks/common.py
M llvm/utils/gn/secondary/clang/lib/Sema/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Plugins/SymbolFile/DWARF/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ProfileData/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/AArch64/Disassembler/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Support/BUILD.gn
M llvm/utils/vim/syntax/llvm.vim
M mlir/include/mlir/Analysis/SliceAnalysis.h
M mlir/include/mlir/Conversion/GPUCommon/GPUCommonPass.h
M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
M mlir/include/mlir/Dialect/Arith/Utils/Utils.h
M mlir/include/mlir/Dialect/Complex/IR/ComplexOps.td
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/include/mlir/Dialect/GPU/Transforms/Passes.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMDialect.h
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td
M mlir/include/mlir/Dialect/MemRef/Transforms/Passes.h
M mlir/include/mlir/Dialect/MemRef/Transforms/Passes.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrAttrDefs.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrAttrs.h
M mlir/include/mlir/Dialect/Ptr/IR/PtrEnums.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrOps.h
M mlir/include/mlir/Dialect/Ptr/IR/PtrOps.td
M mlir/include/mlir/Dialect/SMT/IR/SMTAttributes.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaUtilOps.td
M mlir/include/mlir/Dialect/Vector/TransformOps/VectorTransformOps.td
M mlir/include/mlir/Dialect/Vector/Transforms/VectorRewritePatterns.h
M mlir/include/mlir/Dialect/X86Vector/X86Vector.td
M mlir/include/mlir/Dialect/X86Vector/X86VectorDialect.h
M mlir/include/mlir/Dialect/X86Vector/X86VectorInterfaces.td
M mlir/include/mlir/ExecutionEngine/SparseTensor/MapRef.h
M mlir/include/mlir/ExecutionEngine/SparseTensorRuntime.h
M mlir/include/mlir/IR/Builders.h
M mlir/include/mlir/IR/BuiltinAttributes.h
M mlir/include/mlir/IR/BuiltinAttributes.td
M mlir/include/mlir/Pass/PassManager.h
M mlir/include/mlir/Reducer/Tester.h
M mlir/include/mlir/TableGen/AttrOrTypeDef.h
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/include/mlir/Transforms/GreedyPatternRewriteDriver.h
M mlir/include/mlir/Transforms/Passes.td
M mlir/lib/Conversion/FuncToLLVM/FuncToLLVM.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Conversion/TosaToMLProgram/TosaToMLProgram.cpp
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/lib/Dialect/Affine/TransformOps/AffineTransformOps.cpp
M mlir/lib/Dialect/Affine/Transforms/AffineDataCopyGeneration.cpp
M mlir/lib/Dialect/Affine/Transforms/SimplifyAffineStructures.cpp
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/lib/Dialect/Affine/Utils/Utils.cpp
M mlir/lib/Dialect/Arith/Transforms/IntRangeOptimizations.cpp
M mlir/lib/Dialect/Arith/Utils/Utils.cpp
M mlir/lib/Dialect/Bufferization/Pipelines/BufferizationPipelines.cpp
M mlir/lib/Dialect/Bufferization/Transforms/BufferDeallocationSimplification.cpp
M mlir/lib/Dialect/GPU/CMakeLists.txt
M mlir/lib/Dialect/GPU/Transforms/SubgroupReduceLowering.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandRealloc.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
M mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/NormalizeMemRefs.cpp
M mlir/lib/Dialect/MemRef/Transforms/ResolveShapedTypeResultDims.cpp
M mlir/lib/Dialect/Ptr/IR/CMakeLists.txt
M mlir/lib/Dialect/Ptr/IR/PtrAttrs.cpp
M mlir/lib/Dialect/Ptr/IR/PtrDialect.cpp
M mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp
M mlir/lib/Dialect/SMT/IR/SMTAttributes.cpp
M mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/lib/Dialect/Transform/IR/TransformOps.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/TransformOps/VectorTransformOps.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp
M mlir/lib/Dialect/X86Vector/IR/CMakeLists.txt
M mlir/lib/Dialect/X86Vector/IR/X86VectorDialect.cpp
M mlir/lib/Dialect/X86Vector/Transforms/LegalizeForLLVMExport.cpp
M mlir/lib/ExecutionEngine/CudaRuntimeWrappers.cpp
M mlir/lib/IR/Builders.cpp
M mlir/lib/IR/BuiltinAttributes.cpp
M mlir/lib/Interfaces/ControlFlowInterfaces.cpp
M mlir/lib/Reducer/ReductionTreePass.cpp
M mlir/lib/TableGen/AttrOrTypeDef.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/lib/Target/LLVMIR/Dialect/GPU/SelectObjectAttr.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/lib/Tools/tblgen-lsp-server/TableGenServer.cpp
M mlir/lib/Transforms/Canonicalizer.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-pipeline.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
M mlir/test/Conversion/TosaToMLProgram/tosa-to-mlprogram.mlir
M mlir/test/Dialect/Affine/canonicalize.mlir
M mlir/test/Dialect/Affine/invalid.mlir
M mlir/test/Dialect/EmitC/transforms.mlir
M mlir/test/Dialect/GPU/subgroup-reduce-lowering.mlir
M mlir/test/Dialect/LLVMIR/blockaddress-canonicalize.mlir
M mlir/test/Dialect/LLVMIR/canonicalize.mlir
A mlir/test/Dialect/LLVMIR/indirectbr.mlir
M mlir/test/Dialect/LLVMIR/invalid.mlir
M mlir/test/Dialect/LLVMIR/module-roundtrip.mlir
M mlir/test/Dialect/Linalg/canonicalize.mlir
M mlir/test/Dialect/Linalg/vectorize-tensor-extract.mlir
M mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir
A mlir/test/Dialect/Ptr/canonicalize.mlir
A mlir/test/Dialect/Ptr/ops.mlir
M mlir/test/Dialect/SCF/invalid.mlir
M mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/level_check.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/profile_pro_fp_unsupported.mlir
M mlir/test/Dialect/Tosa/profile_pro_int_unsupported.mlir
M mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
M mlir/test/Dialect/Tosa/variables.mlir
M mlir/test/Dialect/Tosa/verifier.mlir
M mlir/test/Dialect/Vector/canonicalize.mlir
M mlir/test/Dialect/Vector/invalid.mlir
M mlir/test/Dialect/Vector/vector-emulate-narrow-type-unaligned.mlir
M mlir/test/Dialect/Vector/vector-emulate-narrow-type.mlir
M mlir/test/Dialect/Vector/vector-sink-transform.mlir
M mlir/test/Dialect/Vector/vector-sink.mlir
M mlir/test/Dialect/X86Vector/legalize-for-llvm.mlir
M mlir/test/Dialect/X86Vector/roundtrip.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul-mixed-types.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/matmul.mlir
A mlir/test/Integration/GPU/CUDA/concurrent-kernels.mlir
M mlir/test/Target/Cpp/expressions.mlir
M mlir/test/Target/LLVMIR/Import/import-failure.ll
A mlir/test/Target/LLVMIR/Import/indirectbr.ll
M mlir/test/Target/LLVMIR/Import/module-flags.ll
M mlir/test/Target/LLVMIR/gpu.mlir
A mlir/test/Target/LLVMIR/indirectbr.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
M mlir/test/Target/LLVMIR/nvvm/tma_bulk_copy.mlir
M mlir/test/Target/LLVMIR/x86vector.mlir
M mlir/test/lib/Dialect/Affine/TestAffineDataCopy.cpp
M mlir/test/lib/Dialect/GPU/TestGpuRewrite.cpp
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
M mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
A mlir/test/mlir-tblgen/apint-param-error.td
M mlir/test/mlir-translate/import-diagnostics.ll
M mlir/test/python/pass_manager.py
M mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp
M mlir/tools/mlir-tblgen/OmpOpGen.cpp
M mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp
M mlir/tools/mlir-tblgen/TosaUtilsGen.cpp
M mlir/utils/generate-test-checks.py
M offload/DeviceRTL/CMakeLists.txt
M offload/DeviceRTL/src/Kernel.cpp
M offload/DeviceRTL/src/Mapping.cpp
M offload/include/Shared/Environment.h
M offload/liboffload/API/APIDefs.td
M offload/liboffload/API/Common.td
M offload/liboffload/API/Device.td
A offload/liboffload/API/Event.td
A offload/liboffload/API/Kernel.td
A offload/liboffload/API/Memory.td
M offload/liboffload/API/OffloadAPI.td
M offload/liboffload/API/Platform.td
A offload/liboffload/API/Program.td
A offload/liboffload/API/Queue.td
M offload/liboffload/API/README.md
M offload/liboffload/include/OffloadImpl.hpp
M offload/liboffload/include/generated/OffloadAPI.h
M offload/liboffload/include/generated/OffloadEntryPoints.inc
M offload/liboffload/include/generated/OffloadFuncs.inc
M offload/liboffload/include/generated/OffloadImplFuncDecls.inc
M offload/liboffload/include/generated/OffloadPrint.hpp
M offload/liboffload/src/OffloadImpl.cpp
M offload/liboffload/src/OffloadLib.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/test/offloading/ompx_bare.c
M offload/test/offloading/ompx_bare_multi_dim.cpp
M offload/test/tools/offload-tblgen/entry_points.td
M offload/test/tools/offload-tblgen/functions_ranged_param.td
M offload/test/tools/offload-tblgen/print_enum.td
M offload/test/tools/offload-tblgen/print_function.td
M offload/test/tools/offload-tblgen/type_tagged_enum.td
M offload/tools/offload-tblgen/APIGen.cpp
M offload/tools/offload-tblgen/EntryPointGen.cpp
M offload/tools/offload-tblgen/PrintGen.cpp
M offload/tools/offload-tblgen/RecordTypes.hpp
M offload/unittests/OffloadAPI/CMakeLists.txt
M offload/unittests/OffloadAPI/common/Environment.cpp
M offload/unittests/OffloadAPI/common/Environment.hpp
M offload/unittests/OffloadAPI/common/Fixtures.hpp
R offload/unittests/OffloadAPI/device/olGetDevice.cpp
R offload/unittests/OffloadAPI/device/olGetDeviceCount.cpp
M offload/unittests/OffloadAPI/device/olGetDeviceInfo.cpp
M offload/unittests/OffloadAPI/device/olGetDeviceInfoSize.cpp
A offload/unittests/OffloadAPI/device/olIterateDevices.cpp
A offload/unittests/OffloadAPI/device_code/CMakeLists.txt
A offload/unittests/OffloadAPI/device_code/bar.c
A offload/unittests/OffloadAPI/device_code/foo.c
A offload/unittests/OffloadAPI/kernel/olGetKernel.cpp
A offload/unittests/OffloadAPI/kernel/olLaunchKernel.cpp
A offload/unittests/OffloadAPI/memory/olMemAlloc.cpp
A offload/unittests/OffloadAPI/memory/olMemFree.cpp
A offload/unittests/OffloadAPI/memory/olMemcpy.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatform.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatformCount.cpp
M offload/unittests/OffloadAPI/platform/olGetPlatformInfo.cpp
M offload/unittests/OffloadAPI/platform/olGetPlatformInfoSize.cpp
M offload/unittests/OffloadAPI/platform/olPlatformInfo.hpp
A offload/unittests/OffloadAPI/program/olCreateProgram.cpp
A offload/unittests/OffloadAPI/program/olDestroyProgram.cpp
A offload/unittests/OffloadAPI/queue/olCreateQueue.cpp
A offload/unittests/OffloadAPI/queue/olDestroyQueue.cpp
A offload/unittests/OffloadAPI/queue/olWaitQueue.cpp
M openmp/runtime/src/kmp_tasking.cpp
M polly/lib/CodeGen/BlockGenerators.cpp
M polly/lib/CodeGen/CodeGeneration.cpp
M polly/lib/CodeGen/IslExprBuilder.cpp
M polly/lib/CodeGen/IslNodeBuilder.cpp
M polly/lib/CodeGen/LoopGenerators.cpp
M polly/lib/CodeGen/LoopGeneratorsGOMP.cpp
M polly/lib/CodeGen/LoopGeneratorsKMP.cpp
M polly/lib/CodeGen/PerfMonitor.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
A utils/bazel/llvm-project-overlay/libc/test/include/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/plugin_config.bzl
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/python/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.4
[skip ci]
Commit: 605a11bf3e6db99986e60f294a26defed97d7883
https://github.com/llvm/llvm-project/commit/605a11bf3e6db99986e60f294a26defed97d7883
Author: Amir Aupov <amir.aupov at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M .github/CODEOWNERS
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/lib/Core/MCPlusBuilder.cpp
M bolt/lib/Passes/ProfileQualityStats.cpp
M bolt/lib/Profile/DataAggregator.cpp
A bolt/test/X86/profile-quality-reporting-small-binary.s
M bolt/test/X86/profile-quality-reporting.test
M bolt/test/link_fdata.py
M bolt/unittests/Core/MCPlusBuilder.cpp
M clang-tools-extra/clang-doc/BitcodeWriter.cpp
M clang-tools-extra/clang-doc/HTMLGenerator.cpp
M clang-tools-extra/clang-doc/Serialize.cpp
M clang-tools-extra/clangd/IncludeCleaner.cpp
M clang-tools-extra/clangd/InlayHints.cpp
M clang-tools-extra/clangd/InlayHints.h
M clang-tools-extra/clangd/SystemIncludeExtractor.cpp
M clang-tools-extra/clangd/XRefs.cpp
M clang-tools-extra/clangd/unittests/CallHierarchyTests.cpp
M clang-tools-extra/clangd/unittests/InlayHintTests.cpp
M clang-tools-extra/clangd/unittests/XRefsTests.cpp
M clang/bindings/python/clang/cindex.py
A clang/bindings/python/tests/cindex/INPUTS/a.inc
A clang/bindings/python/tests/cindex/INPUTS/b.inc
A clang/bindings/python/tests/cindex/INPUTS/testfile.c
M clang/bindings/python/tests/cindex/test_file.py
M clang/docs/ReleaseNotes.rst
M clang/docs/StandardCPlusPlusModules.rst
M clang/include/clang/AST/Type.h
M clang/include/clang/Basic/AddressSpaces.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/BuiltinHeaders.def
M clang/include/clang/Basic/BuiltinsAArch64.def
M clang/include/clang/Basic/BuiltinsARM.def
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/arm_sme.td
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/Dialect/IR/CIRTypes.td
M clang/include/clang/CIR/Dialect/IR/CIRTypesDetails.h
M clang/include/clang/CIR/MissingFeatures.h
M clang/include/clang/Driver/Distro.h
M clang/include/clang/Driver/Options.td
M clang/include/clang/Frontend/CompilerInstance.h
M clang/include/clang/Lex/DependencyDirectivesScanner.h
M clang/include/clang/Lex/Preprocessor.h
M clang/include/clang/Lex/PreprocessorOptions.h
M clang/include/clang/Parse/ParseHLSLRootSignature.h
M clang/include/clang/Parse/Parser.h
M clang/include/clang/Sema/AnalysisBasedWarnings.h
M clang/include/clang/Sema/ScopeInfo.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/SemaARM.h
M clang/include/clang/Sema/SemaCUDA.h
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningFilesystem.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpState.cpp
M clang/lib/AST/ByteCode/InterpState.h
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/AST/ByteCode/PrimType.h
M clang/lib/AST/Decl.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/ItaniumCXXABI.cpp
M clang/lib/AST/RecordLayoutBuilder.cpp
M clang/lib/AST/Type.cpp
M clang/lib/AST/TypePrinter.cpp
M clang/lib/Basic/DiagnosticIDs.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/AVR.h
M clang/lib/Basic/Targets/DirectX.h
M clang/lib/Basic/Targets/NVPTX.cpp
M clang/lib/Basic/Targets/NVPTX.h
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/Basic/Targets/SystemZ.h
M clang/lib/Basic/Targets/TCE.h
M clang/lib/Basic/Targets/WebAssembly.h
M clang/lib/Basic/Targets/X86.h
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenRecordLayout.h
M clang/lib/CIR/CodeGen/CIRGenStmt.cpp
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.h
M clang/lib/CIR/CodeGen/CIRGenValue.h
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/IR/CIRMemorySlot.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/CodeGen/CGClass.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGDebugInfo.h
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/Targets/ARM.cpp
M clang/lib/CodeGen/Targets/DirectX.cpp
M clang/lib/Driver/Distro.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/SanitizerArgs.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Format/FormatTokenLexer.cpp
M clang/lib/Format/FormatTokenLexer.h
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Frontend/CompilerInstance.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Frontend/HeaderIncludeGen.cpp
M clang/lib/Headers/arm_acle.h
M clang/lib/Index/IndexBody.cpp
M clang/lib/Lex/PPLexerChange.cpp
M clang/lib/Parse/ParseExpr.cpp
M clang/lib/Parse/ParseHLSLRootSignature.cpp
M clang/lib/Parse/Parser.cpp
M clang/lib/Sema/AnalysisBasedWarnings.cpp
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaARM.cpp
M clang/lib/Sema/SemaCUDA.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaObjC.cpp
M clang/lib/Sema/SemaObjCProperty.cpp
M clang/lib/Sema/SemaOpenACCClause.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/Serialization/ModuleManager.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefMemberChecker.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
M clang/test/AST/ByteCode/c.c
M clang/test/AST/ByteCode/cxx11.cpp
M clang/test/AST/ByteCode/cxx20.cpp
M clang/test/AST/ByteCode/cxx23.cpp
M clang/test/AST/ByteCode/cxx26.cpp
A clang/test/AST/ByteCode/i686.cpp
M clang/test/AST/ByteCode/literals.cpp
M clang/test/AST/ByteCode/records.cpp
M clang/test/AST/HLSL/OutArgExpr.hlsl
M clang/test/AST/HLSL/StructuredBuffers-AST.hlsl
M clang/test/AST/HLSL/TypedBuffers-AST.hlsl
M clang/test/AST/ast-dump-recovery.cpp
M clang/test/AST/new-unknown-type.cpp
A clang/test/Analysis/Checkers/WebKit/unchecked-call-arg.cpp
M clang/test/Analysis/Checkers/WebKit/unchecked-members.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-members.cpp
M clang/test/Analysis/Checkers/WebKit/unretained-call-args-arc.mm
M clang/test/Analysis/Checkers/WebKit/unretained-call-args.mm
M clang/test/Analysis/Checkers/WebKit/unretained-local-vars-arc.mm
M clang/test/Analysis/Checkers/WebKit/unretained-local-vars.mm
A clang/test/Analysis/pragma-diag-control.cpp
M clang/test/CIR/CodeGen/binop.cpp
M clang/test/CIR/CodeGen/struct.c
M clang/test/CIR/CodeGen/struct.cpp
M clang/test/CIR/CodeGen/typedef.c
M clang/test/CIR/CodeGen/union.c
M clang/test/CIR/CodeGenOpenACC/data.c
M clang/test/CIR/CodeGenOpenACC/init.c
M clang/test/CIR/CodeGenOpenACC/kernels.c
M clang/test/CIR/CodeGenOpenACC/parallel.c
M clang/test/CIR/CodeGenOpenACC/serial.c
M clang/test/CIR/CodeGenOpenACC/set.c
M clang/test/CIR/CodeGenOpenACC/shutdown.c
A clang/test/CIR/IR/stack-save-restore.cir
M clang/test/CIR/IR/struct.cir
A clang/test/CIR/Lowering/select.cir
A clang/test/CIR/Lowering/stack-save-restore.cir
M clang/test/CodeGen/AArch64/gcs.c
A clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
R clang/test/CodeGen/Inputs/cuda.h
A clang/test/CodeGen/arm-former-microsoft-intrinsics-header-warning.c
A clang/test/CodeGen/arm-former-microsoft-intrinsics.c
A clang/test/CodeGen/arm-interrupt-save-fp-attr-status-regs.c
A clang/test/CodeGen/arm-interrupt-save-fp-attr.c
M clang/test/CodeGen/arm-microsoft-intrinsics.c
A clang/test/CodeGen/arm64-former-microsoft-intrinsics-header-warning.c
A clang/test/CodeGen/arm64-former-microsoft-intrinsics.c
M clang/test/CodeGen/arm64-microsoft-intrinsics.c
M clang/test/CodeGen/avr/avr-inline-asm-constraints.c
M clang/test/CodeGen/avr/avr-unsupported-inline-asm-constraints.c
M clang/test/CodeGen/builtins-arm-microsoft.c
A clang/test/CodeGen/cfi-icall-trap-recover-runtime.c
R clang/test/CodeGen/nvptx-surface.cu
M clang/test/CodeGen/target-data.c
M clang/test/CodeGenCUDA/Inputs/cuda.h
M clang/test/CodeGenCUDA/builtins-sm90.cu
M clang/test/CodeGenCUDA/correctly-rounded-div.cu
A clang/test/CodeGenCUDA/lambda-constexpr-capture.cu
A clang/test/CodeGenCUDA/nvptx-surface.cu
M clang/test/CodeGenCUDA/offloading-entries.cu
M clang/test/CodeGenCUDA/profile-coverage-mapping.cu
M clang/test/CodeGenCUDA/propagate-attributes.cu
A clang/test/CodeGenCUDASPIRV/printf.cu
A clang/test/CodeGenCXX/cfi-vcall-trap-recover-runtime.cpp
R clang/test/CodeGenCXX/debug-info-dtor-implicit-args.cpp
M clang/test/CodeGenCXX/mangle-template.cpp
A clang/test/CodeGenDirectX/unsupported_intrinsic.hlsl
M clang/test/CodeGenHLSL/ArrayAssignable.hlsl
M clang/test/CodeGenHLSL/builtins/AppendStructuredBuffer-elementtype.hlsl
M clang/test/CodeGenHLSL/builtins/ConsumeStructuredBuffer-elementtype.hlsl
M clang/test/CodeGenHLSL/builtins/RWBuffer-subscript.hlsl
M clang/test/CodeGenHLSL/builtins/RWStructuredBuffer-elementtype.hlsl
M clang/test/CodeGenHLSL/builtins/StructuredBuffer-elementtype.hlsl
M clang/test/CodeGenHLSL/builtins/StructuredBuffers-subscripts.hlsl
M clang/test/Driver/Xclangas.s
M clang/test/Driver/cl-options.c
M clang/test/Driver/cxa-atexit.cpp
M clang/test/Driver/fsanitize.c
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Driver/riscv-cpus.c
M clang/test/Driver/sanitizer-ld.c
M clang/test/Format/lit.local.cfg
M clang/test/Headers/Inputs/include/stdint.h
M clang/test/Headers/__clang_hip_cmath.hip
M clang/test/Headers/__clang_hip_math.hip
M clang/test/Headers/ms-intrin.cpp
M clang/test/Misc/target-invalid-cpu-note/riscv.c
A clang/test/Modules/Inputs/PR137102/module.modulemap
A clang/test/Modules/Inputs/PR137102/type_aware_destroying_new_delete.h
M clang/test/Modules/explicit-build.cpp
A clang/test/Modules/type-aware-destroying-new-and-delete-modules.cpp
A clang/test/PCH/Inputs/type_aware_destroying_new_delete.h
A clang/test/PCH/type-aware-destroying-new-and-delete-pch.cpp
M clang/test/Parser/cxx-concepts-requires-clause.cpp
A clang/test/Parser/extern-template-attributes.cpp
A clang/test/Preprocessor/print-header-crash.modulemap
M clang/test/Preprocessor/print-header-json.c
M clang/test/Preprocessor/riscv-target-features.c
A clang/test/Sema/aarch64-sme2p2-instrinsics/acle_sme2p2_fp8_imm.cpp
M clang/test/Sema/arm-interrupt-attr.c
A clang/test/Sema/arm-interrupt-save-fp-attr.c
A clang/test/Sema/implicit-void-ptr-cast.c
M clang/test/SemaCXX/constant-expression-cxx11.cpp
M clang/test/SemaCXX/constant-expression-p2280r4.cpp
M clang/test/SemaCXX/constexpr-vectors-access-elements.cpp
A clang/test/SemaCXX/cxx20-c99-designator.cpp
M clang/test/SemaCXX/decltype.cpp
M clang/test/SemaCXX/windows-Wpadded-bitfield.cpp
M clang/test/SemaOpenACC/compute-construct-async-clause.c
M clang/test/SemaOpenACC/data-construct-async-clause.c
M clang/test/SemaTemplate/address_space-dependent.cpp
M clang/tools/driver/driver.cpp
M clang/tools/libclang/CIndex.cpp
M clang/unittests/AST/AttrTest.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/FormatTestJS.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M clang/unittests/Lex/PPDependencyDirectivesTest.cpp
M clang/unittests/Parse/ParseHLSLRootSignatureTest.cpp
M clang/unittests/libclang/LibclangTest.cpp
M clang/utils/TableGen/ClangAttrEmitter.cpp
M clang/utils/TableGen/NeonEmitter.cpp
M compiler-rt/lib/asan/asan_report.cpp
M compiler-rt/test/profile/AIX/pgo-lto-bcdtor-function-section.test
A compiler-rt/test/tsan/stack_race3.cpp
M compiler-rt/test/ubsan_minimal/CMakeLists.txt
M compiler-rt/test/ubsan_minimal/lit.common.cfg.py
M compiler-rt/test/ubsan_minimal/lit.site.cfg.py.in
M flang-rt/lib/cuda/allocator.cpp
M flang-rt/unittests/Runtime/CUDA/Allocatable.cpp
M flang/CMakeLists.txt
A flang/docs/FortranStandardsSupport.md
A flang/docs/OpenMPSupport.md
M flang/docs/index.md
M flang/examples/FeatureList/FeatureList.cpp
M flang/include/flang/Lower/DirectivesCommon.h
M flang/include/flang/Optimizer/Builder/DirectivesCommon.h
M flang/include/flang/Optimizer/Dialect/CUF/CUFOps.td
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Semantics/symbol.h
M flang/include/flang/Support/Fortran.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
M flang/lib/Optimizer/CodeGen/LowerRepackArrays.cpp
M flang/lib/Optimizer/CodeGen/TargetRewrite.cpp
M flang/lib/Optimizer/Dialect/CUF/CUFOps.cpp
M flang/lib/Optimizer/Dialect/CUF/CUFToLLVMIRTranslation.cpp
M flang/lib/Optimizer/HLFIR/Transforms/InlineElementals.cpp
M flang/lib/Optimizer/HLFIR/Transforms/InlineHLFIRAssign.cpp
M flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
M flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
M flang/lib/Optimizer/OpenACC/FIROpenACCTypeInterfaces.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/AssumedRankOpConversion.cpp
M flang/lib/Optimizer/Transforms/CUFGPUToLLVMConversion.cpp
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/lib/Optimizer/Transforms/ConstantArgumentGlobalisation.cpp
M flang/lib/Optimizer/Transforms/SimplifyFIROperations.cpp
M flang/lib/Optimizer/Transforms/StackArrays.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-acc-structure.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/rewrite-directives.cpp
A flang/test/Analysis/AliasAnalysis/alias-analysis-pack-array.fir
A flang/test/Driver/m32-option.f90
M flang/test/Fir/CUDA/cuda-gpu-launch-func.mlir
M flang/test/Fir/CUDA/cuda-launch.fir
M flang/test/Fir/CUDA/cuda-target-rewrite.mlir
M flang/test/Fir/OpenACC/openacc-mappable.fir
M flang/test/Lower/CUDA/cuda-kernel-loop-directive.cuf
M flang/test/Lower/OpenACC/acc-bounds.f90
M flang/test/Lower/OpenACC/acc-enter-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-enter-data.f90
A flang/test/Parser/OpenMP/cancel.f90
M flang/test/Semantics/OpenACC/acc-data.f90
M flang/test/Semantics/OpenACC/acc-kernels.f90
M flang/test/Semantics/OpenACC/acc-parallel.f90
M flang/test/Semantics/OpenACC/acc-serial.f90
M flang/test/Semantics/OpenMP/atomic-hint-clause.f90
M flang/test/Semantics/OpenMP/critical-hint-clause.f90
M libc/fuzzing/__support/CMakeLists.txt
R libc/fuzzing/__support/fake_heap.s
M libc/fuzzing/__support/freelist_heap_fuzz.cpp
M libc/src/math/generic/expm1f.cpp
M libc/src/stdio/printf_core/core_structs.h
M libc/test/src/__support/CMakeLists.txt
R libc/test/src/__support/fake_heap.s
M libc/test/src/__support/freelist_heap_test.cpp
R libc/test/src/math/performance_testing/BinaryOpSingleOutputPerf.h
M libc/test/src/math/performance_testing/CMakeLists.txt
A libc/test/src/math/performance_testing/PerfTest.h
R libc/test/src/math/performance_testing/SingleInputSingleOutputPerf.h
M libc/test/src/math/performance_testing/ceilf_perf.cpp
M libc/test/src/math/performance_testing/cosf_perf.cpp
M libc/test/src/math/performance_testing/exp10f16_perf.cpp
M libc/test/src/math/performance_testing/exp2f16_perf.cpp
M libc/test/src/math/performance_testing/exp2f_perf.cpp
M libc/test/src/math/performance_testing/expf16_perf.cpp
M libc/test/src/math/performance_testing/expf_perf.cpp
M libc/test/src/math/performance_testing/expm1f_perf.cpp
M libc/test/src/math/performance_testing/fabsf_perf.cpp
M libc/test/src/math/performance_testing/floorf_perf.cpp
M libc/test/src/math/performance_testing/fmod_perf.cpp
M libc/test/src/math/performance_testing/fmodf128_perf.cpp
M libc/test/src/math/performance_testing/fmodf16_perf.cpp
M libc/test/src/math/performance_testing/fmodf_perf.cpp
M libc/test/src/math/performance_testing/fmodl_perf.cpp
M libc/test/src/math/performance_testing/fmul_perf.cpp
M libc/test/src/math/performance_testing/fmull_perf.cpp
M libc/test/src/math/performance_testing/hypot_perf.cpp
M libc/test/src/math/performance_testing/hypotf16_perf.cpp
M libc/test/src/math/performance_testing/hypotf_perf.cpp
M libc/test/src/math/performance_testing/log10f_perf.cpp
M libc/test/src/math/performance_testing/log1pf_perf.cpp
M libc/test/src/math/performance_testing/log2f_perf.cpp
M libc/test/src/math/performance_testing/logbf_perf.cpp
M libc/test/src/math/performance_testing/logf_perf.cpp
M libc/test/src/math/performance_testing/max_min_funcs_perf.cpp
M libc/test/src/math/performance_testing/misc_basic_ops_perf.cpp
M libc/test/src/math/performance_testing/nearbyintf_perf.cpp
M libc/test/src/math/performance_testing/nearest_integer_funcs_perf.cpp
M libc/test/src/math/performance_testing/rintf_perf.cpp
M libc/test/src/math/performance_testing/roundf_perf.cpp
M libc/test/src/math/performance_testing/sinf_perf.cpp
M libc/test/src/math/performance_testing/sqrtf128_perf.cpp
M libc/test/src/math/performance_testing/sqrtf_perf.cpp
M libc/test/src/math/performance_testing/truncf_perf.cpp
M libclc/CMakeLists.txt
R libclc/amdgpu/lib/SOURCES_3.9
R libclc/amdgpu/lib/SOURCES_4.0
R libclc/amdgpu/lib/SOURCES_5.0
R libclc/amdgpu/lib/shared/vload_half_helpers.ll
R libclc/amdgpu/lib/shared/vstore_half_helpers.ll
M libclc/cmake/modules/AddLibclc.cmake
M libclc/generic/include/clc/clc.h
R libclc/generic/include/clc/clcmacros.h
M libclc/generic/include/clc/image/image.h
M libclc/generic/include/clc/shared/vload.h
M libclc/generic/include/clc/shared/vstore.h
M libclc/generic/lib/shared/vload.cl
M libclc/generic/lib/shared/vload_half.inc
M libclc/generic/lib/shared/vstore.cl
M libclc/generic/lib/shared/vstore_half.inc
R libclc/ptx/lib/SOURCES_3.9
R libclc/ptx/lib/SOURCES_4.0
R libclc/ptx/lib/SOURCES_5.0
R libclc/ptx/lib/shared/vload_half_helpers.ll
R libclc/ptx/lib/shared/vstore_half_helpers.ll
M libcxx/include/__ranges/to.h
M libcxx/include/__tree
M libcxx/test/libcxx/ranges/range.utility/range.utility.conv/to.static_assert.verify.cpp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array.pass.cpp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete.pass.cpp
M libcxxabi/test/test_demangle.pass.cpp
M lld/ELF/ICF.cpp
M lld/ELF/SymbolTable.cpp
M lld/ELF/SymbolTable.h
A lld/test/ELF/aarch64-got-merging-icf.s
M lld/test/ELF/icf-preemptible.s
M lldb/docs/resources/build.rst
M lldb/include/lldb/API/SBExecutionContext.h
M lldb/include/lldb/API/SBInstructionList.h
M lldb/include/lldb/Core/Debugger.h
M lldb/include/lldb/Core/FormatEntity.h
M lldb/include/lldb/Core/IOHandler.h
M lldb/include/lldb/Host/Config.h.cmake
M lldb/include/lldb/Host/Editline.h
M lldb/include/lldb/Interpreter/CommandInterpreter.h
M lldb/include/lldb/Interpreter/CommandObject.h
M lldb/include/lldb/Interpreter/OptionValueEnumeration.h
M lldb/include/lldb/Symbol/CompilerType.h
M lldb/include/lldb/Symbol/TypeSystem.h
M lldb/include/lldb/Target/Statistics.h
M lldb/include/lldb/Utility/CompletionRequest.h
M lldb/packages/Python/lldbsuite/test/lldbtest.py
M lldb/source/API/SBCommandInterpreter.cpp
M lldb/source/API/SBInstructionList.cpp
M lldb/source/Commands/CommandCompletions.cpp
M lldb/source/Commands/CommandObjectProcess.cpp
M lldb/source/Commands/Options.td
M lldb/source/Core/CoreProperties.td
M lldb/source/Core/DataFileCache.cpp
M lldb/source/Core/Debugger.cpp
M lldb/source/Core/FormatEntity.cpp
M lldb/source/Core/IOHandler.cpp
M lldb/source/Host/common/Editline.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Interpreter/OptionValueEnumeration.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangModulesDeclVendor.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxInitializerList.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxSpan.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxVariant.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxVector.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCTypeEncodingParser.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCTypeEncodingParser.h
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/Process/Utility/CMakeLists.txt
A lldb/source/Plugins/Process/Utility/RegisterContextDarwin_riscv32.cpp
A lldb/source/Plugins/Process/Utility/RegisterContextDarwin_riscv32.h
M lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.h
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
M lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp
M lldb/source/Plugins/SymbolFile/DWARF/CMakeLists.txt
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.h
A lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndexSet.cpp
A lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndexSet.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/Plugins/UnwindAssembly/x86/UnwindAssembly-x86.cpp
M lldb/source/Symbol/DWARFCallFrameInfo.cpp
M lldb/source/Symbol/Symtab.cpp
M lldb/source/Symbol/UnwindPlan.cpp
M lldb/source/Target/Statistics.cpp
M lldb/source/Target/Target.cpp
M lldb/source/Utility/ArchSpec.cpp
M lldb/test/API/commands/expression/completion/TestExprCompletion.py
A lldb/test/API/commands/process/reverse-continue/Makefile
A lldb/test/API/commands/process/reverse-continue/TestReverseContinue.py
A lldb/test/API/commands/process/reverse-continue/TestReverseContinueNotSupported.py
A lldb/test/API/commands/process/reverse-continue/main.c
M lldb/test/API/commands/settings/TestSettings.py
M lldb/test/API/commands/statistics/basic/TestStats.py
M lldb/test/API/functionalities/statusline/TestStatusline.py
A lldb/test/API/macosx/riscv32-corefile/Makefile
A lldb/test/API/macosx/riscv32-corefile/TestRV32MachOCorefile.py
A lldb/test/API/macosx/riscv32-corefile/create-empty-riscv-corefile.cpp
M lldb/test/API/terminal/TestEditline.py
R lldb/test/Shell/SymbolFile/DWARF/range-lower-then-low-pc.s
M lldb/test/Shell/SymbolFile/DWARF/x86/discontinuous-inline-function.s
M lldb/test/Shell/Unwind/Inputs/eh-frame-small-fde.s
M lldb/test/Shell/Unwind/eh-frame-small-fde.test
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/Handler/BreakpointLocationsHandler.cpp
M lldb/tools/lldb-dap/Handler/CancelRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/DisconnectRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/NextRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
M lldb/tools/lldb-dap/Handler/SourceRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/StepInRequestHandler.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolBase.h
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
M lldb/tools/lldb-dap/Transport.cpp
M lldb/unittests/Symbol/UnwindPlanTest.cpp
M lldb/unittests/SymbolFile/DWARF/DWARFIndexCachingTest.cpp
M lldb/unittests/Utility/ArchSpecTest.cpp
M llvm/CMakeLists.txt
M llvm/cmake/modules/AddLLVM.cmake
M llvm/docs/GitHub.rst
M llvm/docs/HowToUpdateDebugInfo.rst
M llvm/docs/InterfaceExportAnnotations.rst
M llvm/docs/LangRef.rst
M llvm/docs/NVPTXUsage.rst
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/docs/ResponseGuide.rst
M llvm/docs/SPIRVUsage.rst
M llvm/docs/TableGen/BackGuide.rst
M llvm/include/llvm/Analysis/CmpInstAnalysis.h
M llvm/include/llvm/Analysis/DXILResource.h
M llvm/include/llvm/Analysis/LazyBlockFrequencyInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/BinaryFormat/MachO.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/MachinePipeliner.h
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/Frontend/Directive/DirectiveBase.td
M llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h
M llvm/include/llvm/Frontend/OpenACC/ACC.td
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/Frontend/OpenMP/OMPDeviceConstants.h
M llvm/include/llvm/IR/DebugLoc.h
M llvm/include/llvm/IR/DiagnosticInfo.h
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/include/llvm/IR/IntrinsicsARM.td
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/IntrinsicsPowerPC.td
M llvm/include/llvm/IR/RuntimeLibcalls.def
M llvm/include/llvm/IR/Value.h
M llvm/include/llvm/InitializePasses.h
A llvm/include/llvm/ProfileData/IndexedMemProfData.h
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/include/llvm/Support/Caching.h
M llvm/include/llvm/Support/Compiler.h
M llvm/include/llvm/Support/InstructionCost.h
M llvm/include/llvm/Support/NVPTXAddrSpace.h
M llvm/include/llvm/TableGen/DirectiveEmitter.h
M llvm/include/llvm/TableGen/Record.h
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/include/llvm/Transforms/Utils/UnrollLoop.h
M llvm/lib/Analysis/AliasAnalysis.cpp
M llvm/lib/Analysis/Analysis.cpp
M llvm/lib/Analysis/AssumptionCache.cpp
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/BlockFrequencyInfo.cpp
M llvm/lib/Analysis/BranchProbabilityInfo.cpp
M llvm/lib/Analysis/CallGraph.cpp
M llvm/lib/Analysis/CmpInstAnalysis.cpp
M llvm/lib/Analysis/CostModel.cpp
M llvm/lib/Analysis/CtxProfAnalysis.cpp
M llvm/lib/Analysis/CycleAnalysis.cpp
M llvm/lib/Analysis/DXILMetadataAnalysis.cpp
M llvm/lib/Analysis/DXILResource.cpp
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/lib/Analysis/DomPrinter.cpp
M llvm/lib/Analysis/DominanceFrontier.cpp
M llvm/lib/Analysis/GlobalsModRef.cpp
M llvm/lib/Analysis/IRSimilarityIdentifier.cpp
M llvm/lib/Analysis/IVUsers.cpp
M llvm/lib/Analysis/InlineSizeEstimatorAnalysis.cpp
M llvm/lib/Analysis/LazyBlockFrequencyInfo.cpp
M llvm/lib/Analysis/LazyValueInfo.cpp
M llvm/lib/Analysis/LoopInfo.cpp
M llvm/lib/Analysis/LoopPass.cpp
M llvm/lib/Analysis/MemoryDependenceAnalysis.cpp
M llvm/lib/Analysis/MemorySSA.cpp
M llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
M llvm/lib/Analysis/OptimizationRemarkEmitter.cpp
M llvm/lib/Analysis/PhiValues.cpp
M llvm/lib/Analysis/PostDominators.cpp
M llvm/lib/Analysis/ProfileSummaryInfo.cpp
M llvm/lib/Analysis/RegionInfo.cpp
M llvm/lib/Analysis/RegionPrinter.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp
M llvm/lib/Analysis/ScopedNoAliasAA.cpp
M llvm/lib/Analysis/StackSafetyAnalysis.cpp
M llvm/lib/Analysis/StaticDataProfileInfo.cpp
M llvm/lib/Analysis/TargetLibraryInfo.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/TypeBasedAliasAnalysis.cpp
M llvm/lib/Analysis/UniformityAnalysis.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CGData/CodeGenData.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/CodeGen/LiveRangeShrink.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/PrologEpilogInserter.cpp
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/SplitKit.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/Debuginfod/Debuginfod.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/DebugLoc.cpp
M llvm/lib/IR/DiagnosticInfo.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/ProfDataUtils.cpp
M llvm/lib/IR/Value.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/LTO/LTOBackend.cpp
M llvm/lib/MC/MCParser/MasmParser.cpp
M llvm/lib/ProfileData/CMakeLists.txt
A llvm/lib/ProfileData/IndexedMemProfData.cpp
M llvm/lib/ProfileData/InstrProf.cpp
M llvm/lib/ProfileData/InstrProfReader.cpp
M llvm/lib/ProfileData/InstrProfWriter.cpp
M llvm/lib/Support/Caching.cpp
M llvm/lib/Support/SuffixTree.cpp
M llvm/lib/TableGen/DetailedRecordsBackend.cpp
M llvm/lib/TableGen/JSONBackend.cpp
M llvm/lib/TableGen/Record.cpp
M llvm/lib/TableGen/SetTheory.cpp
M llvm/lib/TableGen/TGParser.cpp
M llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrAtomics.td
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrGISel.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AArch64/CMakeLists.txt
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
M llvm/lib/Target/ARM/ARMCallingConv.td
M llvm/lib/Target/ARM/ARMFrameLowering.cpp
M llvm/lib/Target/ARM/ARMFrameLowering.h
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMInstrVFP.td
M llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
M llvm/lib/Target/ARM/ARMRegisterInfo.td
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/BPF/BPFISelLowering.h
M llvm/lib/Target/BPF/BPFInstrInfo.td
M llvm/lib/Target/BPF/BPFTargetTransformInfo.h
M llvm/lib/Target/DirectX/CMakeLists.txt
A llvm/lib/Target/DirectX/DXILForwardHandleAccesses.cpp
A llvm/lib/Target/DirectX/DXILForwardHandleAccesses.h
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/lib/Target/DirectX/DXILResourceAccess.cpp
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/DirectX/DirectX.h
M llvm/lib/Target/DirectX/DirectXPassRegistry.def
M llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.h
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.h
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
M llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.cpp
M llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h
M llvm/lib/Target/Mips/MipsTargetTransformInfo.cpp
M llvm/lib/Target/Mips/MipsTargetTransformInfo.h
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTX.h
M llvm/lib/Target/NVPTX/NVPTXAliasAnalysis.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp
M llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/NVPTX/NVPTXUtilities.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.h
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
M llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVSystemOperands.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
M llvm/lib/Target/SPIRV/SPIRVTargetTransformInfo.h
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/Sparc/SparcInstrVIS.td
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.h
M llvm/lib/Target/SystemZ/SystemZInstrFP.td
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
M llvm/lib/Target/VE/VETargetTransformInfo.h
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
M llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86LowerTileCopy.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/lib/Transforms/Coroutines/CoroElide.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/IPO/FunctionAttrs.cpp
M llvm/lib/Transforms/IPO/FunctionSpecialization.cpp
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/IPO/PartialInlining.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Instrumentation/SanitizerBinaryMetadata.cpp
M llvm/lib/Transforms/Instrumentation/ThreadSanitizer.cpp
M llvm/lib/Transforms/Scalar/ConstantHoisting.cpp
M llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
M llvm/lib/Transforms/Scalar/LoopDataPrefetch.cpp
M llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
M llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
M llvm/lib/Transforms/Scalar/NewGVN.cpp
M llvm/lib/Transforms/Scalar/Reassociate.cpp
M llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
M llvm/lib/Transforms/Utils/Debugify.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/MisExpect.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/runtimes/CMakeLists.txt
M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
M llvm/test/Analysis/CostModel/AArch64/vector-select.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-fadd.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-exact-vlen.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-permute.ll
M llvm/test/Analysis/CtxProfAnalysis/flatten-and-annotate.ll
M llvm/test/Analysis/CtxProfAnalysis/flatten-check-path.ll
M llvm/test/Analysis/CtxProfAnalysis/flatten-insert-icp-mdprof.ll
M llvm/test/Analysis/CtxProfAnalysis/flatten-zero-path.ll
M llvm/test/Analysis/CtxProfAnalysis/full-cycle.ll
M llvm/test/Analysis/CtxProfAnalysis/inline.ll
M llvm/test/Analysis/CtxProfAnalysis/load.ll
M llvm/test/Analysis/DXILResource/buffer-frombinding.ll
M llvm/test/Assembler/auto_upgrade_nvvm_intrinsics.ll
A llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/lower-neon-vector-fcmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-const-vector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vector-fcmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-shift-imm.mir
M llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll
M llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll
M llvm/test/CodeGen/AArch64/arm64-tbl.ll
M llvm/test/CodeGen/AArch64/arm64-zip.ll
M llvm/test/CodeGen/AArch64/fsh.ll
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/optimize-cond-branch.ll
M llvm/test/CodeGen/AArch64/select_cc.ll
A llvm/test/CodeGen/AArch64/sme2-intrinsics-mop4-fp8.ll
M llvm/test/CodeGen/AArch64/sve-extract-element.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/sve-varargs-caller-broken.ll
M llvm/test/CodeGen/AArch64/sve-varargs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
M llvm/test/CodeGen/AMDGPU/add64-low-32-bits-known-zero.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast.gfx6.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
M llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/cc-update.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
M llvm/test/CodeGen/AMDGPU/constrained-shift.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/dead-machine-elim-after-dead-lane.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
A llvm/test/CodeGen/AMDGPU/do-not-fold-copy.mir
M llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs-r600.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx942.ll
M llvm/test/CodeGen/AMDGPU/fpext-free.ll
M llvm/test/CodeGen/AMDGPU/fpow.ll
R llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.fpmath.ll
A llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.path.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/function-args.ll
M llvm/test/CodeGen/AMDGPU/function-returns.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-store.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernel-argument-alignment.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
A llvm/test/CodeGen/AMDGPU/insert-waitcnts-gfx12-wbinv.mir
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.wave32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.AFLCustomIRMutator.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/lower-kernargs.ll
M llvm/test/CodeGen/AMDGPU/lrint.ll
M llvm/test/CodeGen/AMDGPU/lround.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll
M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/ptrmask.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/sdag-print-divergence.ll
M llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
A llvm/test/CodeGen/AMDGPU/si-instr-info-vopc-exec.mir
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/strict_fpext.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub64-low-32-bits-known-zero.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
A llvm/test/CodeGen/AMDGPU/uniform-vgpr-to-sgpr-return.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
M llvm/test/CodeGen/AMDGPU/vector_rebroadcast.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
M llvm/test/CodeGen/AMDGPU/vopc_dpp.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-global-inv-wb.mir
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
A llvm/test/CodeGen/ARM/interrupt-save-fp-attr-status-regs.mir
A llvm/test/CodeGen/ARM/interrupt-save-fp-attr.ll
M llvm/test/CodeGen/ARM/popcnt.ll
M llvm/test/CodeGen/AVR/inline-asm/inline-asm-invalid.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/alloca.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/ambiguous.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/buffer-O0.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/cbuffer-access.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/undominated.ll
M llvm/test/CodeGen/DirectX/ResourceAccess/load_typedbuffer.ll
A llvm/test/CodeGen/DirectX/ShaderFlags/max-64-uavs-array-sm6_5.ll
A llvm/test/CodeGen/DirectX/ShaderFlags/max-64-uavs-array-sm6_6.ll
A llvm/test/CodeGen/DirectX/ShaderFlags/max-64-uavs.ll
A llvm/test/CodeGen/DirectX/legalize-lifetimes.ll
M llvm/test/CodeGen/DirectX/llc-pipeline.ll
M llvm/test/CodeGen/DirectX/unsupported_intrinsic.ll
A llvm/test/CodeGen/Hexagon/swp-alias-cross-iteration.mir
M llvm/test/CodeGen/Hexagon/swp-epilog-phi11.ll
M llvm/test/CodeGen/Hexagon/swp-epilog-phi12.ll
M llvm/test/CodeGen/Hexagon/swp-epilog-phi13.ll
M llvm/test/CodeGen/Hexagon/swp-epilog-phi6.ll
M llvm/test/CodeGen/Hexagon/swp-epilog-phi9.ll
A llvm/test/CodeGen/Hexagon/swp-no-alias.mir
M llvm/test/CodeGen/LoongArch/lasx/broadcast-load.ll
A llvm/test/CodeGen/LoongArch/lasx/widen-shuffle-mask.ll
M llvm/test/CodeGen/LoongArch/lsx/broadcast-load.ll
A llvm/test/CodeGen/LoongArch/lsx/widen-shuffle-mask.ll
M llvm/test/CodeGen/NVPTX/LoadStoreVectorizer.ll
A llvm/test/CodeGen/NVPTX/addrspacecast-ptx64.ll
M llvm/test/CodeGen/NVPTX/and-or-setcc.ll
M llvm/test/CodeGen/NVPTX/atomics.ll
M llvm/test/CodeGen/NVPTX/bf16-instructions.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions-approx.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/bug21465.ll
M llvm/test/CodeGen/NVPTX/convert-fp-i8.ll
M llvm/test/CodeGen/NVPTX/convert-sm100.ll
M llvm/test/CodeGen/NVPTX/convert-sm100a.ll
M llvm/test/CodeGen/NVPTX/convert-sm80.ll
M llvm/test/CodeGen/NVPTX/convert-sm90.ll
M llvm/test/CodeGen/NVPTX/copysign.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk.ll
A llvm/test/CodeGen/NVPTX/distributed-shared-cluster.ll
M llvm/test/CodeGen/NVPTX/div.ll
M llvm/test/CodeGen/NVPTX/f16-abs.ll
M llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/f32-ex2.ll
M llvm/test/CodeGen/NVPTX/f32-lg2.ll
M llvm/test/CodeGen/NVPTX/fabs-intrinsics.ll
M llvm/test/CodeGen/NVPTX/fexp2.ll
M llvm/test/CodeGen/NVPTX/flog2.ll
M llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
M llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll
M llvm/test/CodeGen/NVPTX/fma-relu-instruction-flag.ll
M llvm/test/CodeGen/NVPTX/forward-ld-param.ll
M llvm/test/CodeGen/NVPTX/fp-contract.ll
M llvm/test/CodeGen/NVPTX/fp128-storage-type.ll
M llvm/test/CodeGen/NVPTX/frem.ll
M llvm/test/CodeGen/NVPTX/i128-array.ll
M llvm/test/CodeGen/NVPTX/i128-retval.ll
M llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test1.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test3.ll
M llvm/test/CodeGen/NVPTX/intrinsics.ll
M llvm/test/CodeGen/NVPTX/ldg-invariant.ll
M llvm/test/CodeGen/NVPTX/ldu-ldg.ll
M llvm/test/CodeGen/NVPTX/load-store-scalars.ll
M llvm/test/CodeGen/NVPTX/load-store-vectors.ll
M llvm/test/CodeGen/NVPTX/load-with-non-coherent-cache.ll
M llvm/test/CodeGen/NVPTX/lower-args-gridconstant.ll
M llvm/test/CodeGen/NVPTX/lower-args.ll
M llvm/test/CodeGen/NVPTX/lower-byval-args.ll
M llvm/test/CodeGen/NVPTX/math-intrins.ll
M llvm/test/CodeGen/NVPTX/misched_func_call.ll
M llvm/test/CodeGen/NVPTX/nvptx-aa.ll
M llvm/test/CodeGen/NVPTX/param-add.ll
M llvm/test/CodeGen/NVPTX/rcp-opt.ll
A llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
M llvm/test/CodeGen/NVPTX/redux-sync-f32.ll
M llvm/test/CodeGen/NVPTX/reg-types.ll
M llvm/test/CodeGen/NVPTX/st-param-imm.ll
M llvm/test/CodeGen/NVPTX/surf-read-cuda.ll
M llvm/test/CodeGen/NVPTX/tex-read-cuda.ll
M llvm/test/CodeGen/NVPTX/variadics-backend.ll
M llvm/test/CodeGen/PowerPC/dmf-outer-product.ll
M llvm/test/CodeGen/PowerPC/dmr-enable.ll
M llvm/test/CodeGen/PowerPC/undef-args.ll
M llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
A llvm/test/CodeGen/PowerPC/vsx-fma-m-early.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
A llvm/test/CodeGen/RISCV/atomic-load-zext.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
A llvm/test/CodeGen/RISCV/di-assignment-tracking-vector.ll
M llvm/test/CodeGen/RISCV/features-info.ll
A llvm/test/CodeGen/RISCV/fold-mem-offset.mir
M llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
A llvm/test/CodeGen/RISCV/pr101786.ll
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvqdotq.ll
M llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
M llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
M llvm/test/CodeGen/RISCV/xqccmp-additional-stack.ll
M llvm/test/CodeGen/RISCV/xqccmp-callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
M llvm/test/CodeGen/RISCV/xqccmp-with-float.ll
A llvm/test/CodeGen/RISCV/xqcia.ll
A llvm/test/CodeGen/RISCV/zalasr-offset-folding.ll
M llvm/test/CodeGen/RISCV/zcmp-additional-stack.ll
M llvm/test/CodeGen/RISCV/zcmp-with-float.ll
M llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
A llvm/test/CodeGen/SPARC/multiply-extension.ll
M llvm/test/CodeGen/SPARC/smulo-128-legalisation-lowering.ll
M llvm/test/CodeGen/SPARC/umulo-128-legalisation-lowering.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroup_matrix_multiply_accumulate/subgroup_matrix_multiply_accumulate_generic.ll
M llvm/test/CodeGen/SPIRV/pointers/getelementptr-downcast-struct.ll
M llvm/test/CodeGen/SPIRV/pointers/getelementptr-downcast-vector.ll
A llvm/test/CodeGen/SPIRV/pointers/store-struct.ll
M llvm/test/CodeGen/SystemZ/fp-abs-01.ll
M llvm/test/CodeGen/SystemZ/fp-abs-02.ll
M llvm/test/CodeGen/SystemZ/fp-abs-03.ll
M llvm/test/CodeGen/SystemZ/fp-abs-04.ll
M llvm/test/CodeGen/SystemZ/fp-copysign-01.ll
M llvm/test/CodeGen/SystemZ/fp-copysign-02.ll
M llvm/test/CodeGen/SystemZ/fp-copysign-03.ll
M llvm/test/CodeGen/SystemZ/fp-mul-08.ll
M llvm/test/CodeGen/SystemZ/fp-mul-10.ll
M llvm/test/CodeGen/SystemZ/fp-neg-01.ll
M llvm/test/CodeGen/SystemZ/fp-neg-02.ll
M llvm/test/CodeGen/Thumb2/mve-ctpop.ll
M llvm/test/CodeGen/VE/Vector/ticket-64420.ll
M llvm/test/CodeGen/X86/avx512-i1test.ll
M llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
M llvm/test/CodeGen/X86/bfloat.ll
M llvm/test/CodeGen/X86/build-vector-128.ll
M llvm/test/CodeGen/X86/build-vector-256.ll
M llvm/test/CodeGen/X86/build-vector-512.ll
A llvm/test/CodeGen/X86/buildvec-widen-dotproduct.ll
M llvm/test/CodeGen/X86/clobber_frame_ptr.ll
M llvm/test/CodeGen/X86/combine-fcopysign.ll
M llvm/test/CodeGen/X86/combine-pmuldq.ll
M llvm/test/CodeGen/X86/concat-fpext-v2bf16.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
M llvm/test/CodeGen/X86/extractelement-load.ll
M llvm/test/CodeGen/X86/ispow2.ll
M llvm/test/CodeGen/X86/jump_sign.ll
M llvm/test/CodeGen/X86/machine-trace-metrics-crash.ll
M llvm/test/CodeGen/X86/masked_store_trunc.ll
M llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll
M llvm/test/CodeGen/X86/masked_store_trunc_usat.ll
M llvm/test/CodeGen/X86/pr40891.ll
M llvm/test/CodeGen/X86/pr50254.ll
M llvm/test/CodeGen/X86/pr57673.ll
M llvm/test/CodeGen/X86/pr63108.ll
M llvm/test/CodeGen/X86/pr91005.ll
A llvm/test/CodeGen/X86/pr94829.ll
M llvm/test/CodeGen/X86/psubus.ll
M llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
M llvm/test/CodeGen/X86/shift-combine.ll
M llvm/test/CodeGen/X86/shuffle-combine-crash.ll
M llvm/test/CodeGen/X86/shuffle-half.ll
M llvm/test/CodeGen/X86/swifterror.ll
M llvm/test/CodeGen/X86/tailcall-cgp-dup.ll
M llvm/test/CodeGen/X86/vaargs-prolog-insert.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
M llvm/test/CodeGen/X86/vector-popcnt-128.ll
M llvm/test/CodeGen/X86/vector-popcnt-256-ult-ugt.ll
M llvm/test/CodeGen/X86/vector-popcnt-256.ll
M llvm/test/CodeGen/X86/vector-popcnt-512-ult-ugt.ll
M llvm/test/CodeGen/X86/vector-popcnt-512.ll
M llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
M llvm/test/CodeGen/X86/vector-trunc-nowrap.ll
M llvm/test/CodeGen/X86/vector-trunc-packus.ll
M llvm/test/CodeGen/X86/vector-trunc-ssat.ll
M llvm/test/CodeGen/X86/vector-trunc-usat.ll
M llvm/test/CodeGen/X86/vector-trunc.ll
M llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
A llvm/test/DebugInfo/AArch64/lexical-block-abstract-origin.ll
M llvm/test/DebugInfo/Generic/inline-scopes.ll
M llvm/test/DebugInfo/NVPTX/debug-info.ll
M llvm/test/DebugInfo/X86/lexical-block-file-inline.ll
M llvm/test/DebugInfo/X86/missing-abstract-variable.ll
A llvm/test/Instrumentation/MemorySanitizer/X86/avx512fp16-arith-intrinsics.ll
A llvm/test/Instrumentation/MemorySanitizer/X86/avx512fp16-arith-vl-intrinsics.ll
A llvm/test/Instrumentation/MemorySanitizer/X86/avx512fp16-intrinsics.ll
M llvm/test/Instrumentation/ThreadSanitizer/capture.ll
M llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
M llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
M llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/test/MC/RISCV/machine-csr-names.s
M llvm/test/MC/RISCV/rv32-machine-csr-names.s
M llvm/test/TableGen/VarLenDecoder.td
M llvm/test/TableGen/trydecode-emission.td
M llvm/test/TableGen/trydecode-emission2.td
M llvm/test/TableGen/trydecode-emission3.td
M llvm/test/TableGen/trydecode-emission4.td
M llvm/test/Transforms/Attributor/issue87856.ll
A llvm/test/Transforms/CodeGenPrepare/unfold-pow2-test-vec.ll
A llvm/test/Transforms/CodeGenPrepare/unfold-pow2-test.ll
M llvm/test/Transforms/CorrelatedValuePropagation/uscmp.ll
M llvm/test/Transforms/FunctionAttrs/initializes.ll
A llvm/test/Transforms/GlobalOpt/X86/preserve-dbgloc-of-load-store-to-bool.ll
A llvm/test/Transforms/GlobalOpt/malloc-promote-atomic.ll
M llvm/test/Transforms/InferAddressSpaces/NVPTX/isspacep.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-binop.ll
A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-shift.ll
M llvm/test/Transforms/InstCombine/and-fcmp.ll
M llvm/test/Transforms/InstCombine/clamp-to-minmax.ll
M llvm/test/Transforms/InstCombine/icmp.ll
A llvm/test/Transforms/InstCombine/max-min-canonicalize.ll
M llvm/test/Transforms/InstCombine/max_known_bits.ll
M llvm/test/Transforms/InstCombine/minmax-fold.ll
M llvm/test/Transforms/InstCombine/minmax-intrinsics.ll
M llvm/test/Transforms/InstCombine/sadd_sat.ll
M llvm/test/Transforms/InstCombine/select-min-max.ll
M llvm/test/Transforms/LoopVectorize/AArch64/blend-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-no-dotprod.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-intrinsic-calls.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/pr51366-sunk-instruction-used-outside-of-loop.ll
M llvm/test/Transforms/LoopVectorize/X86/small-size.ll
M llvm/test/Transforms/LoopVectorize/debugloc.ll
M llvm/test/Transforms/LoopVectorize/dereferenceable-info-from-assumption-constant-size.ll
M llvm/test/Transforms/LoopVectorize/float-induction.ll
M llvm/test/Transforms/LoopVectorize/if-pred-stores.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/load-deref-pred-align.ll
M llvm/test/Transforms/LoopVectorize/load-of-struct-deref-pred.ll
M llvm/test/Transforms/LoopVectorize/loop-form.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/select-cmp-multiuse.ll
M llvm/test/Transforms/LoopVectorize/select-cmp-predicated.ll
M llvm/test/Transforms/LoopVectorize/struct-return.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll
M llvm/test/Transforms/LoopVectorize/trip-count-expansion-may-introduce-ub.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing.ll
M llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll
M llvm/test/Transforms/LowerTypeTests/aarch64-jumptable.ll
M llvm/test/Transforms/LowerTypeTests/cfi-direct-call1.ll
M llvm/test/Transforms/LowerTypeTests/function-arm-thumb.ll
M llvm/test/Transforms/LowerTypeTests/function-thumb-bti.ll
M llvm/test/Transforms/LowerTypeTests/function.ll
M llvm/test/Transforms/LowerTypeTests/x86-jumptable.ll
A llvm/test/Transforms/MemProfContextDisambiguation/mergenodes.ll
A llvm/test/Transforms/MemProfContextDisambiguation/mergenodes2.ll
M llvm/test/Transforms/MemProfContextDisambiguation/overlapping-contexts.ll
M llvm/test/Transforms/MergeFunc/cfi-thunk-merging.ll
A llvm/test/Transforms/PGOProfile/memprof-dump-matched-alloc-site.ll
M llvm/test/Transforms/PGOProfile/memprof-dump-matched-call-sites.ll
M llvm/test/Transforms/PGOProfile/memprof.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/slpordering.ll
M llvm/test/Transforms/PhaseOrdering/X86/blendv-select.ll
A llvm/test/Transforms/Reassociate/canonicalize-made-change.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/loadorder.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/reused-scalar-repeated-in-node.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/transpose-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/transpose.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vectorizable-selects-uniform-cmps.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reductions.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/segmented-loads-simple.ll
M llvm/test/Transforms/SLPVectorizer/X86/full-match-with-poison-scalar.ll
M llvm/test/Transforms/SLPVectorizer/X86/full-matched-bv-with-subvectors.ll
M llvm/test/Transforms/SLPVectorizer/X86/matched-nodes-updated.ll
M llvm/test/Transforms/SLPVectorizer/X86/memory-runtime-checks.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi-extracts-bv-combined.ll
A llvm/test/Transforms/SLPVectorizer/X86/phi-comparator.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduced-val-vectorized-in-transform.ll
M llvm/test/Transforms/SLPVectorizer/X86/reorder-reused-masked-gather.ll
M llvm/test/Transforms/SLPVectorizer/icmp-altopcode-after-reordering.ll
M llvm/test/Transforms/SLPVectorizer/reordering-single-phi.ll
M llvm/test/Transforms/SLPVectorizer/vectorize-reorder-alt-shuffle.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/preserve-inbounds.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep.ll
A llvm/test/Transforms/SimplifyCFG/X86/debugloc-invoke-to-call-br.ll
A llvm/test/Transforms/VectorCombine/pr132563.ll
A llvm/test/Verifier/diassignid-vector-stores.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/nvptx-basic.ll.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/difile_absolute_filenames.ll
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/difile_absolute_filenames.ll.expected
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.globals.expected
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.transitiveglobals.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/difile_absolute_filenames.test
M llvm/test/tools/dsymutil/ARM/stmt-seq-macho.test
A llvm/test/tools/llvm-cov/branch-export-lcov-unify-instances.test
M llvm/test/tools/llvm-cov/branch-export-lcov.test
A llvm/test/tools/llvm-extract/extract-unnamed-bb.ll
M llvm/test/tools/llvm-ml/macro_function.asm
M llvm/tools/gold/gold-plugin.cpp
M llvm/tools/llvm-config/BuildVariables.inc.in
M llvm/tools/llvm-config/CMakeLists.txt
M llvm/tools/llvm-config/llvm-config.cpp
M llvm/tools/llvm-cov/CodeCoverage.cpp
M llvm/tools/llvm-cov/CoverageExporterLcov.cpp
M llvm/tools/llvm-cov/CoverageViewOptions.h
M llvm/tools/llvm-extract/llvm-extract.cpp
M llvm/tools/llvm-lto2/llvm-lto2.cpp
M llvm/tools/llvm-shlib/CMakeLists.txt
M llvm/unittests/Support/CMakeLists.txt
A llvm/unittests/Support/Caching.cpp
M llvm/unittests/Support/InstructionCostTest.cpp
M llvm/unittests/Target/DirectX/UniqueResourceFromUseTests.cpp
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
M llvm/unittests/TargetParser/TripleTest.cpp
M llvm/utils/TableGen/Basic/DirectiveEmitter.cpp
M llvm/utils/TableGen/CallingConvEmitter.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/TableGen/DecoderEmitter.cpp
M llvm/utils/TableGen/GlobalISelEmitter.cpp
M llvm/utils/TableGen/SearchableTableEmitter.cpp
M llvm/utils/UpdateTestChecks/common.py
M llvm/utils/gn/secondary/clang/lib/Sema/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Plugins/SymbolFile/DWARF/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ProfileData/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/AArch64/Disassembler/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Support/BUILD.gn
M llvm/utils/vim/syntax/llvm.vim
M mlir/include/mlir/Analysis/SliceAnalysis.h
M mlir/include/mlir/Conversion/GPUCommon/GPUCommonPass.h
M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
M mlir/include/mlir/Dialect/Arith/Utils/Utils.h
M mlir/include/mlir/Dialect/Complex/IR/ComplexOps.td
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/include/mlir/Dialect/GPU/Transforms/Passes.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMDialect.h
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td
M mlir/include/mlir/Dialect/MemRef/Transforms/Passes.h
M mlir/include/mlir/Dialect/MemRef/Transforms/Passes.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrAttrDefs.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrAttrs.h
M mlir/include/mlir/Dialect/Ptr/IR/PtrEnums.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrOps.h
M mlir/include/mlir/Dialect/Ptr/IR/PtrOps.td
M mlir/include/mlir/Dialect/SMT/IR/SMTAttributes.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaUtilOps.td
M mlir/include/mlir/Dialect/Vector/TransformOps/VectorTransformOps.td
M mlir/include/mlir/Dialect/Vector/Transforms/VectorRewritePatterns.h
M mlir/include/mlir/Dialect/X86Vector/X86Vector.td
M mlir/include/mlir/Dialect/X86Vector/X86VectorDialect.h
M mlir/include/mlir/Dialect/X86Vector/X86VectorInterfaces.td
M mlir/include/mlir/ExecutionEngine/SparseTensor/MapRef.h
M mlir/include/mlir/ExecutionEngine/SparseTensorRuntime.h
M mlir/include/mlir/IR/Builders.h
M mlir/include/mlir/IR/BuiltinAttributes.h
M mlir/include/mlir/IR/BuiltinAttributes.td
M mlir/include/mlir/Pass/PassManager.h
M mlir/include/mlir/Reducer/Tester.h
M mlir/include/mlir/TableGen/AttrOrTypeDef.h
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/include/mlir/Transforms/GreedyPatternRewriteDriver.h
M mlir/include/mlir/Transforms/Passes.td
M mlir/lib/Conversion/FuncToLLVM/FuncToLLVM.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Conversion/TosaToMLProgram/TosaToMLProgram.cpp
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/lib/Dialect/Affine/TransformOps/AffineTransformOps.cpp
M mlir/lib/Dialect/Affine/Transforms/AffineDataCopyGeneration.cpp
M mlir/lib/Dialect/Affine/Transforms/SimplifyAffineStructures.cpp
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/lib/Dialect/Affine/Utils/Utils.cpp
M mlir/lib/Dialect/Arith/Transforms/IntRangeOptimizations.cpp
M mlir/lib/Dialect/Arith/Utils/Utils.cpp
M mlir/lib/Dialect/Bufferization/Pipelines/BufferizationPipelines.cpp
M mlir/lib/Dialect/Bufferization/Transforms/BufferDeallocationSimplification.cpp
M mlir/lib/Dialect/GPU/CMakeLists.txt
M mlir/lib/Dialect/GPU/Transforms/SubgroupReduceLowering.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandRealloc.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
M mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/NormalizeMemRefs.cpp
M mlir/lib/Dialect/MemRef/Transforms/ResolveShapedTypeResultDims.cpp
M mlir/lib/Dialect/Ptr/IR/CMakeLists.txt
M mlir/lib/Dialect/Ptr/IR/PtrAttrs.cpp
M mlir/lib/Dialect/Ptr/IR/PtrDialect.cpp
M mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp
M mlir/lib/Dialect/SMT/IR/SMTAttributes.cpp
M mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/lib/Dialect/Transform/IR/TransformOps.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/TransformOps/VectorTransformOps.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp
M mlir/lib/Dialect/X86Vector/IR/CMakeLists.txt
M mlir/lib/Dialect/X86Vector/IR/X86VectorDialect.cpp
M mlir/lib/Dialect/X86Vector/Transforms/LegalizeForLLVMExport.cpp
M mlir/lib/ExecutionEngine/CudaRuntimeWrappers.cpp
M mlir/lib/IR/Builders.cpp
M mlir/lib/IR/BuiltinAttributes.cpp
M mlir/lib/Interfaces/ControlFlowInterfaces.cpp
M mlir/lib/Reducer/ReductionTreePass.cpp
M mlir/lib/TableGen/AttrOrTypeDef.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/lib/Target/LLVMIR/Dialect/GPU/SelectObjectAttr.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/lib/Tools/tblgen-lsp-server/TableGenServer.cpp
M mlir/lib/Transforms/Canonicalizer.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-pipeline.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
M mlir/test/Conversion/TosaToMLProgram/tosa-to-mlprogram.mlir
M mlir/test/Dialect/Affine/canonicalize.mlir
M mlir/test/Dialect/Affine/invalid.mlir
M mlir/test/Dialect/EmitC/transforms.mlir
M mlir/test/Dialect/GPU/subgroup-reduce-lowering.mlir
M mlir/test/Dialect/LLVMIR/blockaddress-canonicalize.mlir
M mlir/test/Dialect/LLVMIR/canonicalize.mlir
A mlir/test/Dialect/LLVMIR/indirectbr.mlir
M mlir/test/Dialect/LLVMIR/invalid.mlir
M mlir/test/Dialect/LLVMIR/module-roundtrip.mlir
M mlir/test/Dialect/Linalg/canonicalize.mlir
M mlir/test/Dialect/Linalg/vectorize-tensor-extract.mlir
M mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir
A mlir/test/Dialect/Ptr/canonicalize.mlir
A mlir/test/Dialect/Ptr/ops.mlir
M mlir/test/Dialect/SCF/invalid.mlir
M mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/level_check.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/profile_pro_fp_unsupported.mlir
M mlir/test/Dialect/Tosa/profile_pro_int_unsupported.mlir
M mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
M mlir/test/Dialect/Tosa/variables.mlir
M mlir/test/Dialect/Tosa/verifier.mlir
M mlir/test/Dialect/Vector/canonicalize.mlir
M mlir/test/Dialect/Vector/invalid.mlir
M mlir/test/Dialect/Vector/vector-emulate-narrow-type-unaligned.mlir
M mlir/test/Dialect/Vector/vector-emulate-narrow-type.mlir
M mlir/test/Dialect/Vector/vector-sink-transform.mlir
M mlir/test/Dialect/Vector/vector-sink.mlir
M mlir/test/Dialect/X86Vector/legalize-for-llvm.mlir
M mlir/test/Dialect/X86Vector/roundtrip.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul-mixed-types.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/matmul.mlir
A mlir/test/Integration/GPU/CUDA/concurrent-kernels.mlir
M mlir/test/Target/Cpp/expressions.mlir
M mlir/test/Target/LLVMIR/Import/import-failure.ll
A mlir/test/Target/LLVMIR/Import/indirectbr.ll
M mlir/test/Target/LLVMIR/Import/module-flags.ll
M mlir/test/Target/LLVMIR/gpu.mlir
A mlir/test/Target/LLVMIR/indirectbr.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
M mlir/test/Target/LLVMIR/nvvm/tma_bulk_copy.mlir
M mlir/test/Target/LLVMIR/x86vector.mlir
M mlir/test/lib/Dialect/Affine/TestAffineDataCopy.cpp
M mlir/test/lib/Dialect/GPU/TestGpuRewrite.cpp
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
M mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
A mlir/test/mlir-tblgen/apint-param-error.td
M mlir/test/mlir-translate/import-diagnostics.ll
M mlir/test/python/pass_manager.py
M mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp
M mlir/tools/mlir-tblgen/OmpOpGen.cpp
M mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp
M mlir/tools/mlir-tblgen/TosaUtilsGen.cpp
M mlir/utils/generate-test-checks.py
M offload/DeviceRTL/CMakeLists.txt
M offload/DeviceRTL/src/Kernel.cpp
M offload/DeviceRTL/src/Mapping.cpp
M offload/include/Shared/Environment.h
M offload/liboffload/API/APIDefs.td
M offload/liboffload/API/Common.td
M offload/liboffload/API/Device.td
A offload/liboffload/API/Event.td
A offload/liboffload/API/Kernel.td
A offload/liboffload/API/Memory.td
M offload/liboffload/API/OffloadAPI.td
M offload/liboffload/API/Platform.td
A offload/liboffload/API/Program.td
A offload/liboffload/API/Queue.td
M offload/liboffload/API/README.md
M offload/liboffload/include/OffloadImpl.hpp
M offload/liboffload/include/generated/OffloadAPI.h
M offload/liboffload/include/generated/OffloadEntryPoints.inc
M offload/liboffload/include/generated/OffloadFuncs.inc
M offload/liboffload/include/generated/OffloadImplFuncDecls.inc
M offload/liboffload/include/generated/OffloadPrint.hpp
M offload/liboffload/src/OffloadImpl.cpp
M offload/liboffload/src/OffloadLib.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/test/offloading/ompx_bare.c
M offload/test/offloading/ompx_bare_multi_dim.cpp
M offload/test/tools/offload-tblgen/entry_points.td
M offload/test/tools/offload-tblgen/functions_ranged_param.td
M offload/test/tools/offload-tblgen/print_enum.td
M offload/test/tools/offload-tblgen/print_function.td
M offload/test/tools/offload-tblgen/type_tagged_enum.td
M offload/tools/offload-tblgen/APIGen.cpp
M offload/tools/offload-tblgen/EntryPointGen.cpp
M offload/tools/offload-tblgen/PrintGen.cpp
M offload/tools/offload-tblgen/RecordTypes.hpp
M offload/unittests/OffloadAPI/CMakeLists.txt
M offload/unittests/OffloadAPI/common/Environment.cpp
M offload/unittests/OffloadAPI/common/Environment.hpp
M offload/unittests/OffloadAPI/common/Fixtures.hpp
R offload/unittests/OffloadAPI/device/olGetDevice.cpp
R offload/unittests/OffloadAPI/device/olGetDeviceCount.cpp
M offload/unittests/OffloadAPI/device/olGetDeviceInfo.cpp
M offload/unittests/OffloadAPI/device/olGetDeviceInfoSize.cpp
A offload/unittests/OffloadAPI/device/olIterateDevices.cpp
A offload/unittests/OffloadAPI/device_code/CMakeLists.txt
A offload/unittests/OffloadAPI/device_code/bar.c
A offload/unittests/OffloadAPI/device_code/foo.c
A offload/unittests/OffloadAPI/kernel/olGetKernel.cpp
A offload/unittests/OffloadAPI/kernel/olLaunchKernel.cpp
A offload/unittests/OffloadAPI/memory/olMemAlloc.cpp
A offload/unittests/OffloadAPI/memory/olMemFree.cpp
A offload/unittests/OffloadAPI/memory/olMemcpy.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatform.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatformCount.cpp
M offload/unittests/OffloadAPI/platform/olGetPlatformInfo.cpp
M offload/unittests/OffloadAPI/platform/olGetPlatformInfoSize.cpp
M offload/unittests/OffloadAPI/platform/olPlatformInfo.hpp
A offload/unittests/OffloadAPI/program/olCreateProgram.cpp
A offload/unittests/OffloadAPI/program/olDestroyProgram.cpp
A offload/unittests/OffloadAPI/queue/olCreateQueue.cpp
A offload/unittests/OffloadAPI/queue/olDestroyQueue.cpp
A offload/unittests/OffloadAPI/queue/olWaitQueue.cpp
M openmp/runtime/src/kmp_tasking.cpp
M polly/lib/CodeGen/BlockGenerators.cpp
M polly/lib/CodeGen/CodeGeneration.cpp
M polly/lib/CodeGen/IslExprBuilder.cpp
M polly/lib/CodeGen/IslNodeBuilder.cpp
M polly/lib/CodeGen/LoopGenerators.cpp
M polly/lib/CodeGen/LoopGeneratorsGOMP.cpp
M polly/lib/CodeGen/LoopGeneratorsKMP.cpp
M polly/lib/CodeGen/PerfMonitor.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
A utils/bazel/llvm-project-overlay/libc/test/include/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/plugin_config.bzl
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/python/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
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