[all-commits] [llvm/llvm-project] cd92d8: [clang-format][NFC] Reformat clang/test/Format/lit...
Vitaly Buka via All-commits
all-commits at lists.llvm.org
Thu Apr 24 12:51:49 PDT 2025
Branch: refs/heads/users/vitalybuka/spr/drivercfi-allow-cfi-with-minimal-runtime
Home: https://github.com/llvm/llvm-project
Commit: cd92d8db34afd95335697f85a527028fa8309d18
https://github.com/llvm/llvm-project/commit/cd92d8db34afd95335697f85a527028fa8309d18
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/test/Format/lit.local.cfg
Log Message:
-----------
[clang-format][NFC] Reformat clang/test/Format/lit.local.cfg with black
Commit: cb96a3dc07b0a26023633ae91fab9b4213730236
https://github.com/llvm/llvm-project/commit/cb96a3dc07b0a26023633ae91fab9b4213730236
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
A llvm/test/Transforms/PGOProfile/memprof-dump-matched-alloc-site.ll
M llvm/test/Transforms/PGOProfile/memprof-dump-matched-call-sites.ll
M llvm/test/Transforms/PGOProfile/memprof.ll
Log Message:
-----------
[memprof] Dump the number of matched frames (#137082)
This patch teaches readMemprof to dump the number of frames for each
allocation site match. This information helps us analyze what part of
the call stack in the MemProf profile has matched the IR.
Aside from updating existing test cases, this patch adds one more test
case, memprof-dump-matched-alloc-site.ll, because none of the existing
test cases has the number of frames greater than one.
Commit: 77fe6aaeaaf2b16e021675e92e543dafd18bbc0b
https://github.com/llvm/llvm-project/commit/77fe6aaeaaf2b16e021675e92e543dafd18bbc0b
Author: Wenju He <wenju.he at intel.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M libclc/cmake/modules/AddLibclc.cmake
Log Message:
-----------
[libclc] only check filename part of the source for avoiding duplication (#135710)
llvm-diff shows this PR has no changes to amdgcn--amdhsa.bc.
Motivation is that in our downstream the same category of target
built-ins, e.g. math, are organized in several different folders. For
example, in target SOURCES we have math-common/cos.cl, while in generic
SOURCES it is math/cos.cl. Based on current check rule that compares
both folder name and base filename, target math-common/cos.cl won't
override math/cos.cl when collecting source files from SOURCES files in
cmake function libclc_configure_lib_source.
With this PR, we allow folder name to be different in the process.
A notable change of this PR is that two entries in SOURCES with the same
base filename must not implements the same built-in.
Commit: 31c7997a4acb838c94d5ab40baaf154556532ad9
https://github.com/llvm/llvm-project/commit/31c7997a4acb838c94d5ab40baaf154556532ad9
Author: Thurston Dang <thurston at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/CodeGen/CGClass.cpp
M clang/lib/CodeGen/CGExpr.cpp
Log Message:
-----------
[cfi] Fix one -fno-sanitize-merge case, and add two TODOs (#135438)
-fno-sanitize-merge (introduced in
https://github.com/llvm/llvm-project/pull/120464) nearly works for CFI:
code that calls EmitCheck will already check the merge options. This
patch fixes one EmitTrapCheck call, which did not check the merge
options, and for two other EmitTrapChecks, adds two TODOs that explain
why it is difficult to fix them.
Commit: 096ab51de03437e38f97a48b8f2d453fb903414a
https://github.com/llvm/llvm-project/commit/096ab51de03437e38f97a48b8f2d453fb903414a
Author: Jason Molenda <jmolenda at apple.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/Process/Utility/CMakeLists.txt
A lldb/source/Plugins/Process/Utility/RegisterContextDarwin_riscv32.cpp
A lldb/source/Plugins/Process/Utility/RegisterContextDarwin_riscv32.h
A lldb/test/API/macosx/riscv32-corefile/Makefile
A lldb/test/API/macosx/riscv32-corefile/TestRV32MachOCorefile.py
A lldb/test/API/macosx/riscv32-corefile/create-empty-riscv-corefile.cpp
Log Message:
-----------
[lldb][MachO] MachO corefile support for riscv32 binaries (#137092)
Add support for reading a macho corefile with CPU_TYPE_RISCV and the
riscv32 general purpose register file. I added code for the floating
point and exception registers too, but haven't exercised this. If we
start putting the full CSR register bank in a riscv corefile, it'll be
in separate 4k byte chunks, but I don't have a corefile to test against
that so I haven't written the code to read it.
The RegisterContextDarwin_riscv32 is copied & in the style of the other
RegisterContextDarwin classes; it's not the first choice I would make
for representing this, but it wasn't worth changing for this cputype.
rdar://145014653
Commit: 054ee17f88fcd4dd8d646740b975ef1d2f4ea3aa
https://github.com/llvm/llvm-project/commit/054ee17f88fcd4dd8d646740b975ef1d2f4ea3aa
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn
Log Message:
-----------
[gn build] Port 096ab51de034
Commit: dbb0605f87d8b10171fba6291dd184f5fbf17683
https://github.com/llvm/llvm-project/commit/dbb0605f87d8b10171fba6291dd184f5fbf17683
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Log Message:
-----------
[SelectionDAG] Add NewSDValueDbgMsg to getAtomic.
Commit: fb0000b6624a5f2df25d10e3667111e96dd1abd5
https://github.com/llvm/llvm-project/commit/fb0000b6624a5f2df25d10e3667111e96dd1abd5
Author: Ebuka Ezike <yerimyah1 at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M lldb/include/lldb/Interpreter/OptionValueEnumeration.h
M lldb/source/Interpreter/OptionValueEnumeration.cpp
M lldb/test/API/commands/settings/TestSettings.py
Log Message:
-----------
[lldb][lldb-dap] Add ToJSON for OptionValueEnumeration (#137007)
This automatically enables reading enum settings in the SB API
Commit: de81b852fd8d2b654e1c7112f198026aa272c6b3
https://github.com/llvm/llvm-project/commit/de81b852fd8d2b654e1c7112f198026aa272c6b3
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/sve-varargs-caller-broken.ll
M llvm/test/CodeGen/AArch64/sve-varargs.ll
Log Message:
-----------
[AArch64] Allow variadic calls with SVE argument if it is named. (#136833)
The following case used to work:
void foo(svint32_t a, ...);
void bar(svint32_t a) { foo(a); }
but 6c9086d13fa7e1069e75ed2d139aae30ee3863c8 introduced a regression
that wasn't caught by the existing test `sve-varargs.ll` because the
call in the test wasn't a tail call and therefore skipped the code-path
with the `report_fatal_error`.
Commit: 45a3056a4b3b05d2d1bce7a96437dddead60c071
https://github.com/llvm/llvm-project/commit/45a3056a4b3b05d2d1bce7a96437dddead60c071
Author: Kiran Chandramohan <kiran.chandramohan at arm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
A flang/docs/FortranStandardsSupport.md
M flang/docs/index.md
Log Message:
-----------
[Flang] Add a Fortran Standards Support doc (#132195)
Commit: 7af555e524b5cddc338bf73b87d8b666611cefbc
https://github.com/llvm/llvm-project/commit/7af555e524b5cddc338bf73b87d8b666611cefbc
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/ARM/popcnt.ll
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
M llvm/test/CodeGen/RISCV/pr56457.ll
M llvm/test/CodeGen/RISCV/pr95271.ll
M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/RISCV/sextw-removal.ll
M llvm/test/CodeGen/Thumb2/mve-ctpop.ll
Log Message:
-----------
[ARM][RISCV] Partially revert #101786 (#137120)
The change as is breaks the Linux kernel build as pointed out in the
comments.
Commit: 886f1199f07bbcc385e35b90b9e620cbc8d76068
https://github.com/llvm/llvm-project/commit/886f1199f07bbcc385e35b90b9e620cbc8d76068
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Log Message:
-----------
[AMDGPU] Use variadic isa<>. NFC. (#137016)
Commit: bea110db3ed1fa1215bb8e22d2057019fcbd2d16
https://github.com/llvm/llvm-project/commit/bea110db3ed1fa1215bb8e22d2057019fcbd2d16
Author: Hampus Adolfsson <15944368+HampusAdolfsson at users.noreply.github.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang-tools-extra/clangd/XRefs.cpp
M clang-tools-extra/clangd/unittests/CallHierarchyTests.cpp
Log Message:
-----------
[clangd] Strip invalid fromRanges for outgoing calls (#134657)
`CallHierarchyOutgoingCall::fromRanges` are interpreted as ranges in the
same file as the item for which 'outgoingCalls' was called.
It's possible for outgoing calls to be in a different file than that
item if the item is just a declaration (e.g. in a header file). Now,
such calls are dropped instead of being returned to the client.
This is the same as the change made in #111616, but now for outgoing
calls.
Fixes clangd/clangd#2350
---------
Co-authored-by: Nathan Ridge <zeratul976 at hotmail.com>
Commit: 15bb1db4a98309f8769fa6d53a52eae62a61fbb2
https://github.com/llvm/llvm-project/commit/15bb1db4a98309f8769fa6d53a52eae62a61fbb2
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll
M llvm/test/Transforms/LoopVectorize/X86/pr51366-sunk-instruction-used-outside-of-loop.ll
M llvm/test/Transforms/LoopVectorize/X86/small-size.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll
Log Message:
-----------
[VPlan] Remove ILV::sinkScalarOperands. (#136023)
Remove legacy ILV sinkScalarOperands, which is superseded by the
sinkScalarOperands VPlan transforms.
There are a few cases that aren't handled by VPlan's sinkScalarOperands,
because the recipes doesn't support replicating. Those are pointer
inductions and blends.
We could probably improve this further, by allowing replication for more
recipes, but I don't think the extra complexity is warranted.
Depends on https://github.com/llvm/llvm-project/pull/136021.
PR: https://github.com/llvm/llvm-project/pull/136023
Commit: 0c61b24337236a0f67be54c26e12c98e9aecef5b
https://github.com/llvm/llvm-project/commit/0c61b24337236a0f67be54c26e12c98e9aecef5b
Author: Oleksandr "Alex" Zinenko <git at ozinenko.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M flang/lib/Optimizer/CodeGen/LowerRepackArrays.cpp
M flang/lib/Optimizer/HLFIR/Transforms/InlineElementals.cpp
M flang/lib/Optimizer/HLFIR/Transforms/InlineHLFIRAssign.cpp
M flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
M flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/AssumedRankOpConversion.cpp
M flang/lib/Optimizer/Transforms/ConstantArgumentGlobalisation.cpp
M flang/lib/Optimizer/Transforms/SimplifyFIROperations.cpp
M flang/lib/Optimizer/Transforms/StackArrays.cpp
M mlir/include/mlir/Transforms/GreedyPatternRewriteDriver.h
M mlir/include/mlir/Transforms/Passes.td
M mlir/lib/Dialect/Affine/TransformOps/AffineTransformOps.cpp
M mlir/lib/Dialect/Affine/Transforms/AffineDataCopyGeneration.cpp
M mlir/lib/Dialect/Affine/Transforms/SimplifyAffineStructures.cpp
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/lib/Dialect/Affine/Utils/Utils.cpp
M mlir/lib/Dialect/Arith/Transforms/IntRangeOptimizations.cpp
M mlir/lib/Dialect/Bufferization/Transforms/BufferDeallocationSimplification.cpp
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp
M mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp
M mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
M mlir/lib/Dialect/Transform/IR/TransformOps.cpp
M mlir/lib/Reducer/ReductionTreePass.cpp
M mlir/lib/Transforms/Canonicalizer.cpp
M mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
M mlir/test/lib/Dialect/Affine/TestAffineDataCopy.cpp
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
Log Message:
-----------
[mlir] add a fluent API to GreedyRewriterConfig (#137122)
This is similar to other configuration objects used across MLIR.
Rename some fields to better reflect that they are no longer booleans.
Reland 04d261101b4f229189463136a794e3e362a793af / #132253.
Commit: e268f71c5900f13207a7cd942f856f5852233d9e
https://github.com/llvm/llvm-project/commit/e268f71c5900f13207a7cd942f856f5852233d9e
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[VPlan] Remove unneeded early continue. (NFC)
As suggested in
https://github.com/llvm/llvm-project/pull/136455, now unreachable exit
blocks won't have any phi nodes.
Commit: a3d05e89873654dd1b27979b2bfd82ddd4859ba7
https://github.com/llvm/llvm-project/commit/a3d05e89873654dd1b27979b2bfd82ddd4859ba7
Author: anjenner <161845516+anjenner at users.noreply.github.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.AFLCustomIRMutator.opt.ll
Log Message:
-----------
Remove an incorrect assert in MFMASmallGemmSingleWaveOpt. (#130131)
This assert was failing in a fuzzing test. I consulted with @jrbyrnes
who said:
The MFMASmallGemmSingleWaveOpt::apply() method is invoked if and only if
the user has inserted an intrinsic llvm.amdgcn.iglp.opt(i32 1) into
their source code. This intrinsic applies a highly specialized DAG
mutation to result in specific scheduling for a specific set of kernels.
These assertions are really just confirming that the characteristics of
the kernel match what is expected (i.e. The kernels are similar to the
ones this DAG mutation strategy were designed against).
However, if we apply this DAG mutation to kernels for which is was not
designed, then we may not find the types of instructions we are looking
for, and may end up with empty caches.
I think it should be fine to just return false if the cache is empty
instead of the assert.
Commit: 03c2862404a9ab19940f87f8fb2dbe01818ab439
https://github.com/llvm/llvm-project/commit/03c2862404a9ab19940f87f8fb2dbe01818ab439
Author: Yuzhiy <44502685+Yuzhiy05 at users.noreply.github.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M libcxx/include/__ranges/to.h
M libcxx/test/libcxx/ranges/range.utility/range.utility.conv/to.static_assert.verify.cpp
Log Message:
-----------
[libc++][ranges] Reject non-class types in ranges::to (#135802)
This patch adds `static_assert` using `is_class_v` and `is_union_v` to
reject no-class type template parameters.
Fixes #132133
---------
Co-authored-by: A. Jiang <de34 at live.cn>
Commit: a2f00e1f8f124667339b94ffa144c0ff0d6ae3b3
https://github.com/llvm/llvm-project/commit/a2f00e1f8f124667339b94ffa144c0ff0d6ae3b3
Author: Luke Lau <luke at igalia.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
Log Message:
-----------
[RISCV] Add fixed-length patterns for disjoint or patterns for vwadd[u].v{v,x} (#136824)
This is the fixed-length equivalent of #136716.
The pattern we need to match is ({s,z}ext_vl (or_vl disjoint a, b)).
This only allows or_vls with an undef passthru, which allows us to
ignore its mask and vl and just take it from the {s,z}ext_vl.
A riscv_or_vl_is_add_oneuse PatFrag is added to mirror or_is_add in
RISCVInstrInfo.td.
Commit: 3883b27ba8a85c0228d5e49cb59d127d14dd0f8d
https://github.com/llvm/llvm-project/commit/3883b27ba8a85c0228d5e49cb59d127d14dd0f8d
Author: Luke Lau <luke at igalia.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
Log Message:
-----------
[VPlan] Fix typo in assertion. NFC (#137009)
Commit: be044976b6c27a5553d7e83d60f64c4a72c0de52
https://github.com/llvm/llvm-project/commit/be044976b6c27a5553d7e83d60f64c4a72c0de52
Author: SivanShani-Arm <sivan.shani at arm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsAArch64.def
M clang/lib/Headers/arm_acle.h
M clang/test/CodeGen/AArch64/gcs.c
Log Message:
-----------
[AArch64] Update __gcsss intrinsic to match revised ACLE specification (#136850)
The original __gcsss intrinsic was implemented based on:
https://github.com/ARM-software/acle/pull/260
with the signature: const void *__gcsss(const void *)
Per the updated specification in:
https://github.com/ARM-software/acle/pull/364
both const qualifiers have been removed. This commit updates the
signature accordingly to: void *__gcsss(void *)
This aligns the implementation with the latest ACLE definition.
Commit: 59b26abbbe89994c2ffd50a933654be247b68aaf
https://github.com/llvm/llvm-project/commit/59b26abbbe89994c2ffd50a933654be247b68aaf
Author: Camsyn <camsyn at foxmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
A compiler-rt/test/tsan/stack_race3.cpp
M llvm/lib/Transforms/Instrumentation/SanitizerBinaryMetadata.cpp
M llvm/lib/Transforms/Instrumentation/ThreadSanitizer.cpp
M llvm/test/Instrumentation/ThreadSanitizer/capture.ll
Log Message:
-----------
[TSan, SanitizerBinaryMetadata] Analyze the capture status for `alloca` rather than arbitrary `Addr` (#132756)
This PR is based on my last PR #132752 (the first commit of this PR),
but addressing a different issue.
This commit addresses the limitation in `PointerMayBeCaptured` analysis
when dealing with derived pointers (e.g. arr+1) as described in issue
#132739.
The current implementation of `PointerMayBeCaptured` may miss captures
of the underlying `alloca` when analyzing derived pointers, leading to
some FNs in TSan, as follows:
```cpp
void *Thread(void *a) {
((int*)a)[1] = 43;
return 0;
}
int main() {
int Arr[2] = {41, 42};
pthread_t t;
pthread_create(&t, 0, Thread, &Arr[0]);
// Missed instrumentation here due to the FN of PointerMayBeCaptured
Arr[1] = 43;
barrier_wait(&barrier);
pthread_join(t, 0);
}
```
Refer to this [godbolt page](https://godbolt.org/z/n67GrxdcE) to get the
compilation result of TSan.
Even when `PointerMayBeCaptured` working correctly, it should backtrack
to the original `alloca` firstly during analysis, causing redundancy to
the outer's `findAllocaForValue`.
```cpp
const AllocaInst *AI = findAllocaForValue(Addr);
// Instead of Addr, we should check whether its base pointer is captured.
if (AI && !PointerMayBeCaptured(Addr, true)) ...
```
Key changes:
Directly analyze the capture status of the underlying `alloca` instead
of derived pointers to ensure accurate capture detection
```cpp
const AllocaInst *AI = findAllocaForValue(Addr);
// Instead of Addr, we should check whether its base pointer is captured.
if (AI && !PointerMayBeCaptured(AI, true)) ...
```
Commit: 1ec22fae7e2c72b763b1c5ee6b743c59b5a4064c
https://github.com/llvm/llvm-project/commit/1ec22fae7e2c72b763b1c5ee6b743c59b5a4064c
Author: Jonas Paulsson <paulson1 at linux.ibm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZInstrFP.td
M llvm/test/CodeGen/SystemZ/fp-abs-01.ll
M llvm/test/CodeGen/SystemZ/fp-abs-02.ll
M llvm/test/CodeGen/SystemZ/fp-abs-03.ll
M llvm/test/CodeGen/SystemZ/fp-abs-04.ll
M llvm/test/CodeGen/SystemZ/fp-mul-08.ll
M llvm/test/CodeGen/SystemZ/fp-mul-10.ll
M llvm/test/CodeGen/SystemZ/fp-neg-01.ll
M llvm/test/CodeGen/SystemZ/fp-neg-02.ll
Log Message:
-----------
[SystemZ] Handle f16 load positive/negative/complement without libcalls. (#136286)
This can be done directly with the (64-bit) target instruction as only the sign bit
is changed.
Commit: 55066b83612b6bcc8c38ef6a84e5230ad116730f
https://github.com/llvm/llvm-project/commit/55066b83612b6bcc8c38ef6a84e5230ad116730f
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
A clang/test/AST/ByteCode/i686.cpp
Log Message:
-----------
[clang][bytecode] Compute pointer differences as 64bit integers (#137128)
And only convert to the target type after that.
Commit: 94a14f9f0d884eebb87fb3003229ffee5f95d1c8
https://github.com/llvm/llvm-project/commit/94a14f9f0d884eebb87fb3003229ffee5f95d1c8
Author: Jonas Paulsson <paulson1 at linux.ibm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.h
M llvm/lib/Target/SystemZ/SystemZInstrFP.td
M llvm/test/CodeGen/SystemZ/fp-copysign-01.ll
M llvm/test/CodeGen/SystemZ/fp-copysign-02.ll
M llvm/test/CodeGen/SystemZ/fp-copysign-03.ll
Log Message:
-----------
[SystemZ] Add DAGCombine for FCOPYSIGN to remove rounding. (#136131)
Add a DAGCombine for FCOPYSIGN that removes the rounding which is never
needed as the sign bit is already in the correct place. This helps in particular the
rounding to f16 case which needs a libcall.
Also remove the roundings for other FP VTs and simplify the CPSDR
patterns correspondingly.
fp-copysign-03.ll test updated, now also covering the other FP VT
combinations.
Commit: e98a61dc326c1b564461c0ae4fc693be5113d540
https://github.com/llvm/llvm-project/commit/e98a61dc326c1b564461c0ae4fc693be5113d540
Author: Tai Ly <tai.ly at arm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/verifier.mlir
Log Message:
-----------
[mlir][tosa] Add verifier check for Concat Op (#136047)
This adds verifier check for Concat Op
to make sure the sum of concatenated axis dimensions is equal to the
output's axis dimension
add tests in verifier.mlir
also moved existing concat verifier checks to verifier.mlir
Signed-off-by: Tai Ly <tai.ly at arm.com>
Commit: 66461dbb3b8d107fae2d50049205ddb8c192049c
https://github.com/llvm/llvm-project/commit/66461dbb3b8d107fae2d50049205ddb8c192049c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
Log Message:
-----------
SPIRV: Set NoPHIs property after rewriting them (#136327)
There should be no PHIs after selection, as OpPhi is used
instead. This hopefully avoids errors in #135277.
Commit: c6c08462ee3e8fc3d9cf9a69bb51175be49d5d3c
https://github.com/llvm/llvm-project/commit/c6c08462ee3e8fc3d9cf9a69bb51175be49d5d3c
Author: Jannick Kremer <jannick.kremer at mailbox.org>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/bindings/python/clang/cindex.py
A clang/bindings/python/tests/cindex/INPUTS/a.inc
A clang/bindings/python/tests/cindex/INPUTS/b.inc
A clang/bindings/python/tests/cindex/INPUTS/testfile.c
M clang/bindings/python/tests/cindex/test_file.py
M clang/docs/ReleaseNotes.rst
Log Message:
-----------
[libclang/python] Add equality comparison operators for File (#130383)
This covers the `File` interface changes added by #120590
---------
Co-authored-by: Mathias Stearn <redbeard0531 at gmail.com>
Co-authored-by: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Commit: 82c25d27501996683f30eb92dabf8a11925b7a62
https://github.com/llvm/llvm-project/commit/82c25d27501996683f30eb92dabf8a11925b7a62
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/test/AST/ByteCode/i686.cpp
Log Message:
-----------
[clang][bytecode] Disable i686 test
The array is too big and we don't have array fillers yet, see
e.g. https://lab.llvm.org/buildbot/#/builders/154/builds/15255
Commit: 88083a0c42e69e5967737e088ac6e5b1d12343f0
https://github.com/llvm/llvm-project/commit/88083a0c42e69e5967737e088ac6e5b1d12343f0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
Log Message:
-----------
[X86] SimplifyDemandedVectorEltsForTargetNode - handle 512-bit X86ISD::VPERMI with lower half demanded elts (#137139)
512-bit X86ISD::VPERMI nodes handle the lower/upper 256-bits separately - so if we don't demand the upper half elements, we can just use the 256-bit variant.
Commit: ebceb732d5afa7b97b73b34ce078a58c654ff0a0
https://github.com/llvm/llvm-project/commit/ebceb732d5afa7b97b73b34ce078a58c654ff0a0
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/Vector/canonicalize.mlir
Log Message:
-----------
[mlir][vector] Update the folder for vector.{insert|extract} (#136579)
This is a minor follow-up to #135498. It ensures that operations like
the following are not treated as out-of-bounds accesses and can be
folded correctly (*):
```mlir
%c_neg_1 = arith.constant -1 : index
%0 = vector.insert %value_to_store, %dest[%c_neg_1] : vector<5xf32> into vector<4x5xf32>
%1 = vector.extract %src[%c_neg_1, 0] : f32 from vector<4x5xf32>
```
In addition to adding tests for the case above, this PR also relocates
the tests from #135498 to be alongside existing tests for the
`vector.{insert|extract}` folder, and reformats them to follow:
* https://mlir.llvm.org/getting_started/TestingGuide/
For example:
* The "no_fold" prefix is now used to label negative tests.
* Redundant check lines have been removed (e.g., CHECK: vector.insert
is sufficient to verify that folding did not occur).
(*) As per https://mlir.llvm.org/docs/Dialects/Vector/#vectorinsert-vectorinsertop,
these are poison values.
Commit: 427b6448a3af009e57c0142d6d8af83318b45093
https://github.com/llvm/llvm-project/commit/427b6448a3af009e57c0142d6d8af83318b45093
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrGISel.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/lower-neon-vector-fcmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vector-fcmp.mir
M llvm/test/CodeGen/AArch64/arm64-zip.ll
M llvm/test/CodeGen/AArch64/select_cc.ll
Log Message:
-----------
Revert "[LLVM][ISel][AArch64 Remove AArch64ISD::FCM##z nodes. (#135817)"
This reverts commit 15d8b3cae9debc2bd7d27ca92ff599ba9fb30da5.
Commit: e37c236597137bae4f6728e163e9f81a1d9aff18
https://github.com/llvm/llvm-project/commit/e37c236597137bae4f6728e163e9f81a1d9aff18
Author: Christian Sigg <csigg at google.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] Remove unnecessary dependencies. (#136999)
Commit: d664c42baaed7f47a80f73a3974afd6e2593e41a
https://github.com/llvm/llvm-project/commit/d664c42baaed7f47a80f73a3974afd6e2593e41a
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M libclc/generic/include/clc/clc.h
R libclc/generic/include/clc/clcmacros.h
Log Message:
-----------
[libclc] Remove unnecessary clcmacros.h (#137149)
The macros defined by this file (not to be confused with clcmacro.h)
don't appear necessary for building libclc.
The language version macros should be handled by clang, and there are no
uses of NULL or kernel_exec in the source code.
Commit: 6900e9026516963ae625b28dded2cdf0bd16e590
https://github.com/llvm/llvm-project/commit/6900e9026516963ae625b28dded2cdf0bd16e590
Author: jeremyd2019 <github at jdrake.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/TargetParser/Triple.cpp
M llvm/unittests/TargetParser/TripleTest.cpp
Log Message:
-----------
[LLVM][TargetParser] Handle -msys targets the same as -cygwin. (#136817)
MSYS2 uses i686-pc-msys and x86_64-pc-msys as target, and is a fork of
Cygwin. There's an effort underway to try to switch as much as possible
to use -pc-cygwin targets, but the -msys target will be hanging around
for the forseeable future.
Commit: 15321d2c9e686b382262339fa17c5445b1b2609f
https://github.com/llvm/llvm-project/commit/15321d2c9e686b382262339fa17c5445b1b2609f
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaObjC.cpp
M clang/lib/Sema/SemaObjCProperty.cpp
M clang/lib/Sema/SemaOverload.cpp
A clang/test/Sema/implicit-void-ptr-cast.c
Log Message:
-----------
[C] Add (new) -Wimplicit-void-ptr-cast to -Wc++-compat (#136855)
This introduces a new diagnostic group (-Wimplicit-void-ptr-cast),
grouped under -Wc++-compat, which diagnoses implicit conversions from
void * to another pointer type in C. It's a common source of
incompatibility with C++ and is something GCC diagnoses (though GCC does
not have a specific warning group for this).
Fixes #17792
Commit: 2edade28245b1fc2b7cb0b39804894f8fdcfb7ff
https://github.com/llvm/llvm-project/commit/2edade28245b1fc2b7cb0b39804894f8fdcfb7ff
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M libclc/generic/include/clc/shared/vload.h
M libclc/generic/include/clc/shared/vstore.h
M libclc/generic/lib/shared/vload.cl
M libclc/generic/lib/shared/vload_half.inc
M libclc/generic/lib/shared/vstore.cl
M libclc/generic/lib/shared/vstore_half.inc
Log Message:
-----------
[libclc][NFC] Clang-format vload/vstore code
Commit: acc335bfa7b00ab19bf9832870aaf207f587b48b
https://github.com/llvm/llvm-project/commit/acc335bfa7b00ab19bf9832870aaf207f587b48b
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/test/CodeGen/X86/build-vector-128.ll
M llvm/test/CodeGen/X86/build-vector-256.ll
M llvm/test/CodeGen/X86/build-vector-512.ll
Log Message:
-----------
[X86] Add build vector test patterns with only 2 unique scalars
Based off test coverage for #135753 - these should be lowered to BLEND(BROADCAST(X),BROADCAST(Y))
Commit: 5d136f90a9806daf6d9ac905734a27974fc8f1b7
https://github.com/llvm/llvm-project/commit/5d136f90a9806daf6d9ac905734a27974fc8f1b7
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Manage instruction metadata in VPlan. (#135272)
Add a new helper to manage IR metadata that can be progated to generated
instructions for recipes.
This helps to remove a number of remaining uses of getUnderlyingInstr
during VPlan execution.
PR: https://github.com/llvm/llvm-project/pull/135272
Commit: f218cd28d4b762846a84a24817396465b824710d
https://github.com/llvm/llvm-project/commit/f218cd28d4b762846a84a24817396465b824710d
Author: Luke Lau <luke at igalia.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
Log Message:
-----------
[IA] Remove unused argument. NFC
Commit: dde00f5e22e81ac88b37d1502d2383985a58329d
https://github.com/llvm/llvm-project/commit/dde00f5e22e81ac88b37d1502d2383985a58329d
Author: Tejas Vipin <alissxlace at proton.me>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
R libc/test/src/math/performance_testing/BinaryOpSingleOutputPerf.h
M libc/test/src/math/performance_testing/CMakeLists.txt
A libc/test/src/math/performance_testing/PerfTest.h
R libc/test/src/math/performance_testing/SingleInputSingleOutputPerf.h
M libc/test/src/math/performance_testing/ceilf_perf.cpp
M libc/test/src/math/performance_testing/cosf_perf.cpp
M libc/test/src/math/performance_testing/exp10f16_perf.cpp
M libc/test/src/math/performance_testing/exp2f16_perf.cpp
M libc/test/src/math/performance_testing/exp2f_perf.cpp
M libc/test/src/math/performance_testing/expf16_perf.cpp
M libc/test/src/math/performance_testing/expf_perf.cpp
M libc/test/src/math/performance_testing/expm1f_perf.cpp
M libc/test/src/math/performance_testing/fabsf_perf.cpp
M libc/test/src/math/performance_testing/floorf_perf.cpp
M libc/test/src/math/performance_testing/fmod_perf.cpp
M libc/test/src/math/performance_testing/fmodf128_perf.cpp
M libc/test/src/math/performance_testing/fmodf16_perf.cpp
M libc/test/src/math/performance_testing/fmodf_perf.cpp
M libc/test/src/math/performance_testing/fmodl_perf.cpp
M libc/test/src/math/performance_testing/fmul_perf.cpp
M libc/test/src/math/performance_testing/fmull_perf.cpp
M libc/test/src/math/performance_testing/hypot_perf.cpp
M libc/test/src/math/performance_testing/hypotf16_perf.cpp
M libc/test/src/math/performance_testing/hypotf_perf.cpp
M libc/test/src/math/performance_testing/log10f_perf.cpp
M libc/test/src/math/performance_testing/log1pf_perf.cpp
M libc/test/src/math/performance_testing/log2f_perf.cpp
M libc/test/src/math/performance_testing/logbf_perf.cpp
M libc/test/src/math/performance_testing/logf_perf.cpp
M libc/test/src/math/performance_testing/max_min_funcs_perf.cpp
M libc/test/src/math/performance_testing/misc_basic_ops_perf.cpp
M libc/test/src/math/performance_testing/nearbyintf_perf.cpp
M libc/test/src/math/performance_testing/nearest_integer_funcs_perf.cpp
M libc/test/src/math/performance_testing/rintf_perf.cpp
M libc/test/src/math/performance_testing/roundf_perf.cpp
M libc/test/src/math/performance_testing/sinf_perf.cpp
M libc/test/src/math/performance_testing/sqrtf128_perf.cpp
M libc/test/src/math/performance_testing/sqrtf_perf.cpp
M libc/test/src/math/performance_testing/truncf_perf.cpp
Log Message:
-----------
[libc][math] Improve performance test framework (#134501)
- Merges `BinaryOpSingleOutputPerf.h` and
`SingleInputSingleOutputPerf.h` files into a unified `PerfTest.h` and
update all performance tests to use this.
- Improve the output printed to log file for tests.
- Removes unused `run_diff` method and redundant `run_perf` call in
`BINARY_INPUT_SINGLE_OUTPUT_PERF_EX` (previously
`BINARY_OP_SINGLE_OUTPUT_PERF_EX`)
- Change `BINARY_INPUT_SINGLE_OUTPUT_PERF_EX` and
`SINGLE_INPUT_SINGLE_OUTPUT_PERF` to not define `main`
Commit: 06d48769825c656bff97c05d398ce3ec77acfb36
https://github.com/llvm/llvm-project/commit/06d48769825c656bff97c05d398ce3ec77acfb36
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Replace checking IR loop with checking VPlan predecessors (NFC).
Update check to use VPEarlyExitBlock's predecessors, which removes a
dependence on underlying IR and is more in line with the comment below.
Commit: 79144643b6b82f05fd0cee8916a2162b14bfd9fd
https://github.com/llvm/llvm-project/commit/79144643b6b82f05fd0cee8916a2162b14bfd9fd
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/test/Transforms/PhaseOrdering/X86/blendv-select.ll
Log Message:
-----------
[PhaseOrdering][X86] blendv-select.ll - add test coverage for #66513
Commit: e35cc2d387e170d0e1f6ef647f17423262feb1ea
https://github.com/llvm/llvm-project/commit/e35cc2d387e170d0e1f6ef647f17423262feb1ea
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
Log Message:
-----------
[lldb][TypeSystemClang][NFC] Clean up TypeSystemClang::DeclGetMangledName to LLVM-style
Will make upcoming changes in this area easier to read.
Commit: bcdafc107e1fb68893036cfba14e761c7b37b0e9
https://github.com/llvm/llvm-project/commit/bcdafc107e1fb68893036cfba14e761c7b37b0e9
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M lldb/test/API/commands/process/reverse-continue/TestReverseContinueNotSupported.py
Log Message:
-----------
[lldb] Disable reverse continue command test on Windows
The new test added in https://github.com/llvm/llvm-project/pull/132783
is timing out on our Windows on Arm bot
https://lab.llvm.org/buildbot/#/builders/141/builds/8149
Disable it there while I figure out the problem.
Commit: 8b2d269db22d253ef07a48ef433bc94dc70f2c75
https://github.com/llvm/llvm-project/commit/8b2d269db22d253ef07a48ef433bc94dc70f2c75
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
A llvm/test/CodeGen/X86/buildvec-widen-dotproduct.ll
Log Message:
-----------
[X86] Add extended test coverage for #135010
Commit: d7f3c3129344b133859d89d962fcdd5058702f72
https://github.com/llvm/llvm-project/commit/d7f3c3129344b133859d89d962fcdd5058702f72
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrGISel.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/lower-neon-vector-fcmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-const-vector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vector-fcmp.mir
M llvm/test/CodeGen/AArch64/arm64-zip.ll
M llvm/test/CodeGen/AArch64/select_cc.ll
Log Message:
-----------
Reapply "[LLVM][ISel][AArch64 Remove AArch64ISD::FCM##z nodes. (#135817)"
This reverts commit 427b6448a3af009e57c0142d6d8af83318b45093.
Original patch has been updated to include a fix to esnure
AArch64InstructionSelector::emitConstantVector supports all the cases
where isBuildVectorAllOnes returns true.
Commit: ecdd3fd71f41f600623e93bad08f9e41b1d0d8cc
https://github.com/llvm/llvm-project/commit/ecdd3fd71f41f600623e93bad08f9e41b1d0d8cc
Author: Karthika Devi C <quic_kartc at quicinc.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M polly/lib/CodeGen/BlockGenerators.cpp
M polly/lib/CodeGen/CodeGeneration.cpp
M polly/lib/CodeGen/IslExprBuilder.cpp
M polly/lib/CodeGen/IslNodeBuilder.cpp
M polly/lib/CodeGen/LoopGenerators.cpp
M polly/lib/CodeGen/LoopGeneratorsGOMP.cpp
M polly/lib/CodeGen/LoopGeneratorsKMP.cpp
M polly/lib/CodeGen/PerfMonitor.cpp
Log Message:
-----------
[RemoveDI][Polly] Use iterators instead of instruction pointers to SetInsertPoint (#135336)
As part of the effort to transition to using Debug Records instead of
Debug intrinsics, some API/argument changes are necessary to achieve the
desired behavior from Debug Records. This particular fix involves
passing iterators instead of instruction pointers to the SetInsertPoint
function. While this is crucial in certain areas, it may be more than
needed in others, but it does not cause any harm.
Commit: 224cd50e005a9215e8c528d5ce68d4fcdfcdb98f
https://github.com/llvm/llvm-project/commit/224cd50e005a9215e8c528d5ce68d4fcdfcdb98f
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
A llvm/test/Transforms/GlobalOpt/X86/preserve-dbgloc-of-load-store-to-bool.ll
Log Message:
-----------
[DebugInfo][GlobalOpt] Preserve source locs for optimized loads (#134828)
Some optimizations in globalopt simplify uses of a global value to uses
of a generated global bool value; in some cases where this happens, the
newly-generated instructions would not have the original source
location(s) of the instructions they replaced propagated to them; this
patch properly preserves those source locations.
Found using https://github.com/llvm/llvm-project/pull/107279.
Commit: 57530c23a53b5e003d389437637f61c5b9814e22
https://github.com/llvm/llvm-project/commit/57530c23a53b5e003d389437637f61c5b9814e22
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
A llvm/test/Transforms/GlobalOpt/malloc-promote-atomic.ll
Log Message:
-----------
[GlobalOpt] Do not promote malloc if there are atomic loads/stores (#137158)
When converting a malloc stored to a global into a global, we will
introduce an i1 flag to track whether the global has been initialized.
In case of atomic loads/stores, this will result in verifier failures,
because atomic ops on i1 are illegal. Even if we changed this to i8, I
don't think it is a good idea to change atomic types in that way.
Instead, bail out of the transform is we encounter any atomic
loads/stores of the global.
Fixes https://github.com/llvm/llvm-project/issues/137152.
Commit: f572a5951a664d57e909928d5595285212ad6884
https://github.com/llvm/llvm-project/commit/f572a5951a664d57e909928d5595285212ad6884
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
A llvm/test/Transforms/VectorCombine/pr132563.ll
Log Message:
-----------
[VectorCombine] Ensure canScalarizeAccess handles cases where the index type can't represent all inbounds values
Fixes #132563
Commit: 2dfe68a306b33048346d30ca141605be991e5302
https://github.com/llvm/llvm-project/commit/2dfe68a306b33048346d30ca141605be991e5302
Author: Josep Pinot <josep.pinot at bsc.es>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M openmp/runtime/src/kmp_tasking.cpp
Log Message:
-----------
[NFC][OpenMP] Fix task record/replay comments (#137178)
Commit: 10ea5eedb1d13760e4caf0bd983ce7778cff0426
https://github.com/llvm/llvm-project/commit/10ea5eedb1d13760e4caf0bd983ce7778cff0426
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/test/CodeGen/X86/pr40891.ll
Log Message:
-----------
[X86] pr40891.ll - add X64 test coverage
Commit: 139e30e2158dcb83db82e59df6ec48894eac0129
https://github.com/llvm/llvm-project/commit/139e30e2158dcb83db82e59df6ec48894eac0129
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
R libclc/amdgpu/lib/SOURCES_3.9
R libclc/amdgpu/lib/SOURCES_4.0
R libclc/amdgpu/lib/SOURCES_5.0
R libclc/amdgpu/lib/shared/vload_half_helpers.ll
R libclc/amdgpu/lib/shared/vstore_half_helpers.ll
M libclc/generic/lib/shared/vload.cl
M libclc/generic/lib/shared/vstore.cl
M libclc/generic/lib/shared/vstore_half.inc
R libclc/ptx/lib/SOURCES_3.9
R libclc/ptx/lib/SOURCES_4.0
R libclc/ptx/lib/SOURCES_5.0
R libclc/ptx/lib/shared/vload_half_helpers.ll
R libclc/ptx/lib/shared/vstore_half_helpers.ll
Log Message:
-----------
[libclc] Remove (vload|vstore)_half helpers (#137181)
These were only being used when compiling with versions of clang older
than clang 6. As such they were essentially unsupported and untested.
This somewhat simplifies the codebase, producing fewer helper functions
in the final builtins library. It also avoids typed pointer IR.
There's no change to any of the targets' bytecode other than removing
these helper functions.
Commit: e3eee9e81ec2a42d1f78d8a4e52f4b4ee8927436
https://github.com/llvm/llvm-project/commit/e3eee9e81ec2a42d1f78d8a4e52f4b4ee8927436
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/test/CodeGen/X86/vector-trunc.ll
Log Message:
-----------
[X86] vector-trunc.ll - replace stores to ptr undef with real ptr values
Prevents some unnecessary codegen changes in an upcoming patch
Commit: ed866d994c3b074cb1b7a380b1ce9169dde3362c
https://github.com/llvm/llvm-project/commit/ed866d994c3b074cb1b7a380b1ce9169dde3362c
Author: Evgenii Kudriashov <evgenii.kudriashov at intel.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/extractelement-load.ll
Log Message:
-----------
[X86][Combine] Ensure single use chain in extract-load combine (#136520)
The problem is that `SrcBC = peekThroughBitcasts(Src)` doesn't ensure
single use chain. It results in the situation when a cast may have
multiple users and instead of replacing a load we introduce a new one.
The situation is worsened by the fact that we've replaced the token from
the original load and its correct memory order now is not guaranteed.
Commit: 52a96491e1e4e0d033e39fad87f49ccd871df41d
https://github.com/llvm/llvm-project/commit/52a96491e1e4e0d033e39fad87f49ccd871df41d
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/lib/Basic/Targets/SPIR.h
A clang/test/CodeGenCUDASPIRV/printf.cu
Log Message:
-----------
[clang][SPIR-V] Addrspace of opencl_global should always be 1 (#136753)
This fixes a CUDA SPIR-V regression introduced in
https://github.com/llvm/llvm-project/pull/134399.
---------
Signed-off-by: Sarnie, Nick <nick.sarnie at intel.com>
Commit: 3e605b1e1d85f6767bbc2a91d3916688118040cd
https://github.com/llvm/llvm-project/commit/3e605b1e1d85f6767bbc2a91d3916688118040cd
Author: zhijian lin <zhijian at ca.ibm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
A llvm/test/CodeGen/PowerPC/vsx-fma-m-early.ll
Log Message:
-----------
[NFC] Add a pre-commit test case for #111696 (#136730)
Add a pre- commit test case for Patch
https://github.com/llvm/llvm-project/pull/111696
Test ppc-vsx-fma-mutate pass work with
-schedule-ppc-vsx-fma-mutation-early not hoist the instruction
`xxspltiw vs2, 1170469888` out the loop.
---------
Co-authored-by: Amy Kwan <amy.kwan1 at ibm.com>
Commit: d859cb68836191cfa469d0c951134b53ee31298e
https://github.com/llvm/llvm-project/commit/d859cb68836191cfa469d0c951134b53ee31298e
Author: erichkeane <ekeane at nvidia.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/lib/Sema/SemaOpenACCClause.cpp
Log Message:
-----------
[OpenACC] Fix variable dereference found by static analysis
Reported here: https://github.com/llvm/llvm-project/issues/137116
Fixes: 137116
Commit: 9ae7aa79b1e151c3af12b9ffec0e2fdeacde5cc9
https://github.com/llvm/llvm-project/commit/9ae7aa79b1e151c3af12b9ffec0e2fdeacde5cc9
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/test/AST/ByteCode/records.cpp
Log Message:
-----------
[clang][bytecode] Diagnose comparing pointers to fields... (#137159)
... with different access specifiers.
Commit: 0fcc9ffafd35e4567e6bc90f46b8c75f501dddf9
https://github.com/llvm/llvm-project/commit/0fcc9ffafd35e4567e6bc90f46b8c75f501dddf9
Author: Kajetan Puchalski <kajetan.puchalski at arm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M flang/CMakeLists.txt
M llvm/CMakeLists.txt
Log Message:
-----------
[CMake] Support using precompiled headers with ccache in flang (#136856)
In order for precompiled headers to work with ccache, a specific flag
needs to be passed to the compiler and ccache's sloppiness configuration
option needs to be set appropriately.
Due to issues with configuring CMake on certain Windows platforms, set
the required ccache option only on non-Windows systems for the time
being.
-----
Signed-off-by: Kajetan Puchalski <kajetan.puchalski at arm.com>
Commit: d43ce3504891edde937d68f6158dfacfa76de77a
https://github.com/llvm/llvm-project/commit/d43ce3504891edde937d68f6158dfacfa76de77a
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/utils/TableGen/GlobalISelEmitter.cpp
Log Message:
-----------
[TableGen][GISel] Allow isTrivialOperatorNode to import patterns with isStore and a memory VT. (#137080)
This removes the need to explicitly set isTruncStore on truncstorei8 and
other similar PatFrags that include truncstore in their frags DAG.
This allows some new patterns to be imported for AMDGPU as you can see
in the changed test.
The extra isTruncStore were added in ae2b36e8bdfa6, along with some
other tablegen changes to look for MemoryVT along with isTruncStore. I
did not remove the code, because I'm not sure if any out of tree users
have become dependent on it. It's no longer exercised in tree.
Commit: 4f5cfa81dcbd51d5416022d1872b04a9f376331b
https://github.com/llvm/llvm-project/commit/4f5cfa81dcbd51d5416022d1872b04a9f376331b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast.gfx6.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/cc-update.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs-r600.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernel-argument-alignment.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/lower-kernargs.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
Log Message:
-----------
AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)
These were added to the migration from v4 to v5 and should be removed
now
that the default has changed.
Commit: 72cc868c65b0641f23d1fb0518a8503c73ecdb5a
https://github.com/llvm/llvm-project/commit/72cc868c65b0641f23d1fb0518a8503c73ecdb5a
Author: Shafik Yaghmour <shafik.yaghmour at intel.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/lib/Serialization/ASTReader.cpp
Log Message:
-----------
[Clang][NFC] Move temp variable back into the source (#137095)
Static analysis flagged this code b/c we are copying the temp variable
back in when we could move it instead.
Commit: b278aa31979f22409ee73d413a739394366fe2ff
https://github.com/llvm/llvm-project/commit/b278aa31979f22409ee73d413a739394366fe2ff
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
Log Message:
-----------
[RISCV] Make xrivosvizip interleave2 and deinterleave2 undef safe (#136733)
We're duplicating uses here, so we need to freeze the inputs.
---------
Co-authored-by: Luke Lau <luke_lau at icloud.com>
Commit: a903c7b7f5d1cb8d72c170d494d94dc251fc7204
https://github.com/llvm/llvm-project/commit/a903c7b7f5d1cb8d72c170d494d94dc251fc7204
Author: RolandF77 <55763885+RolandF77 at users.noreply.github.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsPowerPC.td
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
M llvm/test/CodeGen/PowerPC/dmr-enable.ll
Log Message:
-----------
[PowerPC] Intrinsics and tests for dmr insert/extract (#135653)
Add some intrinsics and LIT tests for PPC dmr insert/extract
instructions.
Commit: 2ca071b1decf006a31385c75478b57013964e49a
https://github.com/llvm/llvm-project/commit/2ca071b1decf006a31385c75478b57013964e49a
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/Target/AArch64/AArch64InstrAtomics.td
M llvm/lib/Target/BPF/BPFInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/GlobalISelEmitter.cpp
Log Message:
-----------
[TableGen][RISCV][AArch64][GISel] Properly implement isAnyExtLoad/isSignExtLoad/isZeroExtLoad for IsAtomic in SelectionDAG. (#137096)
Support isAnyExtLoad() for IsAtomic in GISel.
Modify atomic_load_az* to check for extload or zextload. And rename to
atomic_load_azext*
Add atomic_load_asext* and use in RISC-V. I used "asext" rather than
"as" so it wouldn't be confused with the word "as".
Commit: feaa5aa840dcda69bd4133536142be882f696114
https://github.com/llvm/llvm-project/commit/feaa5aa840dcda69bd4133536142be882f696114
Author: Akira Hatanaka <ahatanak at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/lib/AST/ExprConstant.cpp
M clang/test/SemaCXX/constexpr-vectors-access-elements.cpp
Log Message:
-----------
Fix a crash in constant evaluation of ExtVectorElementExprs (#136771)
Handle the case where the base expression is a pointer to a vector type.
rdar://149223362
Commit: c7fbabaf87f9411fbcc48a33efaa76f0f03135e9
https://github.com/llvm/llvm-project/commit/c7fbabaf87f9411fbcc48a33efaa76f0f03135e9
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/test/CodeGenCXX/mangle-template.cpp
Log Message:
-----------
[clang] fix typo in CHECK line
Commit: 0ab330b344dc6333907542bb6267a9bd13e94b07
https://github.com/llvm/llvm-project/commit/0ab330b344dc6333907542bb6267a9bd13e94b07
Author: Eric Astor <epastor at google.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/MC/MCParser/MasmParser.cpp
M llvm/test/tools/llvm-ml/macro_function.asm
Log Message:
-----------
[ms] [llvm-ml] Add support for `@CatStr` built-in function symbol (#130781)
MASM supports some built-in macro-type functions.
We start our support for these with `@CatStr`, one of the more commonly used.
Commit: 72b2d4d758501ab9bf203e82be5b612f48c863b4
https://github.com/llvm/llvm-project/commit/72b2d4d758501ab9bf203e82be5b612f48c863b4
Author: stma247 <184293860+stma247 at users.noreply.github.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
A llvm/test/tools/llvm-cov/branch-export-lcov-unify-instances.test
M llvm/test/tools/llvm-cov/branch-export-lcov.test
M llvm/tools/llvm-cov/CodeCoverage.cpp
M llvm/tools/llvm-cov/CoverageExporterLcov.cpp
M llvm/tools/llvm-cov/CoverageViewOptions.h
Log Message:
-----------
[llvm-cov] Fix branch counts of template functions (second attempt) (#135074)
This PR is a second attempt for issue #111743 to finish reverted PR
#113925.
Added option "--unify-instantiations" to llvm-cov export to combine branch execution counts of C++ template instantiations. Fix non-deterministic behavior.
Commit: fe90b9dac76dd3efcb24f747007c68ee2bc27630
https://github.com/llvm/llvm-project/commit/fe90b9dac76dd3efcb24f747007c68ee2bc27630
Author: Camsyn <camsyn at foxmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M compiler-rt/lib/asan/asan_report.cpp
Log Message:
-----------
[ASan] Limits the conditions of the deadlock patch (#137127)
PR #131756 introduced a patch to fix a deadlock between LSan and ASan.
The relevant deadlock only occurs when LSan is enabled and
`dl_iterate_phdr` is used for Stop-the-World, i.e., under the condition
`CAN_SANITIZE_LEAKS && (SANITIZER_LINUX || SANITIZER_NETBSD)`.
Therefore, this commit also sets the effective condition of this patch
to the above condition, avoiding unnecessary problems in other
environments, e.g., stack overflow on MSVC/Windows.
Commit: e329b6c530f30bc645ea188cd25068c6759eb16a
https://github.com/llvm/llvm-project/commit/e329b6c530f30bc645ea188cd25068c6759eb16a
Author: Finn Plummer <canadienfinn at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/include/clang/Parse/ParseHLSLRootSignature.h
M clang/lib/Parse/ParseHLSLRootSignature.cpp
Log Message:
-----------
[NFC][RootSignatures] Conform to new std::optional calling conventions (#136747)
- It was determined to define the parsing methods much more inline with
a recursive descent parser to follow the EBNF notation better
- As part of this change, we decided to go with a calling convention to
the parse.* methods of returning an optional rather than a bool and a
reference to the parsed struct
This is a clean-up task from
https://github.com/llvm/llvm-project/pull/133800
Commit: 565a075909046f74c2fbb7713419518464599a4e
https://github.com/llvm/llvm-project/commit/565a075909046f74c2fbb7713419518464599a4e
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M flang-rt/lib/cuda/allocator.cpp
M flang-rt/unittests/Runtime/CUDA/Allocatable.cpp
Log Message:
-----------
[flang][cuda][rt] Track asynchronous allocation stream for deallocation (#137073)
When an asynchronous allocation is made, we call `cudaMallocAsync` with
a stream. For deallocation, we need to call `cudaFreeAsync` with the
same stream. in order to achieve that, we need to track the allocation
and their respective stream.
This patch adds a simple sorted array of asynchronous allocations. A
binary search is performed to retrieve the allocation when deallocation
is needed.
Commit: e78b763568e47e685926614195c3075afa35668c
https://github.com/llvm/llvm-project/commit/e78b763568e47e685926614195c3075afa35668c
Author: Scott Linder <scott.linder at amd.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/difile_absolute_filenames.ll
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/difile_absolute_filenames.ll.expected
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.globals.expected
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.transitiveglobals.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/difile_absolute_filenames.test
M llvm/utils/UpdateTestChecks/common.py
Log Message:
-----------
update_test_checks: Relax DIFile filename checks (#135692)
Avoid baking in absolute paths in check lines generated for DIFile
metadata. Generated test checks cannot be sensitive to absolute paths
anyway, as those vary with the environment, but there could be
situations where some sensitivity to partial paths is required for
certain tests. This implementation just assumes such tests aren't worth
the effort to support, but it could be supported in the future.
This is most useful for update_cc_test_checks with debug info enabled,
where the test writer cannot manipulate the paths within the generated
IR directly.
Commit: 2de936b6eb38e7a37224a97c2a22aa79b9dfb9dc
https://github.com/llvm/llvm-project/commit/2de936b6eb38e7a37224a97c2a22aa79b9dfb9dc
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
M mlir/test/Dialect/Vector/vector-emulate-narrow-type-unaligned.mlir
M mlir/test/Dialect/Vector/vector-emulate-narrow-type.mlir
Log Message:
-----------
[mlir][vector] Fix emulation of "narrow" type `vector.store` (#133231)
Below are two examples of "narrow" `vector.stores`. The first example
does not require partial stores and hence no RMW stores. This is
currently emulated correctly.
```mlir
func.func @example_1(%arg0: vector<4xi2>) {
%0 = memref.alloc() : memref<13xi2>
%c4 = arith.constant 4 : index
vector.store %arg0, %0[%c4] : memref<13xi2>, vector<4xi2>
return
}
```
The second example requires a partial (and hence RMW) store due to the
offset pointing outside the emulated type boundary (`%c3`).
```mlir
func.func @example_2(%arg0: vector<4xi2>) {
%0 = memref.alloc() : memref<13xi2>
%c3 = arith.constant 3 : index
vector.store %arg0, %0[%c3] : memref<13xi2>, vector<4xi2>
return
}
```
This is currently incorrectly emulated as a single "full" store (note
that the offset is incorrect) instead of partial stores:
```mlir
func.func @example_2(%arg0: vector<4xi2>) {
%alloc = memref.alloc() : memref<4xi8>
%0 = vector.bitcast %arg0 : vector<4xi2> to vector<1xi8>
%c0 = arith.constant 0 : index
vector.store %0, %alloc[%c0] : memref<4xi8>, vector<1xi8>
return
}
```
The incorrect emulation stems from this simplified (i.e. incomplete)
calculation of the front padding:
```cpp
std::optional<int64_t> foldedNumFrontPadElems =
isDivisibleInSize ? 0
: getConstantIntValue(linearizedInfo.intraDataOffset);
```
Since `isDivisibleInSize` is `true` (i8 / i2 = 4):
* front padding is set to `0` and, as a result,
* the input offset (`%c3`) is ignored, and
* we incorrectly assume that partial stores won't be needed.
Note that in both examples we are storing `vector<4xi2>` into
`memref<13xi2>` (note _different_ trailing dims) and hence partial
stores might in fact be required. The condition above is updated to:
```cpp
std::optional<int64_t> foldedNumFrontPadElems =
(isDivisibleInSize && trailingDimsMatch)
? 0
: getConstantIntValue(linearizedInfo.intraDataOffset);
```
This change ensures that the input offset is properly taken into
account, which fixes the issue. It doesn't affect `@example1`.
Additional comments are added to clarify the current logic.
Commit: 7a276c8acfc3977de8c3ceb0af67fcf603834946
https://github.com/llvm/llvm-project/commit/7a276c8acfc3977de8c3ceb0af67fcf603834946
Author: Dave Lee <davelee.com at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCTypeEncodingParser.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCTypeEncodingParser.h
Log Message:
-----------
[lldb] Fix logic error in AppleObjCTypeEncodingParser (#137067)
Fixes parsing of an ObjC type encoding such as `{?="a""b"}`. Parsing of such a type
encoding would lead to an assert. This was observed when running `language objc
class-table dump`.
The function `ReadQuotedString` consumes the closing quote, however one of its two
callers (`ReadStructElement`) was also consuming a quote. For the above type encoding,
where two quoted strings occur back to back, the parser would unintentionally consume
the opening quote of the second quoted string - leaving the remaining text with an
unbalanced quote.
This changes fixes `ReadStructElement` to not consume a quote after calling
`ReadQuotedString`.
For callers to know whether a string was successfully parsed, `ReadQuotedString` now
returns an optional string.
Commit: 8832a5950f3b62331842ecb2f3a68f33732822eb
https://github.com/llvm/llvm-project/commit/8832a5950f3b62331842ecb2f3a68f33732822eb
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/lib/Frontend/CompilerInstance.cpp
Log Message:
-----------
[clang] Enable making the module build stack thread-safe (#137059)
This PR makes another piece of the
`CompilerInstance::cloneForModuleCompile()` result thread-safe: the
module build stack. This data structure is used to detect cyclic
dependencies between modules. The problem is that it uses
`FullSourceLoc` which refers to the `SourceManager` of the parent
`CompilerInstance`: if two threads happen to execute `CompilerInstance`s
cloned from the same parent concurrently, and both discover a dependency
cycle, they may concurrently access the parent `SourceManager` when
emitting the diagnostic, creating a data race.
In this PR, we prevent this by keeping the stack empty and moving the
responsibility of cycle detection to the client. The client can recreate
the same module build stack externally and ensure thread-safety by
enforcing mutual exclusion.
Commit: 22700c472e168cc46ef6eff381a535100d166cdc
https://github.com/llvm/llvm-project/commit/22700c472e168cc46ef6eff381a535100d166cdc
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang-tools-extra/clangd/XRefs.cpp
M clang-tools-extra/clangd/unittests/CallHierarchyTests.cpp
M clang/bindings/python/clang/cindex.py
A clang/bindings/python/tests/cindex/INPUTS/a.inc
A clang/bindings/python/tests/cindex/INPUTS/b.inc
A clang/bindings/python/tests/cindex/INPUTS/testfile.c
M clang/bindings/python/tests/cindex/test_file.py
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/BuiltinsAArch64.def
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Parse/ParseHLSLRootSignature.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/CodeGen/CGClass.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/Frontend/CompilerInstance.cpp
M clang/lib/Headers/arm_acle.h
M clang/lib/Parse/ParseHLSLRootSignature.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaObjC.cpp
M clang/lib/Sema/SemaObjCProperty.cpp
M clang/lib/Sema/SemaOpenACCClause.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Serialization/ASTReader.cpp
A clang/test/AST/ByteCode/i686.cpp
M clang/test/AST/ByteCode/records.cpp
M clang/test/CodeGen/AArch64/gcs.c
A clang/test/CodeGenCUDASPIRV/printf.cu
M clang/test/CodeGenCXX/mangle-template.cpp
M clang/test/Format/lit.local.cfg
A clang/test/Sema/implicit-void-ptr-cast.c
M clang/test/SemaCXX/constexpr-vectors-access-elements.cpp
M compiler-rt/lib/asan/asan_report.cpp
A compiler-rt/test/tsan/stack_race3.cpp
M flang-rt/lib/cuda/allocator.cpp
M flang-rt/unittests/Runtime/CUDA/Allocatable.cpp
M flang/CMakeLists.txt
A flang/docs/FortranStandardsSupport.md
M flang/docs/index.md
M flang/lib/Optimizer/CodeGen/LowerRepackArrays.cpp
M flang/lib/Optimizer/HLFIR/Transforms/InlineElementals.cpp
M flang/lib/Optimizer/HLFIR/Transforms/InlineHLFIRAssign.cpp
M flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
M flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/AssumedRankOpConversion.cpp
M flang/lib/Optimizer/Transforms/ConstantArgumentGlobalisation.cpp
M flang/lib/Optimizer/Transforms/SimplifyFIROperations.cpp
M flang/lib/Optimizer/Transforms/StackArrays.cpp
R libc/test/src/math/performance_testing/BinaryOpSingleOutputPerf.h
M libc/test/src/math/performance_testing/CMakeLists.txt
A libc/test/src/math/performance_testing/PerfTest.h
R libc/test/src/math/performance_testing/SingleInputSingleOutputPerf.h
M libc/test/src/math/performance_testing/ceilf_perf.cpp
M libc/test/src/math/performance_testing/cosf_perf.cpp
M libc/test/src/math/performance_testing/exp10f16_perf.cpp
M libc/test/src/math/performance_testing/exp2f16_perf.cpp
M libc/test/src/math/performance_testing/exp2f_perf.cpp
M libc/test/src/math/performance_testing/expf16_perf.cpp
M libc/test/src/math/performance_testing/expf_perf.cpp
M libc/test/src/math/performance_testing/expm1f_perf.cpp
M libc/test/src/math/performance_testing/fabsf_perf.cpp
M libc/test/src/math/performance_testing/floorf_perf.cpp
M libc/test/src/math/performance_testing/fmod_perf.cpp
M libc/test/src/math/performance_testing/fmodf128_perf.cpp
M libc/test/src/math/performance_testing/fmodf16_perf.cpp
M libc/test/src/math/performance_testing/fmodf_perf.cpp
M libc/test/src/math/performance_testing/fmodl_perf.cpp
M libc/test/src/math/performance_testing/fmul_perf.cpp
M libc/test/src/math/performance_testing/fmull_perf.cpp
M libc/test/src/math/performance_testing/hypot_perf.cpp
M libc/test/src/math/performance_testing/hypotf16_perf.cpp
M libc/test/src/math/performance_testing/hypotf_perf.cpp
M libc/test/src/math/performance_testing/log10f_perf.cpp
M libc/test/src/math/performance_testing/log1pf_perf.cpp
M libc/test/src/math/performance_testing/log2f_perf.cpp
M libc/test/src/math/performance_testing/logbf_perf.cpp
M libc/test/src/math/performance_testing/logf_perf.cpp
M libc/test/src/math/performance_testing/max_min_funcs_perf.cpp
M libc/test/src/math/performance_testing/misc_basic_ops_perf.cpp
M libc/test/src/math/performance_testing/nearbyintf_perf.cpp
M libc/test/src/math/performance_testing/nearest_integer_funcs_perf.cpp
M libc/test/src/math/performance_testing/rintf_perf.cpp
M libc/test/src/math/performance_testing/roundf_perf.cpp
M libc/test/src/math/performance_testing/sinf_perf.cpp
M libc/test/src/math/performance_testing/sqrtf128_perf.cpp
M libc/test/src/math/performance_testing/sqrtf_perf.cpp
M libc/test/src/math/performance_testing/truncf_perf.cpp
R libclc/amdgpu/lib/SOURCES_3.9
R libclc/amdgpu/lib/SOURCES_4.0
R libclc/amdgpu/lib/SOURCES_5.0
R libclc/amdgpu/lib/shared/vload_half_helpers.ll
R libclc/amdgpu/lib/shared/vstore_half_helpers.ll
M libclc/cmake/modules/AddLibclc.cmake
M libclc/generic/include/clc/clc.h
R libclc/generic/include/clc/clcmacros.h
M libclc/generic/include/clc/shared/vload.h
M libclc/generic/include/clc/shared/vstore.h
M libclc/generic/lib/shared/vload.cl
M libclc/generic/lib/shared/vload_half.inc
M libclc/generic/lib/shared/vstore.cl
M libclc/generic/lib/shared/vstore_half.inc
R libclc/ptx/lib/SOURCES_3.9
R libclc/ptx/lib/SOURCES_4.0
R libclc/ptx/lib/SOURCES_5.0
R libclc/ptx/lib/shared/vload_half_helpers.ll
R libclc/ptx/lib/shared/vstore_half_helpers.ll
M libcxx/include/__ranges/to.h
M libcxx/test/libcxx/ranges/range.utility/range.utility.conv/to.static_assert.verify.cpp
M lldb/include/lldb/Interpreter/OptionValueEnumeration.h
M lldb/source/Interpreter/OptionValueEnumeration.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCTypeEncodingParser.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCTypeEncodingParser.h
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/Process/Utility/CMakeLists.txt
A lldb/source/Plugins/Process/Utility/RegisterContextDarwin_riscv32.cpp
A lldb/source/Plugins/Process/Utility/RegisterContextDarwin_riscv32.h
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/test/API/commands/process/reverse-continue/TestReverseContinueNotSupported.py
M lldb/test/API/commands/settings/TestSettings.py
A lldb/test/API/macosx/riscv32-corefile/Makefile
A lldb/test/API/macosx/riscv32-corefile/TestRV32MachOCorefile.py
A lldb/test/API/macosx/riscv32-corefile/create-empty-riscv-corefile.cpp
M llvm/CMakeLists.txt
M llvm/include/llvm/IR/IntrinsicsPowerPC.td
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/MC/MCParser/MasmParser.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrAtomics.td
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/BPF/BPFInstrInfo.td
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.h
M llvm/lib/Target/SystemZ/SystemZInstrFP.td
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
M llvm/lib/Transforms/Instrumentation/SanitizerBinaryMetadata.cpp
M llvm/lib/Transforms/Instrumentation/ThreadSanitizer.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/select-const-vector.mir
M llvm/test/CodeGen/AArch64/sve-varargs-caller-broken.ll
M llvm/test/CodeGen/AArch64/sve-varargs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast.gfx6.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/cc-update.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs-r600.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernel-argument-alignment.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.AFLCustomIRMutator.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/lower-kernargs.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/ARM/popcnt.ll
M llvm/test/CodeGen/PowerPC/dmr-enable.ll
A llvm/test/CodeGen/PowerPC/vsx-fma-m-early.ll
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
M llvm/test/CodeGen/RISCV/pr56457.ll
M llvm/test/CodeGen/RISCV/pr95271.ll
M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/sextw-removal.ll
M llvm/test/CodeGen/SystemZ/fp-abs-01.ll
M llvm/test/CodeGen/SystemZ/fp-abs-02.ll
M llvm/test/CodeGen/SystemZ/fp-abs-03.ll
M llvm/test/CodeGen/SystemZ/fp-abs-04.ll
M llvm/test/CodeGen/SystemZ/fp-copysign-01.ll
M llvm/test/CodeGen/SystemZ/fp-copysign-02.ll
M llvm/test/CodeGen/SystemZ/fp-copysign-03.ll
M llvm/test/CodeGen/SystemZ/fp-mul-08.ll
M llvm/test/CodeGen/SystemZ/fp-mul-10.ll
M llvm/test/CodeGen/SystemZ/fp-neg-01.ll
M llvm/test/CodeGen/SystemZ/fp-neg-02.ll
M llvm/test/CodeGen/Thumb2/mve-ctpop.ll
M llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
M llvm/test/CodeGen/X86/build-vector-128.ll
M llvm/test/CodeGen/X86/build-vector-256.ll
M llvm/test/CodeGen/X86/build-vector-512.ll
A llvm/test/CodeGen/X86/buildvec-widen-dotproduct.ll
M llvm/test/CodeGen/X86/extractelement-load.ll
M llvm/test/CodeGen/X86/pr40891.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
M llvm/test/CodeGen/X86/vector-trunc.ll
M llvm/test/Instrumentation/ThreadSanitizer/capture.ll
A llvm/test/Transforms/GlobalOpt/X86/preserve-dbgloc-of-load-store-to-bool.ll
A llvm/test/Transforms/GlobalOpt/malloc-promote-atomic.ll
M llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll
M llvm/test/Transforms/LoopVectorize/X86/pr51366-sunk-instruction-used-outside-of-loop.ll
M llvm/test/Transforms/LoopVectorize/X86/small-size.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll
A llvm/test/Transforms/PGOProfile/memprof-dump-matched-alloc-site.ll
M llvm/test/Transforms/PGOProfile/memprof-dump-matched-call-sites.ll
M llvm/test/Transforms/PGOProfile/memprof.ll
M llvm/test/Transforms/PhaseOrdering/X86/blendv-select.ll
A llvm/test/Transforms/VectorCombine/pr132563.ll
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/difile_absolute_filenames.ll
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/difile_absolute_filenames.ll.expected
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.globals.expected
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.transitiveglobals.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/difile_absolute_filenames.test
A llvm/test/tools/llvm-cov/branch-export-lcov-unify-instances.test
M llvm/test/tools/llvm-cov/branch-export-lcov.test
M llvm/test/tools/llvm-ml/macro_function.asm
M llvm/tools/llvm-cov/CodeCoverage.cpp
M llvm/tools/llvm-cov/CoverageExporterLcov.cpp
M llvm/tools/llvm-cov/CoverageViewOptions.h
M llvm/unittests/TargetParser/TripleTest.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/GlobalISelEmitter.cpp
M llvm/utils/UpdateTestChecks/common.py
M llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn
M mlir/include/mlir/Transforms/GreedyPatternRewriteDriver.h
M mlir/include/mlir/Transforms/Passes.td
M mlir/lib/Dialect/Affine/TransformOps/AffineTransformOps.cpp
M mlir/lib/Dialect/Affine/Transforms/AffineDataCopyGeneration.cpp
M mlir/lib/Dialect/Affine/Transforms/SimplifyAffineStructures.cpp
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/lib/Dialect/Affine/Utils/Utils.cpp
M mlir/lib/Dialect/Arith/Transforms/IntRangeOptimizations.cpp
M mlir/lib/Dialect/Bufferization/Transforms/BufferDeallocationSimplification.cpp
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp
M mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp
M mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Transform/IR/TransformOps.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
M mlir/lib/Reducer/ReductionTreePass.cpp
M mlir/lib/Transforms/Canonicalizer.cpp
M mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/verifier.mlir
M mlir/test/Dialect/Vector/canonicalize.mlir
M mlir/test/Dialect/Vector/vector-emulate-narrow-type-unaligned.mlir
M mlir/test/Dialect/Vector/vector-emulate-narrow-type.mlir
M mlir/test/lib/Dialect/Affine/TestAffineDataCopy.cpp
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
M openmp/runtime/src/kmp_tasking.cpp
M polly/lib/CodeGen/BlockGenerators.cpp
M polly/lib/CodeGen/CodeGeneration.cpp
M polly/lib/CodeGen/IslExprBuilder.cpp
M polly/lib/CodeGen/IslNodeBuilder.cpp
M polly/lib/CodeGen/LoopGenerators.cpp
M polly/lib/CodeGen/LoopGeneratorsGOMP.cpp
M polly/lib/CodeGen/LoopGeneratorsKMP.cpp
M polly/lib/CodeGen/PerfMonitor.cpp
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
rebase
Created using spr 1.3.4
Compare: https://github.com/llvm/llvm-project/compare/1e3a7d1eac42...22700c472e16
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