[all-commits] [llvm/llvm-project] f261f1: [SelectionDAG][RISCV] Teach computeKnownBits to us...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f261f1406d4870410d3c9e61903e65ffd427d8ec
      https://github.com/llvm/llvm-project/commit/f261f1406d4870410d3c9e61903e65ffd427d8ec
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-04-24 (Thu, 24 Apr 2025)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    A llvm/test/CodeGen/RISCV/atomic-load-zext.ll

  Log Message:
  -----------
  [SelectionDAG][RISCV] Teach computeKnownBits to use range metadata for atomic_load. (#137119)

And teach SelectionDAGBuilder to get the range metadata in
visitAtomicLoad.

This allows us to recognize that sign extending a byte load of a
boolean value from memory will produce zeros for the extended bits.
This allow us to remove an AND on RISC-V.

Tests copied from #136502 with range metadata added to i1 cases.
Some of the test effects overlap with #136502, but that patch can't
handle the acquire or seq_cst cases with the Zalasr extension. We
only have sign extending versions of those loads.



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