[all-commits] [llvm/llvm-project] 6e3b16: [AArch64][GlobalISel] Fix EXTRACT_SUBREG reg class...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6e3b16bec3a3384d8d2deb23d770d1d6a7357c50
      https://github.com/llvm/llvm-project/commit/6e3b16bec3a3384d8d2deb23d770d1d6a7357c50
  Author: David Green <david.green at arm.com>
  Date:   2025-04-24 (Thu, 24 Apr 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-shift-imm.mir
    M llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] Fix EXTRACT_SUBREG reg classes in patterns to generate MULL. (#136083)

This fixes the GISel warning "Skipped pattern: EXTRACT_SUBREG child #0
could not be coerced to a register class" by ensuring the register class
is correct for the EXTRACT_SUBREG patterns. This most notably allows
UMADDL / SMADDL patterns to be imported (many still do not work as a
PatLeaf on a child cannot be generated at the moment).



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