[all-commits] [llvm/llvm-project] 2ca071: [TableGen][RISCV][AArch64][GISel] Properly impleme...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2ca071b1decf006a31385c75478b57013964e49a
      https://github.com/llvm/llvm-project/commit/2ca071b1decf006a31385c75478b57013964e49a
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-04-24 (Thu, 24 Apr 2025)

  Changed paths:
    M llvm/include/llvm/Target/TargetSelectionDAG.td
    M llvm/lib/Target/AArch64/AArch64InstrAtomics.td
    M llvm/lib/Target/BPF/BPFInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
    M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
    M llvm/utils/TableGen/GlobalISelEmitter.cpp

  Log Message:
  -----------
  [TableGen][RISCV][AArch64][GISel] Properly implement isAnyExtLoad/isSignExtLoad/isZeroExtLoad for IsAtomic in SelectionDAG. (#137096)

Support isAnyExtLoad() for IsAtomic in GISel.

Modify atomic_load_az* to check for extload or zextload. And rename to
atomic_load_azext*

Add atomic_load_asext* and use in RISC-V. I used "asext" rather than
"as" so it wouldn't be confused with the word "as".



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