[all-commits] [llvm/llvm-project] 91edbe: [lldb][LoongArch] Fix expression function call fai...
Iris Shi via All-commits
all-commits at lists.llvm.org
Thu Apr 24 04:01:47 PDT 2025
Branch: refs/heads/users/el-ev/cleanup-c-fn-noproto
Home: https://github.com/llvm/llvm-project
Commit: 91edbe223177504cf878340f37a36dfcee349cab
https://github.com/llvm/llvm-project/commit/91edbe223177504cf878340f37a36dfcee349cab
Author: wanglei <wanglei at loongson.cn>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
Log Message:
-----------
[lldb][LoongArch] Fix expression function call failure
After upgrading the default code model from small to medium on
LoongArch, function calls using expression may fail. This is because the
function call instruction has changed from `bl` to `pcalau18i + jirl`,
but `RuntimeDyld` does not handle out-of-range jumps for this
instruction sequence.
This patch fixes: #136561
Reviewed By: SixWeining
Pull Request: https://github.com/llvm/llvm-project/pull/136563
Commit: 8a57df6a5210d0c54ed482eb7230b7689a1f9cb9
https://github.com/llvm/llvm-project/commit/8a57df6a5210d0c54ed482eb7230b7689a1f9cb9
Author: Allin Lee <60502081+AllinLeeYL at users.noreply.github.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/IR/Value.h
M llvm/lib/IR/Value.cpp
A llvm/test/tools/llvm-extract/extract-unnamed-bb.ll
M llvm/tools/llvm-extract/llvm-extract.cpp
Log Message:
-----------
[llvm-extract] support unnamed bbs. (#135140)
Dear developer:
I have recently working with LLVM IR and I want to isolate basic blocks
using the command "llvm-extract". However, I found that the command
option "llvm-extract --bb func_name:bb_name" will only function when
dumping source code into IRs with options "-fno-discard-value-names".
That is to say, the "llvm-extract" command cannot support unnamed basic
blocks, which is a default output of the compiler. So, I made these
changes and hope they will make LLVM better.
Best regards,
Co-authored-by: Yilin Li <allinleeme at gmail.com>
Commit: 6db447f824d46956172b104f08105b25f9428f55
https://github.com/llvm/llvm-project/commit/6db447f824d46956172b104f08105b25f9428f55
Author: Iris Shi <0.0 at owo.li>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/test/Transforms/InstCombine/clamp-to-minmax.ll
A llvm/test/Transforms/InstCombine/max-min-canonicalize.ll
M llvm/test/Transforms/InstCombine/max_known_bits.ll
M llvm/test/Transforms/InstCombine/minmax-fold.ll
M llvm/test/Transforms/InstCombine/minmax-intrinsics.ll
M llvm/test/Transforms/InstCombine/sadd_sat.ll
M llvm/test/Transforms/InstCombine/select-min-max.ll
Log Message:
-----------
[InstCombine] Canonicalize `max(min(X, MinC), MaxC) -> min(max(X, MaxC), MinC)` (#136665)
Closes #121870.
https://alive2.llvm.org/ce/z/WjmAjz
https://alive2.llvm.org/ce/z/4KCjgL
Commit: 4a58071d87265dfccba72134b25cf4d1595d98c5
https://github.com/llvm/llvm-project/commit/4a58071d87265dfccba72134b25cf4d1595d98c5
Author: Diana Picus <Diana-Magda.Picus at amd.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineFrameInfo.h
M llvm/include/llvm/CodeGen/TargetFrameLowering.h
M llvm/lib/CodeGen/PrologEpilogInserter.cpp
M llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
A llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir
A llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll
A llvm/test/CodeGen/AMDGPU/vgpr-blocks-funcinfo.mir
M llvm/unittests/Target/AMDGPU/CMakeLists.txt
A llvm/unittests/Target/AMDGPU/LiveRegUnits.cpp
Log Message:
-----------
[AMDGPU] Support block load/store for CSR (#130013)
Add support for using the existing `SCRATCH_STORE_BLOCK` and
`SCRATCH_LOAD_BLOCK` instructions for saving and restoring callee-saved
VGPRs. This is controlled by a new subtarget feature, `block-vgpr-csr`.
It does not include WWM registers - those will be saved and restored
individually, just like before. This patch does not change the ABI.
Use of this feature may lead to slightly increased stack usage, because
the memory is not compacted if certain registers don't have to be
transferred (this will happen in practice for calling conventions where
the callee and caller saved registers are interleaved in groups of 8).
However, if the registers at the end of the block of 32 don't have to be
transferred, we don't need to use a whole 128-byte stack slot - we can
trim some space off the end of the range.
In order to implement this feature, we need to rely less on the
target-independent code in the PrologEpilogInserter, so we override
several new methods in `SIFrameLowering`. We also add new pseudos,
`SI_BLOCK_SPILL_V1024_SAVE/RESTORE`.
One peculiarity is that both the SI_BLOCK_V1024_RESTORE pseudo and the
SCRATCH_LOAD_BLOCK instructions will have all the registers that are not
transferred added as implicit uses. This is done in order to inform
LiveRegUnits that those registers are not available before the restore
(since we're not really restoring them - so we can't afford to scavenge
them). Unfortunately, this trick doesn't work with the save, so before
the save all the registers in the block will be unavailable (see the
unit test).
Commit: 48585caf727004678617dc34fa50383c3f4eb2de
https://github.com/llvm/llvm-project/commit/48585caf727004678617dc34fa50383c3f4eb2de
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/test/Transforms/InstCombine/icmp.ll
Log Message:
-----------
InstCombine: Avoid counting uses of constants (#136566)
Logically it does not matter; getFreelyInvertedImpl doesn't
depend on the value for the m_ImmConstant case.
This use count logic should probably sink into getFreelyInvertedImpl,
every use of this appears to just be a hasOneUse or hasNUse count,
so this could change to just be a use count threshold.
Commit: a1331704752c46cd4d954eb8682af230937fe5a6
https://github.com/llvm/llvm-project/commit/a1331704752c46cd4d954eb8682af230937fe5a6
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/Target/AMDGPU/BUILD.gn
Log Message:
-----------
[gn build] Port 4a58071d8726
Commit: 3cd6b86cc1e1fd1d8d62ca1bcb8498362a4f7b68
https://github.com/llvm/llvm-project/commit/3cd6b86cc1e1fd1d8d62ca1bcb8498362a4f7b68
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachinePipeliner.h
M llvm/lib/CodeGen/MachinePipeliner.cpp
A llvm/test/CodeGen/Hexagon/swp-alias-cross-iteration.mir
A llvm/test/CodeGen/Hexagon/swp-no-alias.mir
Log Message:
-----------
[MachinePipeliner] Use AliasAnalysis properly when analyzing loop-carried dependencies (#136691)
MachinePipeliner uses AliasAnalysis to collect loop-carried memory
dependencies. To analyze loop-carried dependencies, we need to
explicitly tell AliasAnalysis that the values may come from different
iterations. Before this patch, MachinePipeliner didn't do this, so some
loop-carried dependencies might be missed. For example, in the following
case, there is a loop-carried dependency from the load to the store, but
it wasn't considered.
```
def @f(ptr noalias %p0, ptr noalias %p1) {
entry:
br label %body
loop:
%idx0 = phi ptr [ %p0, %entry ], [ %p1, %body ]
%idx1 = phi ptr [ %p1, %entry ], [ %p0, %body ]
%v0 = load %idx0
...
store %v1, %idx1
...
}
```
Further, the handling of the underlying objects was not sound. If there
is no information about memory operands (i.e., `memoperands()` is
empty), it must be handled conservatively. However, Machinepipeliner
uses a dummy value (namely `UnknownValue`). It is distinguished from
other "known" objects, causing necessary dependencies to be missed.
(NOTE: in such cases, `buildSchedGraph` adds non-loop-carried
dependencies correctly, so perhaps a critical problem has not occurred.)
This patch fixes the above problems. This change has increased false
dependencies that didn't exist before. Therefore, this patch also
introduces additional alias checks with the underlying objects.
Split off from #135148
Commit: 0de2f64e652a1b8c1e051635c98fb2b69c6b2c62
https://github.com/llvm/llvm-project/commit/0de2f64e652a1b8c1e051635c98fb2b69c6b2c62
Author: Alex Rønne Petersen <alex at alexrp.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/test/Driver/Xclangas.s
Log Message:
-----------
[clang] XFAIL the `Xclangas.s` test on AIX. (#136744)
Clang on AIX does not use the integrated assembler.
https://github.com/llvm/llvm-project/pull/100714#issuecomment-2822056054
Commit: 11a3de7e98785b0df8f2010fb22c10c0590d2707
https://github.com/llvm/llvm-project/commit/11a3de7e98785b0df8f2010fb22c10c0590d2707
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/IR/RuntimeLibcalls.def
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/ARM/popcnt.ll
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
M llvm/test/CodeGen/RISCV/pr56457.ll
M llvm/test/CodeGen/RISCV/pr95271.ll
M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/RISCV/sextw-removal.ll
M llvm/test/CodeGen/Thumb2/mve-ctpop.ll
Log Message:
-----------
[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall (#101786)
This is a reland of #99752 with the bug fixed (see test diff in the
third commit in this PR).
All `popcount` libcalls return `int`, but `ISD::CTPOP` returns the type
of the argument, which can be wider than `int`. The fix is to make DAG
legalizer pass the correct return type to `makeLibCall` and sign-extend
the result afterwards.
Original commit message:
The main change is adding CTPOP to `RuntimeLibcalls.def` to allow
targets to use LibCall action for CTPOP. DAG legalizers are changed
accordingly.
Pull Request: https://github.com/llvm/llvm-project/pull/101786
Commit: 8e9ff8ea51b5a734df1314bd87ddb8dab31c2fbd
https://github.com/llvm/llvm-project/commit/8e9ff8ea51b5a734df1314bd87ddb8dab31c2fbd
Author: Jerry-Ge <jerry.ge at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaUtilOps.td
M mlir/lib/Conversion/TosaToMLProgram/TosaToMLProgram.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-pipeline.mlir
M mlir/test/Conversion/TosaToMLProgram/tosa-to-mlprogram.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/level_check.mlir
M mlir/test/Dialect/Tosa/variables.mlir
Log Message:
-----------
[mlir][tosa] Align Variable ops to match with TOSA v1.0 spec (#130680)
- updated AnyType:$value to Tosa_Tensor:$input1 and Tosa_Tensor:$output1
for VariableWrite and VriableRead Operators
- updated description discrepancies
- note: in the TOSA spec, we had var_shape attr, but it's already
included
in the TypeAttr:$type in MLIR
Signed-off-by: Jerry Ge <jerry.ge at arm.com>
Commit: a7999f3fba49b7b5da08afb070841f792ea1c796
https://github.com/llvm/llvm-project/commit/a7999f3fba49b7b5da08afb070841f792ea1c796
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
Log Message:
-----------
[NFC][AArch64TTI] Refactor instCombineSVEVectorMul into simplifySVEIntrinsicBinOp.
Commit: 3c3fb357a0ed4dbf640bdb6c61db2a430f7eb298
https://github.com/llvm/llvm-project/commit/3c3fb357a0ed4dbf640bdb6c61db2a430f7eb298
Author: TatWai Chong <tatwai.chong at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
M mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/level_check.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/profile_pro_fp_unsupported.mlir
M mlir/test/Dialect/Tosa/profile_pro_int_unsupported.mlir
M mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
M mlir/test/Dialect/Tosa/verifier.mlir
Log Message:
-----------
[mlir][tosa] Enhance CONV3D & DEPTHWISE_CONV2D verifier (#135738)
Verify the correctness of pad, stride, dilation, and dimension of
input/weight/bias/output.
Adapt and extend the existing conv2d error_if function to support
additional convolution variants.
Commit: 8c47f23232fc8b547f643d379175f322d01e4cbd
https://github.com/llvm/llvm-project/commit/8c47f23232fc8b547f643d379175f322d01e4cbd
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/docs/SPIRVUsage.rst
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroup_matrix_multiply_accumulate/subgroup_matrix_multiply_accumulate_generic.ll
Log Message:
-----------
[SPIRV] Support for the SPV_INTEL_subgroup_matrix_multiply_accumulate SPIR-V extension (#135225)
Adds support for the SPV_INTEL_subgroup_matrix_multiply_accumulate
SPIR-V extension according to
https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_subgroup_matrix_multiply_accumulate.asciidoc
Commit: 15d8b3cae9debc2bd7d27ca92ff599ba9fb30da5
https://github.com/llvm/llvm-project/commit/15d8b3cae9debc2bd7d27ca92ff599ba9fb30da5
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrGISel.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/lower-neon-vector-fcmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vector-fcmp.mir
M llvm/test/CodeGen/AArch64/arm64-zip.ll
M llvm/test/CodeGen/AArch64/select_cc.ll
Log Message:
-----------
[LLVM][ISel][AArch64 Remove AArch64ISD::FCM##z nodes. (#135817)
We can easily select compare-to-zero instructions without dedicated
nodes. The test changes show opportunities that were previous missed
because of the redundant complexity.
Commit: 37e8c6c6ee7c809e45d0e5b61c601a0bb91ca1c4
https://github.com/llvm/llvm-project/commit/37e8c6c6ee7c809e45d0e5b61c601a0bb91ca1c4
Author: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M bolt/lib/Core/MCPlusBuilder.cpp
M bolt/unittests/Core/MCPlusBuilder.cpp
Log Message:
-----------
[BOLT] Do not return Def-ed registers from MCPlusBuilder::getUsedRegs (#129890)
Update the implementation of `MCPlusBuilder::getUsedRegs` to match its
description in the header file, add unit tests.
Commit: c93af22d124ed70742fb692886ff26d8786f8c2d
https://github.com/llvm/llvm-project/commit/c93af22d124ed70742fb692886ff26d8786f8c2d
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineConstantPoolLoads - remove duplicate SDLoc. NFC.
Commit: 720a91183b16f94876adaa831d0a49a04d31420a
https://github.com/llvm/llvm-project/commit/720a91183b16f94876adaa831d0a49a04d31420a
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/preserve-inbounds.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep.ll
Log Message:
-----------
[SeparateConstOffsetFromGEP] Preserve inbounds flag based on ValueTracking and NUW (#130617)
If we know that the initial GEP was inbounds, and we change it to a
sequence of GEPs from the same base pointer where every offset is
non-negative, then the new GEPs are inbounds.
We can also preserve inbounds if the inbounds GEP and the involved additions are NUW.
For SWDEV-516125.
Commit: b0524f332958b6e593868533127fd0651bdcf553
https://github.com/llvm/llvm-project/commit/b0524f332958b6e593868533127fd0651bdcf553
Author: Ben Shi <2283975856 at qq.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/Basic/Targets/AVR.h
M clang/test/CodeGen/avr/avr-inline-asm-constraints.c
M clang/test/CodeGen/avr/avr-unsupported-inline-asm-constraints.c
M llvm/test/CodeGen/AVR/inline-asm/inline-asm-invalid.ll
Log Message:
-----------
[clang][AVR] Improve compatibility of inline assembly with avr-gcc (#136534)
Allow the value 64 to be round up to 0 for constraint 'I'.
Commit: 717efc0a994dfc5b2ed65ddb13b47fb917c9a467
https://github.com/llvm/llvm-project/commit/717efc0a994dfc5b2ed65ddb13b47fb917c9a467
Author: Luke Lau <luke at igalia.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
Log Message:
-----------
[RISCV] Support disjoint RISCVISD::OR_VL in combineOp_VLToVWOp_VL (#136820)
This handles combining fixed-length disjoint ors to vwadd[u].wv, as was
done for scalable vectors in #86929.
vwadd[u].vv patterns need to be handled separately with a pattern in a
separate patch due to the extends being sunk, see #136716.
Commit: 2a9f77f6bd48d757b2d45aadcb6cf76ef4b4ef32
https://github.com/llvm/llvm-project/commit/2a9f77f6bd48d757b2d45aadcb6cf76ef4b4ef32
Author: Björn Pettersson <bjorn.a.pettersson at ericsson.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/Reassociate.cpp
A llvm/test/Transforms/Reassociate/canonicalize-made-change.ll
Log Message:
-----------
[Reassociate] Invalidate analysis passes after canonicalizeOperands (#136835)
When ranking operands for an expression tree the reassociate pass also
perform canonicalization, putting constants on the right hand side. Such
transforms was however not registered as modifying the IR. So at the end
of the pass, if not having made any other changes, the pass returned
that all analyses should be kept.
With this patch we make sure to set MadeChange to true when modifying
the IR via canonicalizeOperands. This is to make sure analyses such as
DemandedBits are properly invalidated when instructions are modified.
Commit: 71ce9e26aec00e4af27a69ccfab8ca1773ed7018
https://github.com/llvm/llvm-project/commit/71ce9e26aec00e4af27a69ccfab8ca1773ed7018
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Sema/AnalysisBasedWarnings.h
M clang/lib/Sema/AnalysisBasedWarnings.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaExpr.cpp
A clang/test/Analysis/pragma-diag-control.cpp
Log Message:
-----------
Control analysis-based diagnostics with #pragma (#136323)
Previously, analysis-based diagnostics (like -Wconsumed) had to be
enabled at file scope in order to be run at the end of each function
body. This meant that they did not respect #pragma clang diagnostic
enabling or disabling the diagnostic.
Now, these pragmas can control the diagnostic emission.
Fixes #42199
Commit: 05b7e97c78ba375cc146c67a4539446f8bcb880c
https://github.com/llvm/llvm-project/commit/05b7e97c78ba375cc146c67a4539446f8bcb880c
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M flang/examples/FeatureList/FeatureList.cpp
M flang/include/flang/Lower/DirectivesCommon.h
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Semantics/symbol.h
M flang/include/flang/Support/Fortran.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/rewrite-directives.cpp
Log Message:
-----------
[flang][OpenMP] Extend common::AtomicDefaultMemOrderType enumeration (#136312)
Add "Acquire" and "Release", and rename it to OmpMemoryOrderType, since
memory order type is a concept extending beyond the
ATOMIC_DEFAULT_MEM_ORDER clause.
When processing a REQUIRES directive (in rewrite-directives.cpp), do not
add Acquire or Release to ATOMIC constructs, because handling of those
types depends on the OpenMP version, which is not available in that
file. This issue will be addressed later.
Commit: 013aab40511bf56a856643105e42c4204fe58f45
https://github.com/llvm/llvm-project/commit/013aab40511bf56a856643105e42c4204fe58f45
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-binop.ll
A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-shift.ll
Log Message:
-----------
[NFC][LLVM] Add test coverage for all binops to sve-intrinsic-simplify-binop.ll.
Also adds sve-intrinsic-simplify-shift.ll to test asr, shl and shr.
Commit: 0f32809139bd104adb2c1de4fa1044da78a7e5af
https://github.com/llvm/llvm-project/commit/0f32809139bd104adb2c1de4fa1044da78a7e5af
Author: arun-thmn <arun.thangamani at intel.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/X86Vector/X86Vector.td
M mlir/include/mlir/Dialect/X86Vector/X86VectorDialect.h
M mlir/include/mlir/Dialect/X86Vector/X86VectorInterfaces.td
M mlir/lib/Dialect/X86Vector/IR/CMakeLists.txt
M mlir/lib/Dialect/X86Vector/IR/X86VectorDialect.cpp
M mlir/lib/Dialect/X86Vector/Transforms/LegalizeForLLVMExport.cpp
M mlir/test/Dialect/X86Vector/legalize-for-llvm.mlir
M mlir/test/Dialect/X86Vector/roundtrip.mlir
M mlir/test/Target/LLVMIR/x86vector.mlir
Log Message:
-----------
Reland [mlir][x86vector] AVX Convert/Broadcast BF16 to F32 instructions (#136830)
Quick fix for the PR: https://github.com/llvm/llvm-project/pull/135143
which failed building on `amd` and `arm` bots build. See the logs in the
above PR for the errors.
Commit: 500cccca0cbcbb547e2a54b25162f20808b45af0
https://github.com/llvm/llvm-project/commit/500cccca0cbcbb547e2a54b25162f20808b45af0
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/Sema/AnalysisBasedWarnings.cpp
Log Message:
-----------
Remove spurious semicolon; NFC
Commit: a99e055030f0da61651e808cbb208bb39594cdc0
https://github.com/llvm/llvm-project/commit/a99e055030f0da61651e808cbb208bb39594cdc0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/BPF/BPFISelLowering.h
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.h
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
Log Message:
-----------
[DAG] shouldReduceLoadWidth - add optional<unsigned> byte offset argument (#136723)
Based off feedback for #129695 - we need to be able to determine the
load offset of smaller loads when trying to determine whether a multiple
use load should be split (in particular for AVX subvector extractions).
This patch adds a std::optional<unsigned> ByteOffset argument to
shouldReduceLoadWidth calls for where we know the constant offset to
allow targets to make use of it in future patches.
Commit: 1fd0b41b44603c190f507f222c16d9f98470f89d
https://github.com/llvm/llvm-project/commit/1fd0b41b44603c190f507f222c16d9f98470f89d
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
R lldb/test/Shell/SymbolFile/DWARF/range-lower-then-low-pc.s
M lldb/test/Shell/SymbolFile/DWARF/x86/discontinuous-inline-function.s
Log Message:
-----------
[lldb/DWARF] Remove "range lower than function low_pc" check (#132395)
The check is not correct for discontinuous functions, as one of the
blocks could very well begin before the function entry point. To catch
dead-stripped ranges, I check whether the functions is after the first
known code address. I don't print any error in this case as that is a
common/expected situation.
This avoids many errors like:
```
error: ld-linux-x86-64.so.2 0x00085f3b: adding range [0x0000000000001ae8-0x0000000000001b07) which has a
base that is less than the function's low PC 0x000000000001cfb0. Please file a bug and attach the file at
the start of this error message
```
when debugging binaries on debian trixie because the dynamic linker
(ld-linux) contains discontinuous functions.
If the block ranges is not a subrange of the enclosing block then this
will range will currently be added to the outer block as well (i.e., we
get the same behavior that's currently possible for non-subrange blocks
larger than function_low_pc). However, this code path is buggy and I'd
like to change that (#117725).
Commit: 94206c9700d52e1a9e42da10e32f0368f9503b44
https://github.com/llvm/llvm-project/commit/94206c9700d52e1a9e42da10e32f0368f9503b44
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/CMakeLists.txt
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.h
A lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndexSet.cpp
A lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndexSet.h
M lldb/unittests/SymbolFile/DWARF/DWARFIndexCachingTest.cpp
Log Message:
-----------
[lldb] Preparation for DWARF indexing speedup (#123732)
This is part of the work proposed in
<https://discourse.llvm.org/t/rfc-speeding-up-dwarf-indexing-again/83979>.
One of the change is that the there will be a different structure for
holding the partial indexes and the final (consolidated) index. To
prepare for this, I'm making the IndexSet structure a template. The
index cache encoding/decoding methods are changed into free functions,
as they only need to know how to work with the final index.
I've moved this functionality to a separate file as all this doesn't
really depend on the rest of the ManualDWARFIndex and it needs to be
public due to its use in the unit test (both of which indicate that it
could be a component of its own).
Commit: 4e073a11c24cc0abfe5a8eabd99f1e4762c89e2b
https://github.com/llvm/llvm-project/commit/4e073a11c24cc0abfe5a8eabd99f1e4762c89e2b
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/Plugins/SymbolFile/DWARF/BUILD.gn
Log Message:
-----------
[gn build] Port 94206c9700d5
Commit: 6bb2f90557fb2b4b216299cc2beb4afb641476aa
https://github.com/llvm/llvm-project/commit/6bb2f90557fb2b4b216299cc2beb4afb641476aa
Author: Diana Picus <Diana-Magda.Picus at amd.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineFrameInfo.h
M llvm/include/llvm/CodeGen/TargetFrameLowering.h
M llvm/lib/CodeGen/PrologEpilogInserter.cpp
M llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
R llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir
R llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll
R llvm/test/CodeGen/AMDGPU/vgpr-blocks-funcinfo.mir
M llvm/unittests/Target/AMDGPU/CMakeLists.txt
R llvm/unittests/Target/AMDGPU/LiveRegUnits.cpp
Log Message:
-----------
Revert "[AMDGPU] Support block load/store for CSR" (#136846)
Reverts llvm/llvm-project#130013 due to failures with expensive checks
on.
Commit: 673882cfbc5cf8425444811f92080bdd0b7cbb78
https://github.com/llvm/llvm-project/commit/673882cfbc5cf8425444811f92080bdd0b7cbb78
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/Target/AMDGPU/BUILD.gn
Log Message:
-----------
[gn build] Port 6bb2f90557fb
Commit: 14b38cf946c5b10039865f1aaedac8ea1ca06abb
https://github.com/llvm/llvm-project/commit/14b38cf946c5b10039865f1aaedac8ea1ca06abb
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/matmul.mlir
Log Message:
-----------
[mlir][vector] Update test post 136699 (nfc) (#136841)
Updates a test that I forgot to update in #136699. Failing bot:
* https://lab.llvm.org/buildbot/#/builders/143/builds/7166
Commit: 8292e050e62f69ae9aea68fafd011152eede7e4d
https://github.com/llvm/llvm-project/commit/8292e050e62f69ae9aea68fafd011152eede7e4d
Author: Wenju He <wenju.he at intel.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M libclc/CMakeLists.txt
Log Message:
-----------
[libclc] Build for OpenCL 3.0 (#135733)
This PR is modified cherry-pick of
https://github.com/intel/llvm/commit/cba338e5fb1c
This PR sets OpenCL language version to be the same, which is 3.0,
for every target and device, in order to unify the build process.
Target should define supported extensions and features via
setSupportedOpenCLOpts API.
llvm-diff shows one change to amdgcn--amdhsa.bc:
* ctz symbols are added since they are now enabled for amdgcn.
Commit: 1ce709cb845b8b0bc4625198afa7a26c0a198fe4
https://github.com/llvm/llvm-project/commit/1ce709cb845b8b0bc4625198afa7a26c0a198fe4
Author: Nicholas Guy <nicholas.guy at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-no-dotprod.ll
Log Message:
-----------
[LV] Fix crash when building partial reductions using types that aren't known scale factors (#136680)
Commit: a1f369e6309c8c6adaae886afc55817b97953641
https://github.com/llvm/llvm-project/commit/a1f369e6309c8c6adaae886afc55817b97953641
Author: Nicholas Guy <nicholas.guy at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
Log Message:
-----------
[AArch64][SVE] Add dot product lowering for PARTIAL_REDUCE_MLA node (#130933)
Add lowering in tablegen for PARTIAL_REDUCE_U/SMLA ISD nodes. Only
happens when the combine has been performed on the ISD node. Also adds
in check to only do the DAG combine when the node can then eventually be
lowered, so changes neon tests too.
---------
Co-authored-by: James Chesterman <james.chesterman at arm.com>
Commit: 386ff113f974967dee9d3fd654c2259a94c59b2e
https://github.com/llvm/llvm-project/commit/386ff113f974967dee9d3fd654c2259a94c59b2e
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
Log Message:
-----------
[flang][OpenMP] Use OmpMemoryOrderType enumeration in FAIL clause (#136313)
Make the FAIL clause contain OmpMemoryOrderType enumeration instead of
OmpClause. This simplifies the semantic checks of the FAIL clause.
Commit: 5b0cd17c386ecd126c7f0ab514413bab8222b421
https://github.com/llvm/llvm-project/commit/5b0cd17c386ecd126c7f0ab514413bab8222b421
Author: Virginia Cangelosi <virginia.cangelosi at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/include/clang/Basic/arm_sme.td
A clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
A clang/test/Sema/aarch64-sme2p2-instrinsics/acle_sme2p2_fp8_imm.cpp
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/SMEInstrFormats.td
A llvm/test/CodeGen/AArch64/sme2-intrinsics-mop4-fp8.ll
Log Message:
-----------
[Clang][llvm] Implement fp8 FMOP4A intrinsics (#130127)
Implement all mf8 FMOP4A instructions in clang and llvm following the
acle in https://github.com/ARM-software/acle/pull/381/files.
It also updates previous mop4 instructions from IntrNoMem to
IntrInaccessibleMemOnly
Commit: 92bba68634ec48c738d45bc86b05b1390aa82f4b
https://github.com/llvm/llvm-project/commit/92bba68634ec48c738d45bc86b05b1390aa82f4b
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/Frontend/OpenMP/OMPDeviceConstants.h
M offload/DeviceRTL/src/Kernel.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/test/offloading/ompx_bare.c
M offload/test/offloading/ompx_bare_multi_dim.cpp
Log Message:
-----------
[Offload] Fix handling of 'bare' mode when environment missing (#136794)
Summary:
We treated the missing kernel environment as a unique mode, but it was
kind of this random bool that was doing the same thing and it explicitly
expects the kernel environment to be zero. It broke after the previous
change since it used to default to SPMD and didn't handle zero in any of
the other cases despite being used. This fixes that and queries for it
without needing to consume an error.
Commit: 6d0d50f0ac0cb108a06558cb178a68fb78cfa06f
https://github.com/llvm/llvm-project/commit/6d0d50f0ac0cb108a06558cb178a68fb78cfa06f
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M offload/DeviceRTL/CMakeLists.txt
Log Message:
-----------
[OpenMP] Update the bitcode library install and search path (#136754)
Summary:
This was accidentally kept in the old location when we moved to the
new `lib/<triple>/` location for the DeviceRTL. Move this to reduce the
delta with https://github.com/llvm/llvm-project/pull/136729.
Commit: 91e1922d45bdefd444a2ba0484fd858e2ad80254
https://github.com/llvm/llvm-project/commit/91e1922d45bdefd444a2ba0484fd858e2ad80254
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
Log Message:
-----------
[DSE] Skip non-pointer args in initializes handling (NFCI)
Avoid performing AA queries on non-pointers.
Commit: 14dee0aeaaef2ebd5c3295edca4c5d3762464934
https://github.com/llvm/llvm-project/commit/14dee0aeaaef2ebd5c3295edca4c5d3762464934
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/NewGVN.cpp
Log Message:
-----------
[NewGVN] Avoid AA query on non-pointers (NFCI)
In order for the instruction result to alias with the pointer it
needs to be a pointer.
Commit: 01ee03c262519597307301715dc4d41e6d62b774
https://github.com/llvm/llvm-project/commit/01ee03c262519597307301715dc4d41e6d62b774
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Coroutines/CoroElide.cpp
Log Message:
-----------
[CoroElide] Avoid AA query on non-pointers (NFCI)
Commit: 208257f7e0f1e7bbf878753bb8a7554891b84380
https://github.com/llvm/llvm-project/commit/208257f7e0f1e7bbf878753bb8a7554891b84380
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Coroutines/CoroElide.cpp
Log Message:
-----------
[CoroElide] Remove unnecessary bitcast (NFCI)
No longer needed with opaque pointers.
Commit: eea1efed305fbeba5dc2b5e856d934ba8e57965c
https://github.com/llvm/llvm-project/commit/eea1efed305fbeba5dc2b5e856d934ba8e57965c
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
Log Message:
-----------
[InstrProfiling] Avoid unnecessary bitcast (NFC)
Not needed with opaque pointers.
Commit: 00934beb8e6b9a5fe04ff7805249706d0edc3c5b
https://github.com/llvm/llvm-project/commit/00934beb8e6b9a5fe04ff7805249706d0edc3c5b
Author: jyli0116 <jyli0116 at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/test/CodeGen/AArch64/fsh.ll
Log Message:
-----------
[AArch64] Funnel Shift now uses rev32/rev64 instructions (#136707)
Fixes #130469
Now uses REV32/REV64 instructions to complete operation.
New Output:
```
G1:
rev64 v0.4s, v0.4s
ret
G2:
rev32 v0.8h, v0.8h
ret
G3:
rev16 v0.16b, v0.16b
ret
G4:
rev32 v0.4h, v0.4h
ret
G5:
rev16 v0.8b, v0.8b
ret
```
Old Output:
```
G1:
shl v1.2d, v0.2d, #32
usra v1.2d, v0.2d, #32
mov v0.16b, v1.16b
ret
G2:
shl v1.4s, v0.4s, #16
usra v1.4s, v0.4s, #16
mov v0.16b, v1.16b
ret
G3:
rev16 v0.16b, v0.16b
ret
G4:
shl v1.2s, v0.2s, #16
usra v1.2s, v0.2s, #16
fmov d0, d1
ret
G5:
rev16 v0.8b, v0.8b
ret
```
Commit: 52cb1c93acdad4fa2aa0ce17691d7205cc9645f9
https://github.com/llvm/llvm-project/commit/52cb1c93acdad4fa2aa0ce17691d7205cc9645f9
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
Log Message:
-----------
[AArch64Arm64ECCallLowering] Remove unnecessary bitcasts (NFCI)
These are all pointer bitcasts, which are no longer necessary
with opaque pointers.
Commit: a2c1ff10eb930dd56be306dc0818d6ff31fff546
https://github.com/llvm/llvm-project/commit/a2c1ff10eb930dd56be306dc0818d6ff31fff546
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
Log Message:
-----------
[mlir][acc] Use consistent name for device_num operand (#136745)
`acc.set`, `acc.init`, and `acc.shutdown` take a `device_num` operand.
However, this was named inconsistently. Give it the same consistent name
for all aforementioned operations.
---------
Co-authored-by: erichkeane <ekeane at nvidia.com>
Commit: 4cc806f9f5b76b3ca42de29fb6a3affe9774d7f8
https://github.com/llvm/llvm-project/commit/4cc806f9f5b76b3ca42de29fb6a3affe9774d7f8
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
Log Message:
-----------
[AArch64Arm64ECCallLowering] Drop unnecessary pointer type members (NFC)
With opaque pointers, these are all the same type. Consolidate to
just PtrTy.
Commit: 5afe85982a6e911326c5df141c718b239edea9c8
https://github.com/llvm/llvm-project/commit/5afe85982a6e911326c5df141c718b239edea9c8
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
Log Message:
-----------
[OMPIRBuilder] Remove unnecessary pointer bitcasts (NFCI)
Not needed with opaque pointers.
Commit: 237ed0cffcd721f0ae48420f17db2e2da97fb625
https://github.com/llvm/llvm-project/commit/237ed0cffcd721f0ae48420f17db2e2da97fb625
Author: Christian Sigg <csigg at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] Port 0f32809139bd104adb2c1de4fa1044da78a7e5af.
Commit: e58d227b09d533e2df644f827cedff8e206e0bfc
https://github.com/llvm/llvm-project/commit/e58d227b09d533e2df644f827cedff8e206e0bfc
Author: Tobias Stadler <mail at stadler-tobias.de>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
A llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector.mir
Log Message:
-----------
[NFC][AArch64][GlobalISel] Add test coverage for vector load/store legalization (#134904)
Precommit tests for vector load/store legalization changes. This exposes
a miscompile in LegalizerHelper::reduceLoadStoreWidth for non-byte-sized
vector elements, which will be fixed in a follow-up patch.
The other tests are potential miscompilations due to unclear semantics
of vector load/stores, which will be addressed in a follow-up
discussion.
Commit: 46f18b7c6febe75b2cc0095f2227d935c14f70f2
https://github.com/llvm/llvm-project/commit/46f18b7c6febe75b2cc0095f2227d935c14f70f2
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M libcxxabi/test/test_demangle.pass.cpp
Log Message:
-----------
[ItaniumDemangle][test] Add test-cases for ref-qualified member pointer parameters
I noticed that there are test-cases that are commented out. But the
manglings for them seem to be impossible to generate from valid C++. I
added two test-cases generated from following C++ program:
```
struct X {
int func() const && { return 5; }
const int &&func2() { return 5; }
const int &&func3(const int &x) volatile { return 5; }
};
void f(int (X::*)() const &&, int const && (X::*)(),
int const && (X::*)(const int &) volatile) {}
int main() {
f(&X::func, &X::func2, &X::func3);
return 0;
}
```
Commit: 8158d43da33b33d260f2c43eb3f448f42b839b21
https://github.com/llvm/llvm-project/commit/8158d43da33b33d260f2c43eb3f448f42b839b21
Author: Dmitriy Smirnov <dmitriy.smirnov at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
Log Message:
-----------
[TOSA] Rescale output_zp fix (#136116)
Patch corrects output_zp in case of usigned output
Commit: 8502ba1eb40acdb0eda1039807afc34db0c7084a
https://github.com/llvm/llvm-project/commit/8502ba1eb40acdb0eda1039807afc34db0c7084a
Author: lorenzo chelini <l.chelini at icloud.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/MemRef/Transforms/Passes.h
M mlir/include/mlir/Dialect/MemRef/Transforms/Passes.td
M mlir/lib/Dialect/Bufferization/Pipelines/BufferizationPipelines.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandRealloc.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
M mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/NormalizeMemRefs.cpp
M mlir/lib/Dialect/MemRef/Transforms/ResolveShapedTypeResultDims.cpp
M mlir/test/python/pass_manager.py
Log Message:
-----------
[MLIR][NFC] Retire let constructor for MemRef (#134788)
let constructor is legacy (do not use in tree!) since the tableGen
backend emits most of the glue logic to build a pass.
Note: The following constructor has been retired:
```cpp
std::unique_ptr<Pass> createExpandReallocPass(bool emitDeallocs = true);
```
To update your codebase, replace it with the new options-based API:
```cpp
memref::ExpandReallocPassOptions expandAllocPassOptions{
/*emitDeallocs=*/false};
pm.addPass(memref::createExpandReallocPass(expandAllocPassOptions));
```
Commit: 806d59eecd16dc35473638fd73ea0be8e59c6275
https://github.com/llvm/llvm-project/commit/806d59eecd16dc35473638fd73ea0be8e59c6275
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M libclc/generic/include/clc/image/image.h
Log Message:
-----------
[libclc] Fix unguarded use of image types (#136871)
Commit 8292e05 which switched the OpenCL C version to 3.0 exposed this
issue, which wasn't caught in pre-commit CI.
Commit: 6c561604336497cbeebc90f9066a9f474458a38d
https://github.com/llvm/llvm-project/commit/6c561604336497cbeebc90f9066a9f474458a38d
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M libclc/CMakeLists.txt
Log Message:
-----------
[libclc] Re-enable compiler warning (#136872)
libclc is now clean of code that triggers the
bitwise-conditional-parentheses warning, so we can finally remove the
workaround.
Commit: f11b3decdd603655d886061c0b2e26b64a6563d2
https://github.com/llvm/llvm-project/commit/f11b3decdd603655d886061c0b2e26b64a6563d2
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M flang/lib/Optimizer/CodeGen/TargetRewrite.cpp
M flang/test/Fir/CUDA/cuda-target-rewrite.mlir
Log Message:
-----------
[flang][cuda] Carry over the CUDA attribute in target rewrite (#136811)
Commit: 96519028d514853d429c2d09482ba0bd9a899c57
https://github.com/llvm/llvm-project/commit/96519028d514853d429c2d09482ba0bd9a899c57
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/source/Plugins/Language/CPlusPlus/LibCxxInitializerList.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxSpan.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxVariant.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxVector.cpp
Log Message:
-----------
[lldb][DataFormatters] Make data-formatters log to the DataFormatters channel
Currently the data-formatters log to either DataFormatters or Types. The
former is probably more sensible, so log there consistently from all
formatters.
Commit: cc6def4b7521676fd339936d027e48928e0ba398
https://github.com/llvm/llvm-project/commit/cc6def4b7521676fd339936d027e48928e0ba398
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M libc/src/stdio/printf_core/core_structs.h
Log Message:
-----------
[libc] Special case PPC double double for print (#136614)
Summary:
We use the storage class for `long double` in the printing
implementations. We don't fully support the PPC double double type,
which that maps to, but we can stub out just the support needed for the
print interface to works. This required using the internal interface for
storage type, but it should be good enough.
Fixes: https://github.com/llvm/llvm-project/issues/136596
Commit: ecb0daa72c442caeb4e295e1076d54c5e18101b2
https://github.com/llvm/llvm-project/commit/ecb0daa72c442caeb4e295e1076d54c5e18101b2
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/utils/TableGen/DecoderEmitter.cpp
Log Message:
-----------
[NFC][LLVM][TableGen] Eliminate inheritance from std::vector (#136573)
Commit: 79151244d6a501c027add60734ddfe4c609e75bb
https://github.com/llvm/llvm-project/commit/79151244d6a501c027add60734ddfe4c609e75bb
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Log Message:
-----------
[DAG] narrowExtractedVectorLoad - reuse existing SDLoc. NFC (#136870)
Commit: 2e389cb9aae0e9734fc8e16f6ebc6edb392d79a9
https://github.com/llvm/llvm-project/commit/2e389cb9aae0e9734fc8e16f6ebc6edb392d79a9
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M flang/test/Semantics/OpenACC/acc-data.f90
M llvm/include/llvm/Frontend/OpenACC/ACC.td
Log Message:
-----------
[Flang][OpenACC] Make async clause on data consistent with elsewhere (#136866)
in #136610 we agreed that all async clauses on compute constructs should
act as 'only 1 per device-type-group'. On `data`, it has the same
specification language, and the same real requirements, so it seems
sensible to make it work the same way.
Commit: 8abc917fe04140b6c6088a67e0398f637efde808
https://github.com/llvm/llvm-project/commit/8abc917fe04140b6c6088a67e0398f637efde808
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/test/Transforms/InstCombine/and-fcmp.ll
Log Message:
-----------
[InstCombine] Do not fold logical is_finite test (#136851)
This patch disables the fold for logical is_finite test (i.e., `and
(fcmp ord x, 0), (fcmp u* x, inf) -> fcmp o* x, inf`).
It is still possible to allow this fold for several logical cases (e.g.,
`stripSignOnlyFPOps(RHS0)` does not strip any operations). Since this
patch has no real-world impact, I decided to disable this fold for all
logical cases.
Alive2: https://alive2.llvm.org/ce/z/aH4LC7
Closes https://github.com/llvm/llvm-project/issues/136650.
Commit: 24c860547e8e595f8bf8d87b52544e2aff243f2e
https://github.com/llvm/llvm-project/commit/24c860547e8e595f8bf8d87b52544e2aff243f2e
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
Log Message:
-----------
AMDGPU/MC: Fix emitting absolute expressions (#136789)
When absolute MCExprs appear in normal instruction operands, we have to
emit them like a normal inline constant or literal. More generally, an
MCExpr that happens to have an absolute evaluation should be treated
exactly like an immediate operand here.
No test; I found this downstream, and I don't think it can be triggered
upstream yet.
Fixes: 16238669 ("[AMDGPU][MC] Support UC_VERSION_* constants. (#95618)")
Commit: 2f0cd0c68ef027f87f34f04141c083212fda2806
https://github.com/llvm/llvm-project/commit/2f0cd0c68ef027f87f34f04141c083212fda2806
Author: Mingming Liu <mingmingl at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/lib/ProfileData/InstrProf.cpp
M llvm/lib/ProfileData/InstrProfWriter.cpp
Log Message:
-----------
[NFCI] Move ProfOStream from InstrProfWriter.cpp to InstrProf.h/cpp (#136791)
ProfOStream is a wrapper class for output stream, and used by
InstrProfWriter.cpp to serialize various profiles, like PGO profiles and
MemProf.
This change proposes to move it into InstrProf.h/cpp. After this is in,
InstrProfWriter can dispatch serialization of various formats into
methods like `obj->serialize()`, and the serialization code could be
move out of InstrProfWriter.cpp into individual classes (each in a
smaller cpp file). One example is that we can gradually move
writeMemprof [1] into llvm/*/ProfileData/MemProf.h/cpp, where a couple
of classes already have `serialize/deserialize` methods.
[1]
https://github.com/llvm/llvm-project/blob/85b35a90770b6053f91d79ca685cdfa4bf6499a4/llvm/lib/ProfileData/InstrProfWriter.cpp#L774-L791
Commit: 1da856a685cf427ab1f5b810125c41e7859ed362
https://github.com/llvm/llvm-project/commit/1da856a685cf427ab1f5b810125c41e7859ed362
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndexSet.h
Log Message:
-----------
[lldb] Fix typo in ManualDWARFIndexSet.h
operator== wasn't used in production code, but the bad definition made
the tests vacuosly pass.
Commit: a83b4a2dc9706d9e898f3462b5c2ff5ed05589d2
https://github.com/llvm/llvm-project/commit/a83b4a2dc9706d9e898f3462b5c2ff5ed05589d2
Author: Justin Bogner <mail at justinbogner.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/Analysis/DXILResource.h
M llvm/lib/Target/DirectX/CMakeLists.txt
A llvm/lib/Target/DirectX/DXILForwardHandleAccesses.cpp
A llvm/lib/Target/DirectX/DXILForwardHandleAccesses.h
M llvm/lib/Target/DirectX/DirectX.h
M llvm/lib/Target/DirectX/DirectXPassRegistry.def
M llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/alloca.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/ambiguous.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/buffer-O0.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/cbuffer-access.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/undominated.ll
M llvm/test/CodeGen/DirectX/llc-pipeline.ll
Log Message:
-----------
[DirectX] Implement the ForwardHandleAccesses pass (#135378)
This pass attempts to forward resource handle creation to accesses of
the handle global. This avoids dependence on optimizations like CSE and
GlobalOpt for correctness of DXIL.
Fixes #134574.
Commit: ea5449ddd5d03da034eccb80e5ba1e44ee02e243
https://github.com/llvm/llvm-project/commit/ea5449ddd5d03da034eccb80e5ba1e44ee02e243
Author: erichkeane <ekeane at nvidia.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M clang/test/CIR/CodeGenOpenACC/data.c
M clang/test/SemaOpenACC/data-construct-async-clause.c
Log Message:
-----------
[OpenACC][CIR] Implement 'async'/'if' lowering for 'data' construct
These two are trivial, and work the same as the compute construct
versions of these, so this adds tests to do so, and adds them to the
implementation.
Commit: d7215c0ee2e4bca1ce87b956335ef6a2cddaf16f
https://github.com/llvm/llvm-project/commit/d7215c0ee2e4bca1ce87b956335ef6a2cddaf16f
Author: Jannick Kremer <jannick.kremer at mailbox.org>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/tools/libclang/CIndex.cpp
M clang/unittests/libclang/LibclangTest.cpp
Log Message:
-----------
[libclang/C++] Fix clang_File_isEqual for in-memory files (#135773)
Add tests for `clang_File_isEqual` (on-disk and in-memory)
Commit: 83c309b90550aa768ff9aa11b70898ee2c56b71e
https://github.com/llvm/llvm-project/commit/83c309b90550aa768ff9aa11b70898ee2c56b71e
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/include/clang/Sema/ScopeInfo.h
M clang/include/clang/Sema/SemaCUDA.h
M clang/lib/Sema/SemaCUDA.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaOverload.cpp
A clang/test/CodeGenCUDA/lambda-constexpr-capture.cu
Log Message:
-----------
[CUDA][HIP] capture possible ODR-used var (#136645)
In a lambda function, a call of a function may
resolve to host and device functions with different
signatures. Especially, a constexpr local variable may
be passed by value by the device function and
passed by reference by the host function, which
will cause the constexpr variable captured by
the lambda function in host compilation but
not in the device compilation. The discrepancy
in the lambda captures will violate ODR and
causes UB for kernels using these lambdas.
This PR fixes the issue by identifying
discrepancy of ODR/non-ODR usages of constexpr
local variables passed to host/device functions
and conservatively capture them.
Fixes: https://github.com/llvm/llvm-project/issues/132068
Commit: 1b6cbaa7b64f54b127d139d653468e213bae007e
https://github.com/llvm/llvm-project/commit/1b6cbaa7b64f54b127d139d653468e213bae007e
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/PrimType.h
M clang/test/AST/ByteCode/literals.cpp
Log Message:
-----------
[clang][bytecode] Refine diagnostics for volatile reads (#136857)
Differentiate between a volarile read via a lvalue-to-rvalue cast of a
volatile qualified subexpression and a read from a pointer with a
volatile base object.
Commit: 6dbc01e8015816e904687c03f0ea8afac817781d
https://github.com/llvm/llvm-project/commit/6dbc01e8015816e904687c03f0ea8afac817781d
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
M llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AMDGPU/fpext-free.ll
M llvm/test/CodeGen/AMDGPU/fpow.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/function-args.ll
M llvm/test/CodeGen/AMDGPU/function-returns.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.wave32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/lrint.ll
M llvm/test/CodeGen/AMDGPU/lround.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/strict_fpext.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
M llvm/test/CodeGen/AMDGPU/vector_rebroadcast.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vopc_dpp.mir
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
Log Message:
-----------
[AMDGPU][True16][CodeGen] update GFX11Plus codegen test with true16 flag (#135078)
This is a NFC patch.
This patch run a bulk update on CodeGen tests that are impacted by the
true16 features. This patch applies:
1. duplicate GFX11plus runlines and apply them with
"+mattr=+real-true16" and "+mattr=-real-true16"
2. update the test with the update script
For some GISEL runlines, the current CodeGen do not fully support the
true16 version. Still update the runlines, but comment out the failing
one, and added a "FIXME-TRUE16" comment to that test for easier
tracking. These test will be fixed in the following patches.
This is in a transition state that we support both
"+real-true16/-real-true16" in our code base. We plan to move to
"+real-true16" as default, and finally remove "-real-true16" mode and
test lines.
Commit: 1041d54bd4f693c1ac03077680ece67e03c99e22
https://github.com/llvm/llvm-project/commit/1041d54bd4f693c1ac03077680ece67e03c99e22
Author: John Harrison <harjohn at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/Handler/CancelRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/DisconnectRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/NextRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
M lldb/tools/lldb-dap/Protocol/ProtocolBase.h
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
M lldb/tools/lldb-dap/Transport.cpp
Log Message:
-----------
[lldb-dap] Updating the 'next' request handler use well structured types (#136642)
This updates the 'next' request to use well structured types. While
working on this I also simplified the 'RequestHandler' implementation to
better handle void responses by allowing requests to return a
'llvm::Error' instead of an 'llvm::Expected<std::monostate>'. This makes
it easier to write and understand request handles that have simple ack
responses.
Commit: 060f3f0dd1614b624b527e871019970e4303de11
https://github.com/llvm/llvm-project/commit/060f3f0dd1614b624b527e871019970e4303de11
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/include/clang/Frontend/CompilerInstance.h
M clang/include/clang/Lex/DependencyDirectivesScanner.h
M clang/include/clang/Lex/Preprocessor.h
M clang/include/clang/Lex/PreprocessorOptions.h
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningFilesystem.h
M clang/lib/Frontend/CompilerInstance.cpp
M clang/lib/Lex/PPLexerChange.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
M clang/unittests/Lex/PPDependencyDirectivesTest.cpp
Log Message:
-----------
[clang][deps] Make dependency directives getter thread-safe (#136178)
This PR fixes two issues in one go:
1. The dependency directives getter (a `std::function`) was being stored
in `PreprocessorOptions`. This goes against the principle where the
options classes are supposed to be value-objects representing the `-cc1`
command line arguments. This is fixed by moving the getter directly to
`CompilerInstance` and propagating it explicitly.
2. The getter was capturing the `ScanInstance` VFS. That's fine in
synchronous implicit module builds where the same VFS instance is used
throughout, but breaks down once you try to build modules asynchronously
(which forces the use of separate VFS instances). This is fixed by
explicitly passing a `FileManager` into the getter and extracting the
right instance of the scanning VFS out of it.
Commit: 385b07b5038ff65f084446a92849e54fd86bd3a7
https://github.com/llvm/llvm-project/commit/385b07b5038ff65f084446a92849e54fd86bd3a7
Author: Paul Kirth <paulkirth at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang-tools-extra/clang-doc/Serialize.cpp
Log Message:
-----------
[clang-doc][NFC] Remove else after return (#136443)
Commit: 0f5965fa9c67969e4de7374362b6af49bf400b3b
https://github.com/llvm/llvm-project/commit/0f5965fa9c67969e4de7374362b6af49bf400b3b
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/test/CIR/CodeGen/struct.c
M clang/test/CIR/CodeGen/struct.cpp
M clang/test/CIR/CodeGen/typedef.c
M clang/test/CIR/CodeGen/union.c
M clang/test/CIR/IR/struct.cir
Log Message:
-----------
[CIR] Introduce type aliases for records (#136387)
This introduces MLIR aliases for ClangIR record types. These are used in
the incubator and having skipped over them upstream is causing the tests
to diverge.
Commit: 3c9027c1d7aac0c1e54af13182f1b8f58d376115
https://github.com/llvm/llvm-project/commit/3c9027c1d7aac0c1e54af13182f1b8f58d376115
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/Serialization/ModuleManager.cpp
M clang/test/Modules/explicit-build.cpp
Log Message:
-----------
[clang][Modules] Clarify error message when size check fails in lookupModuleFile
Commit: dbb8434ff7b9bb414e2222cb8d9cddac599eadc6
https://github.com/llvm/llvm-project/commit/dbb8434ff7b9bb414e2222cb8d9cddac599eadc6
Author: Peter Collingbourne <peter at pcc.me.uk>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Log Message:
-----------
SelectionDAG: Add missing AddNodeIDCustom case for MDNodeSDNode.
Without this we ended up never deduplicating MDNodeSDNodes.
Reviewers: arsenm
Reviewed By: arsenm
Pull Request: https://github.com/llvm/llvm-project/pull/136805
Commit: 3b48e2a7508ab090b1b7c6a68f87e3eddad5473d
https://github.com/llvm/llvm-project/commit/3b48e2a7508ab090b1b7c6a68f87e3eddad5473d
Author: John Harrison <harjohn at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/tools/lldb-dap/Handler/RequestHandler.cpp
Log Message:
-----------
[lldb-dap] Ensure we acquire the SB API lock while handling requests. (#137026)
Acquiring the lock for the target should help ensure consistency with
other background operations, like the thread monitoring events that can
trigger run commands from a different thread.
Commit: 213424b94792d730510a12046abfc05e0262c985
https://github.com/llvm/llvm-project/commit/213424b94792d730510a12046abfc05e0262c985
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/source/Utility/ArchSpec.cpp
M lldb/unittests/Utility/ArchSpecTest.cpp
M llvm/include/llvm/BinaryFormat/MachO.h
Log Message:
-----------
Add MachO RISC-V CPU type and CPU subtype to llvm & lldb (#136785)
Add the enum values for MachO RISC-V CPU type and CPU subtype to
llvm and use in LLDB's ArchSpec.
Commit: bdf21ca8ac8a30ad1ace6732f05c11e812aca535
https://github.com/llvm/llvm-project/commit/bdf21ca8ac8a30ad1ace6732f05c11e812aca535
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
Log Message:
-----------
[LV] Fix missing entry in willGenerateVectors (#136712)
willGenerateVectors switches on opcodes of a recipe, but Histogram is
missing in the switch statement, which could cause a crash in some
cases. The crash was initially observed when developing another patch.
Commit: 98eb4761c8640968a922dab417dfa42ef2621c43
https://github.com/llvm/llvm-project/commit/98eb4761c8640968a922dab417dfa42ef2621c43
Author: alx32 <103613512+alx32 at users.noreply.github.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/test/tools/dsymutil/ARM/stmt-seq-macho.test
Log Message:
-----------
Fix stmt-seq-macho.test for little endian platforms (#137017)
The test YAML was created on a little-endian system, so its data is
stored in little-endian order. When the test runs on a big-endian host,
yaml2obj defaults to the host’s byte order, misreading the file as
big-endian and causing a failure.
This change explicitly marks the YAML as little-endian, guaranteeing
that yaml2obj always uses the correct byte order, no matter which
machine runs the test.
The reason that during creation, obj2yaml doesn't specify the endianness
is because the endianness is set as an optional parameter and therefore
it won't be specified if it matches the platform default. Ref:
https://github.com/llvm/llvm-project/blob/d7215c0ee2e4bca1ce87b956335ef6a2cddaf16f/llvm/lib/ObjectYAML/MachOYAML.cpp#L105
Commit: d3e1fd62aaa7c929952f9e7985c81f05af89476c
https://github.com/llvm/llvm-project/commit/d3e1fd62aaa7c929952f9e7985c81f05af89476c
Author: Matthias Springer <me at m-sp.org>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/test/Dialect/LLVMIR/canonicalize.mlir
Log Message:
-----------
[mlir][LLVM] Improve `llvm.extractvalue` folder (#136861)
Continue the traversal on the SSA chain of the inserted value for
additional folding opportunities.
Commit: 5bb4cf9d9189c41de50adffd960eb2188140eb9c
https://github.com/llvm/llvm-project/commit/5bb4cf9d9189c41de50adffd960eb2188140eb9c
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/hdr/CMakeLists.txt
A libc/hdr/offsetof_macros.h
M libc/include/llvm-libc-types/CMakeLists.txt
M libc/include/llvm-libc-types/jmp_buf.h
M libc/include/setjmp.yaml
M libc/src/setjmp/CMakeLists.txt
A libc/src/setjmp/linux/CMakeLists.txt
A libc/src/setjmp/linux/sigsetjmp_epilogue.cpp
M libc/src/setjmp/setjmp_impl.h
A libc/src/setjmp/siglongjmp.cpp
A libc/src/setjmp/siglongjmp.h
A libc/src/setjmp/sigsetjmp.h
A libc/src/setjmp/sigsetjmp_epilogue.h
M libc/src/setjmp/x86_64/CMakeLists.txt
M libc/src/setjmp/x86_64/setjmp.cpp
A libc/src/setjmp/x86_64/sigsetjmp.cpp
M libc/test/src/setjmp/CMakeLists.txt
A libc/test/src/setjmp/sigsetjmp_test.cpp
Log Message:
-----------
[libc] implement sigsetjmp/siglongjmp for x86-64 (#136072)
Commit: a0fce0ba31277b6cbdb335a9529477415a01760d
https://github.com/llvm/llvm-project/commit/a0fce0ba31277b6cbdb335a9529477415a01760d
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/plugin_config.bzl
Log Message:
-----------
[bazel] Use non_arc_srcs instead of passing -fno-objc-arc (#137037)
This is the recommended way in bazel to differentiate between files that
require arc and those that require it be disabled. This matters
depending on the toolchain since the order of these flags may not have
been correct and we were relying on overwriting the default.
Commit: b8e420e424b41f67019155055f4f600ba0454189
https://github.com/llvm/llvm-project/commit/b8e420e424b41f67019155055f4f600ba0454189
Author: Finn Plummer <canadienfinn at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Parse/ParseHLSLRootSignature.h
M clang/lib/Parse/ParseHLSLRootSignature.cpp
M clang/unittests/Parse/ParseHLSLRootSignatureTest.cpp
M llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h
Log Message:
-----------
Reland "[HLSL][RootSignature] Implement initial parsing of the descriptor table clause params" (#136740)
This pr relands #133800.
It addresses the compilation error of using a shadowed name `Register`
for both the struct name and the data member holding this type:
`Register Register`. It resolves the issues my renaming the data members
called `Register` to `Reg`.
This issue was not caught as the current pre-merge checks do not include
a build of `llvm;clang` using the gcc/g++ compilers and this is not
erroneous with clang/clang++.
Second part of #126569
---------
Co-authored-by: Finn Plummer <finnplummer at microsoft.com>
Commit: bc1198719e206b2b6928ac437cb59107b45662d6
https://github.com/llvm/llvm-project/commit/bc1198719e206b2b6928ac437cb59107b45662d6
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/runtimes/CMakeLists.txt
Log Message:
-----------
[Offload] Fix missing dependency on `clang-nvlink-wrapper' (#137033)
Summary:
It's possible that this won't be built in time for the runtimes build.
Add this as a dependency. We will also need to make this future proof
and loop over all the enabled targets, but that's a later update.
Commit: 3fbbe9b8d08957f901d92f04becfe4352ccc2261
https://github.com/llvm/llvm-project/commit/3fbbe9b8d08957f901d92f04becfe4352ccc2261
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Add exit phi operands during initial construction (NFC). (#136455)
Add incoming exit phi operands during the initial VPlan construction.
This ensures all users are added to the initial VPlan and is also needed
in preparation to retaining exiting edges during initial construction.
PR: https://github.com/llvm/llvm-project/pull/136455
Commit: a05aeda30534fe30dfcccebb61b78489847e5192
https://github.com/llvm/llvm-project/commit/a05aeda30534fe30dfcccebb61b78489847e5192
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefMemberChecker.cpp
M clang/test/Analysis/Checkers/WebKit/unchecked-members.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-members.cpp
Log Message:
-----------
[RawPtrRefMemberChecker] Member variable checker should allow T* in smart pointer classes (#136503)
This PR fixes member variable checker to allow the usage of T* in smart
pointer classes. e.g. alpha.webkit.NoUncheckedPtrMemberChecker should
allow T* to appear within RefPtr.
Commit: f07511a0e0d2ac9bee9ae12a9ad68e279e352634
https://github.com/llvm/llvm-project/commit/f07511a0e0d2ac9bee9ae12a9ad68e279e352634
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M libc/src/setjmp/CMakeLists.txt
M libc/src/setjmp/x86_64/sigsetjmp.cpp
Log Message:
-----------
[libc] build fix for sigsetjmp (#137047)
This PR fixes the build failure due to the `sigsetjmp` implementation.
1. Use a most relaxed input constraint to fix `clang` build.
2. Avoid create alias target if os directory for `sigsetjmp_epilogue`
does not exist.
Commit: 563ab56497104199b9fd57df9bd162f2b02cbe92
https://github.com/llvm/llvm-project/commit/563ab56497104199b9fd57df9bd162f2b02cbe92
Author: Ely Ronnen <elyronnen at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/include/lldb/API/SBExecutionContext.h
M lldb/include/lldb/API/SBInstructionList.h
M lldb/source/API/SBInstructionList.cpp
M lldb/tools/lldb-dap/Handler/SourceRequestHandler.cpp
Log Message:
-----------
[lldb-dap] Show load addresses in disassembly (#136755)
Improves the lldb-dap disassembly by showing load addresses in
disassembly, same as in a regular LLDB `disassemble` command by default.
Before:
After:
Commit: 0fdb908e39b22a3c630bb6b727d71748df96f8ac
https://github.com/llvm/llvm-project/commit/0fdb908e39b22a3c630bb6b727d71748df96f8ac
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M flang/lib/Optimizer/Dialect/CUF/CUFToLLVMIRTranslation.cpp
Log Message:
-----------
[flang][cuda][NFC] Update binary name (#137034)
Name was changed in https://github.com/llvm/llvm-project/pull/135478
Commit: ff36508d2189ca9e414262f2c7a3b3a1d4974108
https://github.com/llvm/llvm-project/commit/ff36508d2189ca9e414262f2c7a3b3a1d4974108
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
Log Message:
-----------
[VPlan] Remove redundant setting of parent in createLoopRegion (NFC).
The regions parents will be set when the parents are set after creating
the parent region.
Commit: 112014ba67792e00ff719d640a5fddb79d78674d
https://github.com/llvm/llvm-project/commit/112014ba67792e00ff719d640a5fddb79d78674d
Author: Shafik Yaghmour <shafik.yaghmour at intel.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/Sema/SemaExprCXX.cpp
Log Message:
-----------
[Clang][NFC] Use temporary instead of one use local variable when creating APValue (#137029)
Static analysis flagged this code b/c we should have been using
std::move when passing by value since the value is not used anymore. In
this case the simpler fix is just to use a temporary value as many of
the other cases where we simply use MakeIntValue to then create an
APValue result from it.
Commit: 71f2c1e2045abaa4c5dcf47edfd1adbc407e7563
https://github.com/llvm/llvm-project/commit/71f2c1e2045abaa4c5dcf47edfd1adbc407e7563
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Use early exit in ::extractLastLaneOfFirstOperand (NFC).
Reduce indent level, as suggested in
https://github.com/llvm/llvm-project/pull/136455.
Commit: f4189817df9b32903d0704028c8d2ea9b0ea5908
https://github.com/llvm/llvm-project/commit/f4189817df9b32903d0704028c8d2ea9b0ea5908
Author: Henrich Lauko <xlauko at mail.muni.cz>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
Log Message:
-----------
[CIR] Create CIR_TypedAttr common class (#136852)
Introduce common base class for attributes with single type parameter.
This mirrors incubator changes introduced in https://github.com/llvm/clangir/pull/1583
Commit: ff6a23d65eccba0991244c4127506452e1030393
https://github.com/llvm/llvm-project/commit/ff6a23d65eccba0991244c4127506452e1030393
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
A llvm/test/CodeGen/RISCV/zalasr-offset-folding.ll
Log Message:
-----------
[RISCV] Return false for Zalasr load/store in isWorthFoldingAdd. (#136799)
The Zalasr load/store don't support reg-imm addressing modes so they
can't fold an ADDI.
Commit: cef9ed56f8c19258f8805512e58627c5bc79bf98
https://github.com/llvm/llvm-project/commit/cef9ed56f8c19258f8805512e58627c5bc79bf98
Author: Dave Lee <davelee.com at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp
Log Message:
-----------
[lldb] Fix typo in tagged-pointer syntax string (NFC) (#137069)
Commit: 6f5b98b3247969eb85135141bdae4a2d6aeb284a
https://github.com/llvm/llvm-project/commit/6f5b98b3247969eb85135141bdae4a2d6aeb284a
Author: Ely Ronnen <elyronnen at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/include/lldb/Utility/CompletionRequest.h
M lldb/packages/Python/lldbsuite/test/lldbtest.py
M lldb/source/API/SBCommandInterpreter.cpp
M lldb/source/Commands/CommandCompletions.cpp
M lldb/test/API/commands/expression/completion/TestExprCompletion.py
Log Message:
-----------
[lldb] returning command completions up to a maximum (#135565)
- Adding `max_return_elements` field to `CompletionRequest`.
- adding maximum checks to `SymbolCompleter` and `SourceFileCompleter`.
Fixes #135553
Commit: ee617f195a2677abd274e4047246fed3a1501b77
https://github.com/llvm/llvm-project/commit/ee617f195a2677abd274e4047246fed3a1501b77
Author: Guy David <49722543+guy-david at users.noreply.github.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
Log Message:
-----------
[NFC] [AArch64] Simplify offset scaling in ldst-opt (#137044)
Commit: cd826d6e840ed33ad88458c862da5f9fcc6e908c
https://github.com/llvm/llvm-project/commit/cd826d6e840ed33ad88458c862da5f9fcc6e908c
Author: Reid Kleckner <rnk at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGDebugInfo.h
M clang/lib/CodeGen/CodeGenModule.cpp
R clang/test/CodeGenCXX/debug-info-dtor-implicit-args.cpp
Log Message:
-----------
Revert "[Clang,debuginfo] added vtt parameter in destructor DISubroutineType (#130674)"
This reverts commit 27c1aa9b9cf9e0b14211758ff8f7d3aaba24ffcf.
See comments on PR. After this change, Clang now asserts like this:
clang: ../llvm/include/llvm/IR/Metadata.h:1435: const MDOperand &llvm::MDNode::getOperand(unsigned int) const: Assertion `I < getNumOperands() && "Out of range"' failed.
...
#8 0x000055f345c4e4cb clang::CodeGen::CGDebugInfo::getOrCreateInstanceMethodType()
#9 0x000055f345c5ba4f clang::CodeGen::CGDebugInfo::EmitFunctionDecl()
#10 0x000055f345b52519 clang::CodeGen::CodeGenModule::EmitExternalFunctionDeclaration()
This is due to pre-existing jankiness in the way BPF emits extra
declarations for debug info, but we should rollback and then fix forward.
Commit: dd17cf4480fc55c38813769a46fb2807397d8f72
https://github.com/llvm/llvm-project/commit/dd17cf4480fc55c38813769a46fb2807397d8f72
Author: Dave Lee <davelee.com at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/include/lldb/Interpreter/CommandObject.h
Log Message:
-----------
[lldb] Minor improvements to AddNamesMatchingPartialString (NFC) (#136760)
The primary changes are:
1. Avoid allocating a temporary `std::string` each time in the loop
2. Use `starts_with` instead of `find(...) == 0`
Commit: 0e0a1665fa340b9f1934d12aff818064aaf289ef
https://github.com/llvm/llvm-project/commit/0e0a1665fa340b9f1934d12aff818064aaf289ef
Author: Reid Kleckner <rnk at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/CodeGen/CodeGenModule.cpp
Log Message:
-----------
Revert unintentional diff from cd826d6e840ed33ad88458c862da5f9fcc6e908c
This is part of a forthcoming fix for issues observed in #91310, and was
unintentionally committed as part of the VTT type changes revert
Commit: b6f32ad8b03dccaba0db7ded9d561ee83e4530ab
https://github.com/llvm/llvm-project/commit/b6f32ad8b03dccaba0db7ded9d561ee83e4530ab
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
M llvm/test/CodeGen/NVPTX/LoadStoreVectorizer.ll
M llvm/test/CodeGen/NVPTX/and-or-setcc.ll
M llvm/test/CodeGen/NVPTX/atomics.ll
M llvm/test/CodeGen/NVPTX/bf16-instructions.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions-approx.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/convert-fp-i8.ll
M llvm/test/CodeGen/NVPTX/convert-sm100.ll
M llvm/test/CodeGen/NVPTX/convert-sm100a.ll
M llvm/test/CodeGen/NVPTX/convert-sm80.ll
M llvm/test/CodeGen/NVPTX/convert-sm90.ll
M llvm/test/CodeGen/NVPTX/copysign.ll
M llvm/test/CodeGen/NVPTX/distributed-shared-cluster.ll
M llvm/test/CodeGen/NVPTX/div.ll
M llvm/test/CodeGen/NVPTX/f16-abs.ll
M llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/f32-ex2.ll
M llvm/test/CodeGen/NVPTX/f32-lg2.ll
M llvm/test/CodeGen/NVPTX/fabs-intrinsics.ll
M llvm/test/CodeGen/NVPTX/fexp2.ll
M llvm/test/CodeGen/NVPTX/flog2.ll
M llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
M llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll
M llvm/test/CodeGen/NVPTX/fma-relu-instruction-flag.ll
M llvm/test/CodeGen/NVPTX/fp-contract.ll
M llvm/test/CodeGen/NVPTX/frem.ll
M llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
M llvm/test/CodeGen/NVPTX/intrinsics.ll
M llvm/test/CodeGen/NVPTX/ldg-invariant.ll
M llvm/test/CodeGen/NVPTX/ldu-ldg.ll
M llvm/test/CodeGen/NVPTX/load-store-scalars.ll
M llvm/test/CodeGen/NVPTX/load-store-vectors.ll
M llvm/test/CodeGen/NVPTX/math-intrins.ll
M llvm/test/CodeGen/NVPTX/misched_func_call.ll
M llvm/test/CodeGen/NVPTX/param-add.ll
M llvm/test/CodeGen/NVPTX/rcp-opt.ll
M llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
M llvm/test/CodeGen/NVPTX/redux-sync-f32.ll
M llvm/test/CodeGen/NVPTX/reg-types.ll
M llvm/test/CodeGen/NVPTX/st-param-imm.ll
M llvm/test/CodeGen/NVPTX/surf-read-cuda.ll
M llvm/test/CodeGen/NVPTX/tex-read-cuda.ll
M llvm/test/CodeGen/NVPTX/variadics-backend.ll
M llvm/test/DebugInfo/NVPTX/debug-info.ll
Log Message:
-----------
[NVPTX] Switch to untyped float registers (#137011)
Register types in PTX are simply syntactic sugar and emitting them has
added lots of unnecessary complexity to the NVPTX backend. This change
takes the first step to their removal by using ".b" registers instead of
".f" in all cases. This should shake out any potential issues or bugs in
ptxas preventing full removal and pre-fetches many of the required test
updates.
Commit: 9a8f90dba3f8c25cbb3525a482053d3abcd3fddc
https://github.com/llvm/llvm-project/commit/9a8f90dba3f8c25cbb3525a482053d3abcd3fddc
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
A llvm/include/llvm/ProfileData/IndexedMemProfData.h
M llvm/lib/ProfileData/CMakeLists.txt
A llvm/lib/ProfileData/IndexedMemProfData.cpp
M llvm/lib/ProfileData/InstrProfWriter.cpp
Log Message:
-----------
[memprof] Move writeMemProf to a separate file (#137051)
This patch moves writeMemProf and its subroutines to a separate file.
The intent is as follows:
- Reduce the size of InstrProfWriter.cpp.
- Move the subroutines to a separate file because they don't interact
with anything else in InstrProfWriter.cpp.
Remarks:
- The new file is named IndexedMemProfData.cpp without "Writer" in the
name so that we can move the reader code to this file in the future.
- This patch just moves code without changing the function signatures
for now. It might make sense to implement a class encompassing
"serialize" and "deserialize" methods for IndexedMemProfData, but
that's left to subsequent patches.
Commit: d72f1f92f469a5d0ee28dc89f72977634d90d111
https://github.com/llvm/llvm-project/commit/d72f1f92f469a5d0ee28dc89f72977634d90d111
Author: GeorgeHuyubo <113479859+GeorgeHuyubo at users.noreply.github.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
Log Message:
-----------
Bug fix in FindModuleUUID (#137075)
In some core file, we are seeing that it's not always the case that the
ELF header would exist in the first region in NT_FILES section.
Therefore the FindModuleUUID is not able to find the module UUID by just
returning the first entry with path matching.
This fix change the behavior to continue search the NT_FILE entries
until finding a valid UUID with path matching.
Co-authored-by: George Hu <georgehuyubo at gmail.com>
Commit: 0d00b6bc3b459122de47d16c5153887063f4ea4b
https://github.com/llvm/llvm-project/commit/0d00b6bc3b459122de47d16c5153887063f4ea4b
Author: gulfemsavrun <gulfem at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/hdr/CMakeLists.txt
R libc/hdr/offsetof_macros.h
M libc/include/llvm-libc-types/CMakeLists.txt
M libc/include/llvm-libc-types/jmp_buf.h
M libc/include/setjmp.yaml
M libc/src/setjmp/CMakeLists.txt
R libc/src/setjmp/linux/CMakeLists.txt
R libc/src/setjmp/linux/sigsetjmp_epilogue.cpp
M libc/src/setjmp/setjmp_impl.h
R libc/src/setjmp/siglongjmp.cpp
R libc/src/setjmp/siglongjmp.h
R libc/src/setjmp/sigsetjmp.h
R libc/src/setjmp/sigsetjmp_epilogue.h
M libc/src/setjmp/x86_64/CMakeLists.txt
M libc/src/setjmp/x86_64/setjmp.cpp
R libc/src/setjmp/x86_64/sigsetjmp.cpp
M libc/test/src/setjmp/CMakeLists.txt
R libc/test/src/setjmp/sigsetjmp_test.cpp
Log Message:
-----------
Revert "[libc] build fix for sigsetjmp (#137047)" (#137077)
This reverts commit f07511a0e0d2ac9bee9ae12a9ad68e279e352634.
This reverts commit 5bb4cf9d9189c41de50adffd960eb2188140eb9c.
It caused a CMake configuration issue.
Commit: 6388a7acf7e31fdc7b9c168bd6ce0f4d25c98cd0
https://github.com/llvm/llvm-project/commit/6388a7acf7e31fdc7b9c168bd6ce0f4d25c98cd0
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
Log Message:
-----------
[RISCV] Check the extension type for atomic loads in isel patterns. (#137019)
Previously we ignored the extension type and only used the memory type.
The extension type on RISC-V today can only be nonextload, extload, or
sextload. It is ok to treat extload as the same as sextload so ignoring
the extension type is fine.
For #136502, we want to support zextload as well so we will need to
disambiguate based on the extension type.
I wanted to use IsAtomic/IsZeroExtLoad/IsSignExtLoad/IsAnyExtLoad flags
from PatFrags to autogenerate the predicates, but those aren't hooked up
properly in tablegen for ISD::ATOMIC_LOAD. Fixing that will impact other
targets as almost all of them also ignore the extension type.
Commit: 0547e84181ff10b24d6363bbfc97f168fe245397
https://github.com/llvm/llvm-project/commit/0547e84181ff10b24d6363bbfc97f168fe245397
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/IPO/FunctionAttrs.cpp
M llvm/test/Transforms/FunctionAttrs/initializes.ll
Log Message:
-----------
[FunctionAttrs] Bail if initializes range overflows 64-bit signed int (#137053)
Otherwise the range doesn't make sense since we interpret it as signed.
Fixes #134115
Commit: f75295f7982ee893473db6c3dc59886e02cd728c
https://github.com/llvm/llvm-project/commit/f75295f7982ee893473db6c3dc59886e02cd728c
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/ProfileData/BUILD.gn
Log Message:
-----------
[gn build] Port 9a8f90dba3f8
Commit: 4f36ada1e205df08ad4377df88729f8defb36558
https://github.com/llvm/llvm-project/commit/4f36ada1e205df08ad4377df88729f8defb36558
Author: Bob Wilson <bob.wilson at apple.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/test/Preprocessor/print-header-json.c
M clang/tools/driver/driver.cpp
Log Message:
-----------
[Clang] Fix crash when -header-include-filtering is not specified (#136232)
If you specify -header-include-format=json, the only filtering option
currently supported is -header-include-filtering=only-direct-system. If
you specify some other filtering option, Clang gives an error message.
But, if you do not specify the filtering option at all, Clang crashes
when producing the error message, since it tries to get the value of the
unused option.
Commit: 239718055d7260caa3e6631e82d68ac27e01c1f4
https://github.com/llvm/llvm-project/commit/239718055d7260caa3e6631e82d68ac27e01c1f4
Author: Robert O'Callahan <rocallahan at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/source/Commands/CommandObjectProcess.cpp
M lldb/source/Commands/Options.td
A lldb/test/API/commands/process/reverse-continue/Makefile
A lldb/test/API/commands/process/reverse-continue/TestReverseContinue.py
A lldb/test/API/commands/process/reverse-continue/TestReverseContinueNotSupported.py
A lldb/test/API/commands/process/reverse-continue/main.c
M llvm/docs/ReleaseNotes.md
Log Message:
-----------
[lldb] Implement CLI support for reverse-continue (#132783)
This introduces the options "-F/--forward" and "-R/--reverse" to
`process continue`.
These only work if you're running with a gdbserver backend that supports
reverse execution, such as rr. For testing we rely on the fake
reverse-execution functionality in `lldbreverse.py`.
Commit: 55160e6a89820f219eaa218fa02da2006213ed2c
https://github.com/llvm/llvm-project/commit/55160e6a89820f219eaa218fa02da2006213ed2c
Author: Henrik G. Olsson <hnrklssn at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/AST/ExprConstant.cpp
M clang/test/AST/ByteCode/cxx20.cpp
M clang/test/SemaCXX/constant-expression-cxx11.cpp
Log Message:
-----------
[ConstEval] Fix crash when comparing strings past the end (#137078)
When `ArePotentiallyOverlappingStringLiterals`, added in
https://github.com/llvm/llvm-project/pull/109208, compares string
literals it drops the front of the string with the greatest offset from
its base pointer. The number of characters dropped is equal to the
difference between the two strings' offsets from their base pointers.
This would trigger an assert when the resulting offset is past the end
of the object. Not only are one-past-the-end pointers legal constructs,
the compiler should not crash even when faced with illegal constructs.
rdar://149865910
Commit: de2f9395e6617e58e168fa3b2886f85109849787
https://github.com/llvm/llvm-project/commit/de2f9395e6617e58e168fa3b2886f85109849787
Author: Adrian Prantl <aprantl at apple.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/source/Plugins/ExpressionParser/Clang/ClangModulesDeclVendor.cpp
Log Message:
-----------
[lldb] Quote module name in error message (#137083)
rdar://149554634
Commit: 93705c3a76e9b00137be84fbc6ef3b4af5fcc031
https://github.com/llvm/llvm-project/commit/93705c3a76e9b00137be84fbc6ef3b4af5fcc031
Author: Henrik G. Olsson <hnrklssn at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/AST/ExprConstant.cpp
M clang/test/AST/ByteCode/cxx20.cpp
M clang/test/SemaCXX/constant-expression-cxx11.cpp
Log Message:
-----------
Revert "[ConstEval] Fix crash when comparing strings past the end" (#137088)
Reverts llvm/llvm-project#137078
Commit: 6ba704a7f4e72ba088fa19c7622e42b9c460da47
https://github.com/llvm/llvm-project/commit/6ba704a7f4e72ba088fa19c7622e42b9c460da47
Author: John Harrison <harjohn at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/tools/lldb-dap/Handler/NextRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
M lldb/tools/lldb-dap/Handler/StepInRequestHandler.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
Log Message:
-----------
[lldb-dap] Migrate 'stepIn' request to well structured types. (#137071)
Migrates the 'stepIn' request handler to have well structured types
instead of raw json values.
I also noticed in the 'next' request handler we were not passing the
'RunMode' flag. Updated the 'next' request handler as well.
Commit: fc7fee8360b3e69777fa1c5c3c563728b1a2836f
https://github.com/llvm/llvm-project/commit/fc7fee8360b3e69777fa1c5c3c563728b1a2836f
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
M llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
M llvm/test/CodeGen/RISCV/xqccmp-additional-stack.ll
M llvm/test/CodeGen/RISCV/xqccmp-callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
M llvm/test/CodeGen/RISCV/xqccmp-with-float.ll
M llvm/test/CodeGen/RISCV/zcmp-additional-stack.ll
M llvm/test/CodeGen/RISCV/zcmp-with-float.ll
Log Message:
-----------
Revert "[RISCV] Allow spilling to unused Zcmp Stack (#125959)" (#137060)
This reverts commit 50cdf6cbc5035345507bb4d23fcb0292272754eb.
This patch causes miscompiles with vector and produces some odd code for
ilp32e.
Commit: 905f1d8068a5bc1149732b46afc3f5dd780aa5d9
https://github.com/llvm/llvm-project/commit/905f1d8068a5bc1149732b46afc3f5dd780aa5d9
Author: Muzammil <55665739+Muzammiluddin-Syed-ECE at users.noreply.github.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/GPU/Transforms/Passes.h
M mlir/lib/Dialect/GPU/Transforms/SubgroupReduceLowering.cpp
M mlir/test/Dialect/GPU/subgroup-reduce-lowering.mlir
M mlir/test/lib/Dialect/GPU/TestGpuRewrite.cpp
Log Message:
-----------
[mlir][AMDGPU] Implement gpu.subgroup_reduce with DPP intrinsics on AMD GPUs (#133204)
When performing cross-lane reductions using subgroup_reduce ops across
contiguous lanes on AMD GPUs, lower to Data Parallel Primitives (DPP)
ops when possible. This reduces latency on applicable devices.
See related [Issue](https://github.com/iree-org/iree/issues/20007)
To do:
- Improve lowering to subgroup_reduce in compatible matvecs (these get
directly lowered to gpu.shuffles in an earlier pass)
---------
Signed-off-by: Muzammiluddin Syed <muzasyed at amd.com>
Commit: 0400b8e8fd2ff66c8faab1fa818dec8199d969ce
https://github.com/llvm/llvm-project/commit/0400b8e8fd2ff66c8faab1fa818dec8199d969ce
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/test/Driver/fsanitize.c
M clang/test/Driver/sanitizer-ld.c
Log Message:
-----------
[NFC][CFI] Add CFI minimal runtime tests (#137093)
Commit: 9ad219372a31ec362b8ea462d694b8b819127235
https://github.com/llvm/llvm-project/commit/9ad219372a31ec362b8ea462d694b8b819127235
Author: Evgenii Kudriashov <evgenii.kudriashov at intel.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/test/CodeGen/X86/extractelement-load.ll
Log Message:
-----------
[X86][NFC] Precommit test for #136520
Commit: adab66f7a5b1f0f9ee00f42cf0ac517ba2b58e90
https://github.com/llvm/llvm-project/commit/adab66f7a5b1f0f9ee00f42cf0ac517ba2b58e90
Author: Jorge Gorbe Moya <jgorbe at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Add missing deps after 905f1d8068a5bc1149732b46afc3f5dd780aa5d9
Commit: b45225fd0c756d969f1188baaef374dffd561aa2
https://github.com/llvm/llvm-project/commit/b45225fd0c756d969f1188baaef374dffd561aa2
Author: Jim Lin <jim at andestech.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/utils/vim/syntax/llvm.vim
Log Message:
-----------
[Utils][vim] Add missing highlights for disjoint (#136801)
This patch adds the `disjoint` as keyword.
Commit: 5981be76925c2d6ee5b33029332beae254addb46
https://github.com/llvm/llvm-project/commit/5981be76925c2d6ee5b33029332beae254addb46
Author: Jim Lin <jim at andestech.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/test/Driver/riscv-cpus.c
M clang/test/Misc/target-invalid-cpu-note/riscv.c
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/RISCVProcessors.td
Log Message:
-----------
[RISCV] Add Andes A45/AX45 processor definition (#136832)
Andes A45/AX45 are 32/64bit in-order dual-issue 8-stage pipeline
linux-capable CPU implementing the RV[32|64]IMAFDC_Zba_Zbb_Zbs ISA
extensions. They are developed by Andes Technology
https://www.andestech.com, a RISC-V IP provider.
The overviews for A45/AX45:
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-a45/
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45/
Scheduling model will be implemented in a later PR.
Commit: a68c8e831452febc82ffb4091134aeb87ca52c2b
https://github.com/llvm/llvm-project/commit/a68c8e831452febc82ffb4091134aeb87ca52c2b
Author: Cedric <14017092+douyixuan at users.noreply.github.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/Vector/invalid.mlir
Log Message:
-----------
[mlir][vector] Fix parser of vector.transfer_read (#133721)
This PR adds a check in the parser to prevent a crash when
vector.transfer_read fails to create minor identity permutation. map.
Fixes #132851
a.mlir
```
module {
func.func @test_vector.transfer_read(%arg1: memref<?xindex>) -> vector<3x4xi32> {
%c3_i32 = arith.constant 3 : i32
%0 = vector.transfer_read %arg1[%c3_i32, %c3_i32], %c3_i32 : memref<?xindex>, vector<3x4xi32>
return %0 : vector<3x4xi32>
}
}
```
Commit: 178cdbf746bbc49ad18b5e83a95514ddd42f764c
https://github.com/llvm/llvm-project/commit/178cdbf746bbc49ad18b5e83a95514ddd42f764c
Author: Jorge Gorbe Moya <jgorbe at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
[bazel] Add missing deps in mlir/test/BUILD.bazel after 905f1d8068a5bc1149732b46afc3f5dd780aa5d9
Commit: 30fec128e8cc515392521628771510b347411c28
https://github.com/llvm/llvm-project/commit/30fec128e8cc515392521628771510b347411c28
Author: Muzammil <55665739+Muzammiluddin-Syed-ECE at users.noreply.github.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/lib/Dialect/GPU/CMakeLists.txt
Log Message:
-----------
[mlir][AMDGPU] Add missing dependency (#137107)
Add missing deps after
https://github.com/llvm/llvm-project/commit/905f1d8068a5bc1149732b46afc3f5dd780aa5d9
---------
Signed-off-by: Muzammiluddin Syed <muzasyed at amd.com>
Commit: ea0dbee80813edf1c8a57d1c1bfd7fadee71d3fa
https://github.com/llvm/llvm-project/commit/ea0dbee80813edf1c8a57d1c1bfd7fadee71d3fa
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/ProfileData/IndexedMemProfData.cpp
M llvm/lib/ProfileData/InstrProfReader.cpp
Log Message:
-----------
[memprof] Move IndexedMemProfReader::deserialize to IndexedemProfData.cpp (NFC) (#137089)
This patch moves IndexedMemProfReader::deserialize and its subroutines
to IndexedMemProfData.cpp, building on:
commit 9a8f90dba3f8c25cbb3525a482053d3abcd3fddc
Author: Kazu Hirata <kazu at google.com>
Date: Wed Apr 23 15:39:45 2025 -0700
The intent is as follows:
- Reduce the size of InstrProfReader.cpp.
- Move the subroutines to a separate file because they don't interact
with anything else in InstrProfReader.cpp.
Commit: de1af6b7271c6f4fc67848a849cf8fa6000d2b97
https://github.com/llvm/llvm-project/commit/de1af6b7271c6f4fc67848a849cf8fa6000d2b97
Author: Henrik G. Olsson <hnrklssn at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/AST/ExprConstant.cpp
M clang/test/AST/ByteCode/cxx20.cpp
M clang/test/SemaCXX/constant-expression-cxx11.cpp
Log Message:
-----------
Eval string one past end reland (#137091)
Relands #137078 after updating clang/test/AST/ByteCode/cxx20.cpp to
account for diagnostic outputs that differ between Linux and macOS.
Commit: 0975c09c671aca48c25b1f5952a675931ae93702
https://github.com/llvm/llvm-project/commit/0975c09c671aca48c25b1f5952a675931ae93702
Author: Oliver Hunt <oliver at apple.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
A clang/test/Modules/Inputs/PR137102/module.modulemap
A clang/test/Modules/Inputs/PR137102/type_aware_destroying_new_delete.h
A clang/test/Modules/type-aware-destroying-new-and-delete-modules.cpp
A clang/test/PCH/Inputs/type_aware_destroying_new_delete.h
A clang/test/PCH/type-aware-destroying-new-and-delete-pch.cpp
Log Message:
-----------
[clang][p2719] Module deserialization does not restore allocator flags (#137102)
When serializing and deserializing a FunctionDecl we don't recover
whether or not the decl was a type aware allocator or destroying delete,
because in the final PR that information was placed in a side table in
ASTContext.
In principle it should be possible to re-do the semantic checks to
determine what these flags should be when deserializing, but it seems
like the most robust path is simply recording the flags directly in the
serialized AST.
Commit: e6466420505d9940fda087f30a500fb03e5507b5
https://github.com/llvm/llvm-project/commit/e6466420505d9940fda087f30a500fb03e5507b5
Author: Bruno Cardoso Lopes <bruno.cardoso at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/test/Dialect/LLVMIR/invalid.mlir
M mlir/test/Dialect/LLVMIR/module-roundtrip.mlir
M mlir/test/Target/LLVMIR/Import/module-flags.ll
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[MLIR][LLVM] Allow strings in module flag value (#136793)
Expand support a bit beyond integers.
Next step is to support more complex metadata values (e.g. !"CG Profile"
and !"ProfileSummary"), but that's a bit more complex and deserves it
own PR.
Commit: cb8495c0fcf32592c6fcd23429b702dccb57d2eb
https://github.com/llvm/llvm-project/commit/cb8495c0fcf32592c6fcd23429b702dccb57d2eb
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/Driver/SanitizerArgs.cpp
M clang/test/Driver/fsanitize.c
M clang/test/Driver/sanitizer-ld.c
Log Message:
-----------
[Driver][CFI] Add missing '-' into error message (#137097)
Co-authored-by: Jim Lin <jim at andestech.com>
Commit: cd92d8db34afd95335697f85a527028fa8309d18
https://github.com/llvm/llvm-project/commit/cd92d8db34afd95335697f85a527028fa8309d18
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/test/Format/lit.local.cfg
Log Message:
-----------
[clang-format][NFC] Reformat clang/test/Format/lit.local.cfg with black
Commit: cb96a3dc07b0a26023633ae91fab9b4213730236
https://github.com/llvm/llvm-project/commit/cb96a3dc07b0a26023633ae91fab9b4213730236
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
A llvm/test/Transforms/PGOProfile/memprof-dump-matched-alloc-site.ll
M llvm/test/Transforms/PGOProfile/memprof-dump-matched-call-sites.ll
M llvm/test/Transforms/PGOProfile/memprof.ll
Log Message:
-----------
[memprof] Dump the number of matched frames (#137082)
This patch teaches readMemprof to dump the number of frames for each
allocation site match. This information helps us analyze what part of
the call stack in the MemProf profile has matched the IR.
Aside from updating existing test cases, this patch adds one more test
case, memprof-dump-matched-alloc-site.ll, because none of the existing
test cases has the number of frames greater than one.
Commit: 77fe6aaeaaf2b16e021675e92e543dafd18bbc0b
https://github.com/llvm/llvm-project/commit/77fe6aaeaaf2b16e021675e92e543dafd18bbc0b
Author: Wenju He <wenju.he at intel.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M libclc/cmake/modules/AddLibclc.cmake
Log Message:
-----------
[libclc] only check filename part of the source for avoiding duplication (#135710)
llvm-diff shows this PR has no changes to amdgcn--amdhsa.bc.
Motivation is that in our downstream the same category of target
built-ins, e.g. math, are organized in several different folders. For
example, in target SOURCES we have math-common/cos.cl, while in generic
SOURCES it is math/cos.cl. Based on current check rule that compares
both folder name and base filename, target math-common/cos.cl won't
override math/cos.cl when collecting source files from SOURCES files in
cmake function libclc_configure_lib_source.
With this PR, we allow folder name to be different in the process.
A notable change of this PR is that two entries in SOURCES with the same
base filename must not implements the same built-in.
Commit: 31c7997a4acb838c94d5ab40baaf154556532ad9
https://github.com/llvm/llvm-project/commit/31c7997a4acb838c94d5ab40baaf154556532ad9
Author: Thurston Dang <thurston at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/CodeGen/CGClass.cpp
M clang/lib/CodeGen/CGExpr.cpp
Log Message:
-----------
[cfi] Fix one -fno-sanitize-merge case, and add two TODOs (#135438)
-fno-sanitize-merge (introduced in
https://github.com/llvm/llvm-project/pull/120464) nearly works for CFI:
code that calls EmitCheck will already check the merge options. This
patch fixes one EmitTrapCheck call, which did not check the merge
options, and for two other EmitTrapChecks, adds two TODOs that explain
why it is difficult to fix them.
Commit: 096ab51de03437e38f97a48b8f2d453fb903414a
https://github.com/llvm/llvm-project/commit/096ab51de03437e38f97a48b8f2d453fb903414a
Author: Jason Molenda <jmolenda at apple.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/Process/Utility/CMakeLists.txt
A lldb/source/Plugins/Process/Utility/RegisterContextDarwin_riscv32.cpp
A lldb/source/Plugins/Process/Utility/RegisterContextDarwin_riscv32.h
A lldb/test/API/macosx/riscv32-corefile/Makefile
A lldb/test/API/macosx/riscv32-corefile/TestRV32MachOCorefile.py
A lldb/test/API/macosx/riscv32-corefile/create-empty-riscv-corefile.cpp
Log Message:
-----------
[lldb][MachO] MachO corefile support for riscv32 binaries (#137092)
Add support for reading a macho corefile with CPU_TYPE_RISCV and the
riscv32 general purpose register file. I added code for the floating
point and exception registers too, but haven't exercised this. If we
start putting the full CSR register bank in a riscv corefile, it'll be
in separate 4k byte chunks, but I don't have a corefile to test against
that so I haven't written the code to read it.
The RegisterContextDarwin_riscv32 is copied & in the style of the other
RegisterContextDarwin classes; it's not the first choice I would make
for representing this, but it wasn't worth changing for this cputype.
rdar://145014653
Commit: 054ee17f88fcd4dd8d646740b975ef1d2f4ea3aa
https://github.com/llvm/llvm-project/commit/054ee17f88fcd4dd8d646740b975ef1d2f4ea3aa
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn
Log Message:
-----------
[gn build] Port 096ab51de034
Commit: dbb0605f87d8b10171fba6291dd184f5fbf17683
https://github.com/llvm/llvm-project/commit/dbb0605f87d8b10171fba6291dd184f5fbf17683
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Log Message:
-----------
[SelectionDAG] Add NewSDValueDbgMsg to getAtomic.
Commit: fb0000b6624a5f2df25d10e3667111e96dd1abd5
https://github.com/llvm/llvm-project/commit/fb0000b6624a5f2df25d10e3667111e96dd1abd5
Author: Ebuka Ezike <yerimyah1 at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M lldb/include/lldb/Interpreter/OptionValueEnumeration.h
M lldb/source/Interpreter/OptionValueEnumeration.cpp
M lldb/test/API/commands/settings/TestSettings.py
Log Message:
-----------
[lldb][lldb-dap] Add ToJSON for OptionValueEnumeration (#137007)
This automatically enables reading enum settings in the SB API
Commit: de81b852fd8d2b654e1c7112f198026aa272c6b3
https://github.com/llvm/llvm-project/commit/de81b852fd8d2b654e1c7112f198026aa272c6b3
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/sve-varargs-caller-broken.ll
M llvm/test/CodeGen/AArch64/sve-varargs.ll
Log Message:
-----------
[AArch64] Allow variadic calls with SVE argument if it is named. (#136833)
The following case used to work:
void foo(svint32_t a, ...);
void bar(svint32_t a) { foo(a); }
but 6c9086d13fa7e1069e75ed2d139aae30ee3863c8 introduced a regression
that wasn't caught by the existing test `sve-varargs.ll` because the
call in the test wasn't a tail call and therefore skipped the code-path
with the `report_fatal_error`.
Commit: 45a3056a4b3b05d2d1bce7a96437dddead60c071
https://github.com/llvm/llvm-project/commit/45a3056a4b3b05d2d1bce7a96437dddead60c071
Author: Kiran Chandramohan <kiran.chandramohan at arm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
A flang/docs/FortranStandardsSupport.md
M flang/docs/index.md
Log Message:
-----------
[Flang] Add a Fortran Standards Support doc (#132195)
Commit: 7af555e524b5cddc338bf73b87d8b666611cefbc
https://github.com/llvm/llvm-project/commit/7af555e524b5cddc338bf73b87d8b666611cefbc
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/ARM/popcnt.ll
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
M llvm/test/CodeGen/RISCV/pr56457.ll
M llvm/test/CodeGen/RISCV/pr95271.ll
M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/RISCV/sextw-removal.ll
M llvm/test/CodeGen/Thumb2/mve-ctpop.ll
Log Message:
-----------
[ARM][RISCV] Partially revert #101786 (#137120)
The change as is breaks the Linux kernel build as pointed out in the
comments.
Commit: 886f1199f07bbcc385e35b90b9e620cbc8d76068
https://github.com/llvm/llvm-project/commit/886f1199f07bbcc385e35b90b9e620cbc8d76068
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Log Message:
-----------
[AMDGPU] Use variadic isa<>. NFC. (#137016)
Commit: bea110db3ed1fa1215bb8e22d2057019fcbd2d16
https://github.com/llvm/llvm-project/commit/bea110db3ed1fa1215bb8e22d2057019fcbd2d16
Author: Hampus Adolfsson <15944368+HampusAdolfsson at users.noreply.github.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang-tools-extra/clangd/XRefs.cpp
M clang-tools-extra/clangd/unittests/CallHierarchyTests.cpp
Log Message:
-----------
[clangd] Strip invalid fromRanges for outgoing calls (#134657)
`CallHierarchyOutgoingCall::fromRanges` are interpreted as ranges in the
same file as the item for which 'outgoingCalls' was called.
It's possible for outgoing calls to be in a different file than that
item if the item is just a declaration (e.g. in a header file). Now,
such calls are dropped instead of being returned to the client.
This is the same as the change made in #111616, but now for outgoing
calls.
Fixes clangd/clangd#2350
---------
Co-authored-by: Nathan Ridge <zeratul976 at hotmail.com>
Commit: 15bb1db4a98309f8769fa6d53a52eae62a61fbb2
https://github.com/llvm/llvm-project/commit/15bb1db4a98309f8769fa6d53a52eae62a61fbb2
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll
M llvm/test/Transforms/LoopVectorize/X86/pr51366-sunk-instruction-used-outside-of-loop.ll
M llvm/test/Transforms/LoopVectorize/X86/small-size.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll
Log Message:
-----------
[VPlan] Remove ILV::sinkScalarOperands. (#136023)
Remove legacy ILV sinkScalarOperands, which is superseded by the
sinkScalarOperands VPlan transforms.
There are a few cases that aren't handled by VPlan's sinkScalarOperands,
because the recipes doesn't support replicating. Those are pointer
inductions and blends.
We could probably improve this further, by allowing replication for more
recipes, but I don't think the extra complexity is warranted.
Depends on https://github.com/llvm/llvm-project/pull/136021.
PR: https://github.com/llvm/llvm-project/pull/136023
Commit: 0c61b24337236a0f67be54c26e12c98e9aecef5b
https://github.com/llvm/llvm-project/commit/0c61b24337236a0f67be54c26e12c98e9aecef5b
Author: Oleksandr "Alex" Zinenko <git at ozinenko.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M flang/lib/Optimizer/CodeGen/LowerRepackArrays.cpp
M flang/lib/Optimizer/HLFIR/Transforms/InlineElementals.cpp
M flang/lib/Optimizer/HLFIR/Transforms/InlineHLFIRAssign.cpp
M flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
M flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/AssumedRankOpConversion.cpp
M flang/lib/Optimizer/Transforms/ConstantArgumentGlobalisation.cpp
M flang/lib/Optimizer/Transforms/SimplifyFIROperations.cpp
M flang/lib/Optimizer/Transforms/StackArrays.cpp
M mlir/include/mlir/Transforms/GreedyPatternRewriteDriver.h
M mlir/include/mlir/Transforms/Passes.td
M mlir/lib/Dialect/Affine/TransformOps/AffineTransformOps.cpp
M mlir/lib/Dialect/Affine/Transforms/AffineDataCopyGeneration.cpp
M mlir/lib/Dialect/Affine/Transforms/SimplifyAffineStructures.cpp
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/lib/Dialect/Affine/Utils/Utils.cpp
M mlir/lib/Dialect/Arith/Transforms/IntRangeOptimizations.cpp
M mlir/lib/Dialect/Bufferization/Transforms/BufferDeallocationSimplification.cpp
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp
M mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp
M mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
M mlir/lib/Dialect/Transform/IR/TransformOps.cpp
M mlir/lib/Reducer/ReductionTreePass.cpp
M mlir/lib/Transforms/Canonicalizer.cpp
M mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
M mlir/test/lib/Dialect/Affine/TestAffineDataCopy.cpp
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
Log Message:
-----------
[mlir] add a fluent API to GreedyRewriterConfig (#137122)
This is similar to other configuration objects used across MLIR.
Rename some fields to better reflect that they are no longer booleans.
Reland 04d261101b4f229189463136a794e3e362a793af / #132253.
Commit: e268f71c5900f13207a7cd942f856f5852233d9e
https://github.com/llvm/llvm-project/commit/e268f71c5900f13207a7cd942f856f5852233d9e
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[VPlan] Remove unneeded early continue. (NFC)
As suggested in
https://github.com/llvm/llvm-project/pull/136455, now unreachable exit
blocks won't have any phi nodes.
Commit: a3d05e89873654dd1b27979b2bfd82ddd4859ba7
https://github.com/llvm/llvm-project/commit/a3d05e89873654dd1b27979b2bfd82ddd4859ba7
Author: anjenner <161845516+anjenner at users.noreply.github.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.AFLCustomIRMutator.opt.ll
Log Message:
-----------
Remove an incorrect assert in MFMASmallGemmSingleWaveOpt. (#130131)
This assert was failing in a fuzzing test. I consulted with @jrbyrnes
who said:
The MFMASmallGemmSingleWaveOpt::apply() method is invoked if and only if
the user has inserted an intrinsic llvm.amdgcn.iglp.opt(i32 1) into
their source code. This intrinsic applies a highly specialized DAG
mutation to result in specific scheduling for a specific set of kernels.
These assertions are really just confirming that the characteristics of
the kernel match what is expected (i.e. The kernels are similar to the
ones this DAG mutation strategy were designed against).
However, if we apply this DAG mutation to kernels for which is was not
designed, then we may not find the types of instructions we are looking
for, and may end up with empty caches.
I think it should be fine to just return false if the cache is empty
instead of the assert.
Commit: 03c2862404a9ab19940f87f8fb2dbe01818ab439
https://github.com/llvm/llvm-project/commit/03c2862404a9ab19940f87f8fb2dbe01818ab439
Author: Yuzhiy <44502685+Yuzhiy05 at users.noreply.github.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M libcxx/include/__ranges/to.h
M libcxx/test/libcxx/ranges/range.utility/range.utility.conv/to.static_assert.verify.cpp
Log Message:
-----------
[libc++][ranges] Reject non-class types in ranges::to (#135802)
This patch adds `static_assert` using `is_class_v` and `is_union_v` to
reject no-class type template parameters.
Fixes #132133
---------
Co-authored-by: A. Jiang <de34 at live.cn>
Commit: a2f00e1f8f124667339b94ffa144c0ff0d6ae3b3
https://github.com/llvm/llvm-project/commit/a2f00e1f8f124667339b94ffa144c0ff0d6ae3b3
Author: Luke Lau <luke at igalia.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
Log Message:
-----------
[RISCV] Add fixed-length patterns for disjoint or patterns for vwadd[u].v{v,x} (#136824)
This is the fixed-length equivalent of #136716.
The pattern we need to match is ({s,z}ext_vl (or_vl disjoint a, b)).
This only allows or_vls with an undef passthru, which allows us to
ignore its mask and vl and just take it from the {s,z}ext_vl.
A riscv_or_vl_is_add_oneuse PatFrag is added to mirror or_is_add in
RISCVInstrInfo.td.
Commit: 3883b27ba8a85c0228d5e49cb59d127d14dd0f8d
https://github.com/llvm/llvm-project/commit/3883b27ba8a85c0228d5e49cb59d127d14dd0f8d
Author: Luke Lau <luke at igalia.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
Log Message:
-----------
[VPlan] Fix typo in assertion. NFC (#137009)
Commit: be044976b6c27a5553d7e83d60f64c4a72c0de52
https://github.com/llvm/llvm-project/commit/be044976b6c27a5553d7e83d60f64c4a72c0de52
Author: SivanShani-Arm <sivan.shani at arm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsAArch64.def
M clang/lib/Headers/arm_acle.h
M clang/test/CodeGen/AArch64/gcs.c
Log Message:
-----------
[AArch64] Update __gcsss intrinsic to match revised ACLE specification (#136850)
The original __gcsss intrinsic was implemented based on:
https://github.com/ARM-software/acle/pull/260
with the signature: const void *__gcsss(const void *)
Per the updated specification in:
https://github.com/ARM-software/acle/pull/364
both const qualifiers have been removed. This commit updates the
signature accordingly to: void *__gcsss(void *)
This aligns the implementation with the latest ACLE definition.
Commit: 59b26abbbe89994c2ffd50a933654be247b68aaf
https://github.com/llvm/llvm-project/commit/59b26abbbe89994c2ffd50a933654be247b68aaf
Author: Camsyn <camsyn at foxmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
A compiler-rt/test/tsan/stack_race3.cpp
M llvm/lib/Transforms/Instrumentation/SanitizerBinaryMetadata.cpp
M llvm/lib/Transforms/Instrumentation/ThreadSanitizer.cpp
M llvm/test/Instrumentation/ThreadSanitizer/capture.ll
Log Message:
-----------
[TSan, SanitizerBinaryMetadata] Analyze the capture status for `alloca` rather than arbitrary `Addr` (#132756)
This PR is based on my last PR #132752 (the first commit of this PR),
but addressing a different issue.
This commit addresses the limitation in `PointerMayBeCaptured` analysis
when dealing with derived pointers (e.g. arr+1) as described in issue
#132739.
The current implementation of `PointerMayBeCaptured` may miss captures
of the underlying `alloca` when analyzing derived pointers, leading to
some FNs in TSan, as follows:
```cpp
void *Thread(void *a) {
((int*)a)[1] = 43;
return 0;
}
int main() {
int Arr[2] = {41, 42};
pthread_t t;
pthread_create(&t, 0, Thread, &Arr[0]);
// Missed instrumentation here due to the FN of PointerMayBeCaptured
Arr[1] = 43;
barrier_wait(&barrier);
pthread_join(t, 0);
}
```
Refer to this [godbolt page](https://godbolt.org/z/n67GrxdcE) to get the
compilation result of TSan.
Even when `PointerMayBeCaptured` working correctly, it should backtrack
to the original `alloca` firstly during analysis, causing redundancy to
the outer's `findAllocaForValue`.
```cpp
const AllocaInst *AI = findAllocaForValue(Addr);
// Instead of Addr, we should check whether its base pointer is captured.
if (AI && !PointerMayBeCaptured(Addr, true)) ...
```
Key changes:
Directly analyze the capture status of the underlying `alloca` instead
of derived pointers to ensure accurate capture detection
```cpp
const AllocaInst *AI = findAllocaForValue(Addr);
// Instead of Addr, we should check whether its base pointer is captured.
if (AI && !PointerMayBeCaptured(AI, true)) ...
```
Commit: 1ec22fae7e2c72b763b1c5ee6b743c59b5a4064c
https://github.com/llvm/llvm-project/commit/1ec22fae7e2c72b763b1c5ee6b743c59b5a4064c
Author: Jonas Paulsson <paulson1 at linux.ibm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZInstrFP.td
M llvm/test/CodeGen/SystemZ/fp-abs-01.ll
M llvm/test/CodeGen/SystemZ/fp-abs-02.ll
M llvm/test/CodeGen/SystemZ/fp-abs-03.ll
M llvm/test/CodeGen/SystemZ/fp-abs-04.ll
M llvm/test/CodeGen/SystemZ/fp-mul-08.ll
M llvm/test/CodeGen/SystemZ/fp-mul-10.ll
M llvm/test/CodeGen/SystemZ/fp-neg-01.ll
M llvm/test/CodeGen/SystemZ/fp-neg-02.ll
Log Message:
-----------
[SystemZ] Handle f16 load positive/negative/complement without libcalls. (#136286)
This can be done directly with the (64-bit) target instruction as only the sign bit
is changed.
Commit: 55066b83612b6bcc8c38ef6a84e5230ad116730f
https://github.com/llvm/llvm-project/commit/55066b83612b6bcc8c38ef6a84e5230ad116730f
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
A clang/test/AST/ByteCode/i686.cpp
Log Message:
-----------
[clang][bytecode] Compute pointer differences as 64bit integers (#137128)
And only convert to the target type after that.
Commit: 94a14f9f0d884eebb87fb3003229ffee5f95d1c8
https://github.com/llvm/llvm-project/commit/94a14f9f0d884eebb87fb3003229ffee5f95d1c8
Author: Jonas Paulsson <paulson1 at linux.ibm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.h
M llvm/lib/Target/SystemZ/SystemZInstrFP.td
M llvm/test/CodeGen/SystemZ/fp-copysign-01.ll
M llvm/test/CodeGen/SystemZ/fp-copysign-02.ll
M llvm/test/CodeGen/SystemZ/fp-copysign-03.ll
Log Message:
-----------
[SystemZ] Add DAGCombine for FCOPYSIGN to remove rounding. (#136131)
Add a DAGCombine for FCOPYSIGN that removes the rounding which is never
needed as the sign bit is already in the correct place. This helps in particular the
rounding to f16 case which needs a libcall.
Also remove the roundings for other FP VTs and simplify the CPSDR
patterns correspondingly.
fp-copysign-03.ll test updated, now also covering the other FP VT
combinations.
Commit: e98a61dc326c1b564461c0ae4fc693be5113d540
https://github.com/llvm/llvm-project/commit/e98a61dc326c1b564461c0ae4fc693be5113d540
Author: Tai Ly <tai.ly at arm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/verifier.mlir
Log Message:
-----------
[mlir][tosa] Add verifier check for Concat Op (#136047)
This adds verifier check for Concat Op
to make sure the sum of concatenated axis dimensions is equal to the
output's axis dimension
add tests in verifier.mlir
also moved existing concat verifier checks to verifier.mlir
Signed-off-by: Tai Ly <tai.ly at arm.com>
Commit: 66461dbb3b8d107fae2d50049205ddb8c192049c
https://github.com/llvm/llvm-project/commit/66461dbb3b8d107fae2d50049205ddb8c192049c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
Log Message:
-----------
SPIRV: Set NoPHIs property after rewriting them (#136327)
There should be no PHIs after selection, as OpPhi is used
instead. This hopefully avoids errors in #135277.
Commit: c6c08462ee3e8fc3d9cf9a69bb51175be49d5d3c
https://github.com/llvm/llvm-project/commit/c6c08462ee3e8fc3d9cf9a69bb51175be49d5d3c
Author: Jannick Kremer <jannick.kremer at mailbox.org>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/bindings/python/clang/cindex.py
A clang/bindings/python/tests/cindex/INPUTS/a.inc
A clang/bindings/python/tests/cindex/INPUTS/b.inc
A clang/bindings/python/tests/cindex/INPUTS/testfile.c
M clang/bindings/python/tests/cindex/test_file.py
M clang/docs/ReleaseNotes.rst
Log Message:
-----------
[libclang/python] Add equality comparison operators for File (#130383)
This covers the `File` interface changes added by #120590
---------
Co-authored-by: Mathias Stearn <redbeard0531 at gmail.com>
Co-authored-by: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Commit: 82c25d27501996683f30eb92dabf8a11925b7a62
https://github.com/llvm/llvm-project/commit/82c25d27501996683f30eb92dabf8a11925b7a62
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/test/AST/ByteCode/i686.cpp
Log Message:
-----------
[clang][bytecode] Disable i686 test
The array is too big and we don't have array fillers yet, see
e.g. https://lab.llvm.org/buildbot/#/builders/154/builds/15255
Commit: 88083a0c42e69e5967737e088ac6e5b1d12343f0
https://github.com/llvm/llvm-project/commit/88083a0c42e69e5967737e088ac6e5b1d12343f0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
Log Message:
-----------
[X86] SimplifyDemandedVectorEltsForTargetNode - handle 512-bit X86ISD::VPERMI with lower half demanded elts (#137139)
512-bit X86ISD::VPERMI nodes handle the lower/upper 256-bits separately - so if we don't demand the upper half elements, we can just use the 256-bit variant.
Commit: ebceb732d5afa7b97b73b34ce078a58c654ff0a0
https://github.com/llvm/llvm-project/commit/ebceb732d5afa7b97b73b34ce078a58c654ff0a0
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/Vector/canonicalize.mlir
Log Message:
-----------
[mlir][vector] Update the folder for vector.{insert|extract} (#136579)
This is a minor follow-up to #135498. It ensures that operations like
the following are not treated as out-of-bounds accesses and can be
folded correctly (*):
```mlir
%c_neg_1 = arith.constant -1 : index
%0 = vector.insert %value_to_store, %dest[%c_neg_1] : vector<5xf32> into vector<4x5xf32>
%1 = vector.extract %src[%c_neg_1, 0] : f32 from vector<4x5xf32>
```
In addition to adding tests for the case above, this PR also relocates
the tests from #135498 to be alongside existing tests for the
`vector.{insert|extract}` folder, and reformats them to follow:
* https://mlir.llvm.org/getting_started/TestingGuide/
For example:
* The "no_fold" prefix is now used to label negative tests.
* Redundant check lines have been removed (e.g., CHECK: vector.insert
is sufficient to verify that folding did not occur).
(*) As per https://mlir.llvm.org/docs/Dialects/Vector/#vectorinsert-vectorinsertop,
these are poison values.
Commit: 427b6448a3af009e57c0142d6d8af83318b45093
https://github.com/llvm/llvm-project/commit/427b6448a3af009e57c0142d6d8af83318b45093
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrGISel.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/lower-neon-vector-fcmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vector-fcmp.mir
M llvm/test/CodeGen/AArch64/arm64-zip.ll
M llvm/test/CodeGen/AArch64/select_cc.ll
Log Message:
-----------
Revert "[LLVM][ISel][AArch64 Remove AArch64ISD::FCM##z nodes. (#135817)"
This reverts commit 15d8b3cae9debc2bd7d27ca92ff599ba9fb30da5.
Commit: e37c236597137bae4f6728e163e9f81a1d9aff18
https://github.com/llvm/llvm-project/commit/e37c236597137bae4f6728e163e9f81a1d9aff18
Author: Christian Sigg <csigg at google.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] Remove unnecessary dependencies. (#136999)
Commit: d664c42baaed7f47a80f73a3974afd6e2593e41a
https://github.com/llvm/llvm-project/commit/d664c42baaed7f47a80f73a3974afd6e2593e41a
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M libclc/generic/include/clc/clc.h
R libclc/generic/include/clc/clcmacros.h
Log Message:
-----------
[libclc] Remove unnecessary clcmacros.h (#137149)
The macros defined by this file (not to be confused with clcmacro.h)
don't appear necessary for building libclc.
The language version macros should be handled by clang, and there are no
uses of NULL or kernel_exec in the source code.
Commit: 6900e9026516963ae625b28dded2cdf0bd16e590
https://github.com/llvm/llvm-project/commit/6900e9026516963ae625b28dded2cdf0bd16e590
Author: jeremyd2019 <github at jdrake.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/TargetParser/Triple.cpp
M llvm/unittests/TargetParser/TripleTest.cpp
Log Message:
-----------
[LLVM][TargetParser] Handle -msys targets the same as -cygwin. (#136817)
MSYS2 uses i686-pc-msys and x86_64-pc-msys as target, and is a fork of
Cygwin. There's an effort underway to try to switch as much as possible
to use -pc-cygwin targets, but the -msys target will be hanging around
for the forseeable future.
Commit: 15321d2c9e686b382262339fa17c5445b1b2609f
https://github.com/llvm/llvm-project/commit/15321d2c9e686b382262339fa17c5445b1b2609f
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaObjC.cpp
M clang/lib/Sema/SemaObjCProperty.cpp
M clang/lib/Sema/SemaOverload.cpp
A clang/test/Sema/implicit-void-ptr-cast.c
Log Message:
-----------
[C] Add (new) -Wimplicit-void-ptr-cast to -Wc++-compat (#136855)
This introduces a new diagnostic group (-Wimplicit-void-ptr-cast),
grouped under -Wc++-compat, which diagnoses implicit conversions from
void * to another pointer type in C. It's a common source of
incompatibility with C++ and is something GCC diagnoses (though GCC does
not have a specific warning group for this).
Fixes #17792
Commit: 2edade28245b1fc2b7cb0b39804894f8fdcfb7ff
https://github.com/llvm/llvm-project/commit/2edade28245b1fc2b7cb0b39804894f8fdcfb7ff
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M libclc/generic/include/clc/shared/vload.h
M libclc/generic/include/clc/shared/vstore.h
M libclc/generic/lib/shared/vload.cl
M libclc/generic/lib/shared/vload_half.inc
M libclc/generic/lib/shared/vstore.cl
M libclc/generic/lib/shared/vstore_half.inc
Log Message:
-----------
[libclc][NFC] Clang-format vload/vstore code
Commit: acc335bfa7b00ab19bf9832870aaf207f587b48b
https://github.com/llvm/llvm-project/commit/acc335bfa7b00ab19bf9832870aaf207f587b48b
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/test/CodeGen/X86/build-vector-128.ll
M llvm/test/CodeGen/X86/build-vector-256.ll
M llvm/test/CodeGen/X86/build-vector-512.ll
Log Message:
-----------
[X86] Add build vector test patterns with only 2 unique scalars
Based off test coverage for #135753 - these should be lowered to BLEND(BROADCAST(X),BROADCAST(Y))
Commit: 5d136f90a9806daf6d9ac905734a27974fc8f1b7
https://github.com/llvm/llvm-project/commit/5d136f90a9806daf6d9ac905734a27974fc8f1b7
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Manage instruction metadata in VPlan. (#135272)
Add a new helper to manage IR metadata that can be progated to generated
instructions for recipes.
This helps to remove a number of remaining uses of getUnderlyingInstr
during VPlan execution.
PR: https://github.com/llvm/llvm-project/pull/135272
Commit: 5bcde12fd14386324a7dd2af9af83f1949df760e
https://github.com/llvm/llvm-project/commit/5bcde12fd14386324a7dd2af9af83f1949df760e
Author: Iris Shi <0.0 at owo.li>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M bolt/lib/Core/MCPlusBuilder.cpp
M bolt/unittests/Core/MCPlusBuilder.cpp
M clang-tools-extra/clang-doc/Serialize.cpp
M clang-tools-extra/clangd/XRefs.cpp
M clang-tools-extra/clangd/unittests/CallHierarchyTests.cpp
M clang/bindings/python/clang/cindex.py
A clang/bindings/python/tests/cindex/INPUTS/a.inc
A clang/bindings/python/tests/cindex/INPUTS/b.inc
A clang/bindings/python/tests/cindex/INPUTS/testfile.c
M clang/bindings/python/tests/cindex/test_file.py
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/BuiltinsAArch64.def
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/arm_sme.td
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/Frontend/CompilerInstance.h
M clang/include/clang/Lex/DependencyDirectivesScanner.h
M clang/include/clang/Lex/Preprocessor.h
M clang/include/clang/Lex/PreprocessorOptions.h
M clang/include/clang/Parse/ParseHLSLRootSignature.h
M clang/include/clang/Sema/AnalysisBasedWarnings.h
M clang/include/clang/Sema/ScopeInfo.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/SemaCUDA.h
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningFilesystem.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/PrimType.h
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Basic/Targets/AVR.h
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CodeGen/CGClass.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGDebugInfo.h
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/Driver/SanitizerArgs.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Frontend/CompilerInstance.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Headers/arm_acle.h
M clang/lib/Lex/PPLexerChange.cpp
M clang/lib/Parse/ParseHLSLRootSignature.cpp
M clang/lib/Sema/AnalysisBasedWarnings.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaCUDA.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaObjC.cpp
M clang/lib/Sema/SemaObjCProperty.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/Serialization/ModuleManager.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefMemberChecker.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
M clang/test/AST/ByteCode/cxx20.cpp
A clang/test/AST/ByteCode/i686.cpp
M clang/test/AST/ByteCode/literals.cpp
M clang/test/Analysis/Checkers/WebKit/unchecked-members.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-members.cpp
A clang/test/Analysis/pragma-diag-control.cpp
M clang/test/CIR/CodeGen/struct.c
M clang/test/CIR/CodeGen/struct.cpp
M clang/test/CIR/CodeGen/typedef.c
M clang/test/CIR/CodeGen/union.c
M clang/test/CIR/CodeGenOpenACC/data.c
M clang/test/CIR/IR/struct.cir
M clang/test/CodeGen/AArch64/gcs.c
A clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
M clang/test/CodeGen/avr/avr-inline-asm-constraints.c
M clang/test/CodeGen/avr/avr-unsupported-inline-asm-constraints.c
A clang/test/CodeGenCUDA/lambda-constexpr-capture.cu
R clang/test/CodeGenCXX/debug-info-dtor-implicit-args.cpp
M clang/test/Driver/Xclangas.s
M clang/test/Driver/fsanitize.c
M clang/test/Driver/riscv-cpus.c
M clang/test/Driver/sanitizer-ld.c
M clang/test/Format/lit.local.cfg
M clang/test/Misc/target-invalid-cpu-note/riscv.c
A clang/test/Modules/Inputs/PR137102/module.modulemap
A clang/test/Modules/Inputs/PR137102/type_aware_destroying_new_delete.h
M clang/test/Modules/explicit-build.cpp
A clang/test/Modules/type-aware-destroying-new-and-delete-modules.cpp
A clang/test/PCH/Inputs/type_aware_destroying_new_delete.h
A clang/test/PCH/type-aware-destroying-new-and-delete-pch.cpp
M clang/test/Preprocessor/print-header-json.c
A clang/test/Sema/aarch64-sme2p2-instrinsics/acle_sme2p2_fp8_imm.cpp
A clang/test/Sema/implicit-void-ptr-cast.c
M clang/test/SemaCXX/constant-expression-cxx11.cpp
M clang/test/SemaOpenACC/data-construct-async-clause.c
M clang/tools/driver/driver.cpp
M clang/tools/libclang/CIndex.cpp
M clang/unittests/Lex/PPDependencyDirectivesTest.cpp
M clang/unittests/Parse/ParseHLSLRootSignatureTest.cpp
M clang/unittests/libclang/LibclangTest.cpp
A compiler-rt/test/tsan/stack_race3.cpp
A flang/docs/FortranStandardsSupport.md
M flang/docs/index.md
M flang/examples/FeatureList/FeatureList.cpp
M flang/include/flang/Lower/DirectivesCommon.h
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Semantics/symbol.h
M flang/include/flang/Support/Fortran.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Optimizer/CodeGen/LowerRepackArrays.cpp
M flang/lib/Optimizer/CodeGen/TargetRewrite.cpp
M flang/lib/Optimizer/Dialect/CUF/CUFToLLVMIRTranslation.cpp
M flang/lib/Optimizer/HLFIR/Transforms/InlineElementals.cpp
M flang/lib/Optimizer/HLFIR/Transforms/InlineHLFIRAssign.cpp
M flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
M flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/AssumedRankOpConversion.cpp
M flang/lib/Optimizer/Transforms/ConstantArgumentGlobalisation.cpp
M flang/lib/Optimizer/Transforms/SimplifyFIROperations.cpp
M flang/lib/Optimizer/Transforms/StackArrays.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/rewrite-directives.cpp
M flang/test/Fir/CUDA/cuda-target-rewrite.mlir
M flang/test/Semantics/OpenACC/acc-data.f90
M libc/src/stdio/printf_core/core_structs.h
M libclc/CMakeLists.txt
M libclc/cmake/modules/AddLibclc.cmake
M libclc/generic/include/clc/clc.h
R libclc/generic/include/clc/clcmacros.h
M libclc/generic/include/clc/image/image.h
M libclc/generic/include/clc/shared/vload.h
M libclc/generic/include/clc/shared/vstore.h
M libclc/generic/lib/shared/vload.cl
M libclc/generic/lib/shared/vload_half.inc
M libclc/generic/lib/shared/vstore.cl
M libclc/generic/lib/shared/vstore_half.inc
M libcxx/include/__ranges/to.h
M libcxx/test/libcxx/ranges/range.utility/range.utility.conv/to.static_assert.verify.cpp
M libcxxabi/test/test_demangle.pass.cpp
M lldb/include/lldb/API/SBExecutionContext.h
M lldb/include/lldb/API/SBInstructionList.h
M lldb/include/lldb/Interpreter/CommandObject.h
M lldb/include/lldb/Interpreter/OptionValueEnumeration.h
M lldb/include/lldb/Utility/CompletionRequest.h
M lldb/packages/Python/lldbsuite/test/lldbtest.py
M lldb/source/API/SBCommandInterpreter.cpp
M lldb/source/API/SBInstructionList.cpp
M lldb/source/Commands/CommandCompletions.cpp
M lldb/source/Commands/CommandObjectProcess.cpp
M lldb/source/Commands/Options.td
M lldb/source/Interpreter/OptionValueEnumeration.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangModulesDeclVendor.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxInitializerList.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxSpan.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxVariant.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxVector.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/Process/Utility/CMakeLists.txt
A lldb/source/Plugins/Process/Utility/RegisterContextDarwin_riscv32.cpp
A lldb/source/Plugins/Process/Utility/RegisterContextDarwin_riscv32.h
M lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
M lldb/source/Plugins/SymbolFile/DWARF/CMakeLists.txt
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.h
A lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndexSet.cpp
A lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndexSet.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
M lldb/source/Utility/ArchSpec.cpp
M lldb/test/API/commands/expression/completion/TestExprCompletion.py
A lldb/test/API/commands/process/reverse-continue/Makefile
A lldb/test/API/commands/process/reverse-continue/TestReverseContinue.py
A lldb/test/API/commands/process/reverse-continue/TestReverseContinueNotSupported.py
A lldb/test/API/commands/process/reverse-continue/main.c
M lldb/test/API/commands/settings/TestSettings.py
A lldb/test/API/macosx/riscv32-corefile/Makefile
A lldb/test/API/macosx/riscv32-corefile/TestRV32MachOCorefile.py
A lldb/test/API/macosx/riscv32-corefile/create-empty-riscv-corefile.cpp
R lldb/test/Shell/SymbolFile/DWARF/range-lower-then-low-pc.s
M lldb/test/Shell/SymbolFile/DWARF/x86/discontinuous-inline-function.s
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/Handler/CancelRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/DisconnectRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/NextRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
M lldb/tools/lldb-dap/Handler/SourceRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/StepInRequestHandler.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolBase.h
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
M lldb/tools/lldb-dap/Transport.cpp
M lldb/unittests/SymbolFile/DWARF/DWARFIndexCachingTest.cpp
M lldb/unittests/Utility/ArchSpecTest.cpp
M llvm/docs/ReleaseNotes.md
M llvm/docs/SPIRVUsage.rst
M llvm/include/llvm/Analysis/DXILResource.h
M llvm/include/llvm/BinaryFormat/MachO.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/MachinePipeliner.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h
M llvm/include/llvm/Frontend/OpenACC/ACC.td
M llvm/include/llvm/Frontend/OpenMP/OMPDeviceConstants.h
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/include/llvm/IR/RuntimeLibcalls.def
M llvm/include/llvm/IR/Value.h
A llvm/include/llvm/ProfileData/IndexedMemProfData.h
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/PrologEpilogInserter.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/Value.cpp
M llvm/lib/ProfileData/CMakeLists.txt
A llvm/lib/ProfileData/IndexedMemProfData.cpp
M llvm/lib/ProfileData/InstrProf.cpp
M llvm/lib/ProfileData/InstrProfReader.cpp
M llvm/lib/ProfileData/InstrProfWriter.cpp
M llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/BPF/BPFISelLowering.h
M llvm/lib/Target/DirectX/CMakeLists.txt
A llvm/lib/Target/DirectX/DXILForwardHandleAccesses.cpp
A llvm/lib/Target/DirectX/DXILForwardHandleAccesses.h
M llvm/lib/Target/DirectX/DirectX.h
M llvm/lib/Target/DirectX/DirectXPassRegistry.def
M llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.h
M llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.h
M llvm/lib/Target/SystemZ/SystemZInstrFP.td
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/TargetParser/Triple.cpp
M llvm/lib/Transforms/Coroutines/CoroElide.cpp
M llvm/lib/Transforms/IPO/FunctionAttrs.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
M llvm/lib/Transforms/Instrumentation/SanitizerBinaryMetadata.cpp
M llvm/lib/Transforms/Instrumentation/ThreadSanitizer.cpp
M llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
M llvm/lib/Transforms/Scalar/NewGVN.cpp
M llvm/lib/Transforms/Scalar/Reassociate.cpp
M llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/runtimes/CMakeLists.txt
A llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector.mir
M llvm/test/CodeGen/AArch64/fsh.ll
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
A llvm/test/CodeGen/AArch64/sme2-intrinsics-mop4-fp8.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/sve-varargs-caller-broken.ll
M llvm/test/CodeGen/AArch64/sve-varargs.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
M llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AMDGPU/fpext-free.ll
M llvm/test/CodeGen/AMDGPU/fpow.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/function-args.ll
M llvm/test/CodeGen/AMDGPU/function-returns.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.wave32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.AFLCustomIRMutator.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/lrint.ll
M llvm/test/CodeGen/AMDGPU/lround.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/strict_fpext.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
M llvm/test/CodeGen/AMDGPU/vector_rebroadcast.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vopc_dpp.mir
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/ARM/popcnt.ll
M llvm/test/CodeGen/AVR/inline-asm/inline-asm-invalid.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/alloca.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/ambiguous.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/buffer-O0.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/cbuffer-access.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/undominated.ll
M llvm/test/CodeGen/DirectX/llc-pipeline.ll
A llvm/test/CodeGen/Hexagon/swp-alias-cross-iteration.mir
A llvm/test/CodeGen/Hexagon/swp-no-alias.mir
M llvm/test/CodeGen/NVPTX/LoadStoreVectorizer.ll
M llvm/test/CodeGen/NVPTX/and-or-setcc.ll
M llvm/test/CodeGen/NVPTX/atomics.ll
M llvm/test/CodeGen/NVPTX/bf16-instructions.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions-approx.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/convert-fp-i8.ll
M llvm/test/CodeGen/NVPTX/convert-sm100.ll
M llvm/test/CodeGen/NVPTX/convert-sm100a.ll
M llvm/test/CodeGen/NVPTX/convert-sm80.ll
M llvm/test/CodeGen/NVPTX/convert-sm90.ll
M llvm/test/CodeGen/NVPTX/copysign.ll
M llvm/test/CodeGen/NVPTX/distributed-shared-cluster.ll
M llvm/test/CodeGen/NVPTX/div.ll
M llvm/test/CodeGen/NVPTX/f16-abs.ll
M llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/f32-ex2.ll
M llvm/test/CodeGen/NVPTX/f32-lg2.ll
M llvm/test/CodeGen/NVPTX/fabs-intrinsics.ll
M llvm/test/CodeGen/NVPTX/fexp2.ll
M llvm/test/CodeGen/NVPTX/flog2.ll
M llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
M llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll
M llvm/test/CodeGen/NVPTX/fma-relu-instruction-flag.ll
M llvm/test/CodeGen/NVPTX/fp-contract.ll
M llvm/test/CodeGen/NVPTX/frem.ll
M llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
M llvm/test/CodeGen/NVPTX/intrinsics.ll
M llvm/test/CodeGen/NVPTX/ldg-invariant.ll
M llvm/test/CodeGen/NVPTX/ldu-ldg.ll
M llvm/test/CodeGen/NVPTX/load-store-scalars.ll
M llvm/test/CodeGen/NVPTX/load-store-vectors.ll
M llvm/test/CodeGen/NVPTX/math-intrins.ll
M llvm/test/CodeGen/NVPTX/misched_func_call.ll
M llvm/test/CodeGen/NVPTX/param-add.ll
M llvm/test/CodeGen/NVPTX/rcp-opt.ll
M llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
M llvm/test/CodeGen/NVPTX/redux-sync-f32.ll
M llvm/test/CodeGen/NVPTX/reg-types.ll
M llvm/test/CodeGen/NVPTX/st-param-imm.ll
M llvm/test/CodeGen/NVPTX/surf-read-cuda.ll
M llvm/test/CodeGen/NVPTX/tex-read-cuda.ll
M llvm/test/CodeGen/NVPTX/variadics-backend.ll
M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
M llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
M llvm/test/CodeGen/RISCV/xqccmp-additional-stack.ll
M llvm/test/CodeGen/RISCV/xqccmp-callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
M llvm/test/CodeGen/RISCV/xqccmp-with-float.ll
A llvm/test/CodeGen/RISCV/zalasr-offset-folding.ll
M llvm/test/CodeGen/RISCV/zcmp-additional-stack.ll
M llvm/test/CodeGen/RISCV/zcmp-with-float.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroup_matrix_multiply_accumulate/subgroup_matrix_multiply_accumulate_generic.ll
M llvm/test/CodeGen/SystemZ/fp-abs-01.ll
M llvm/test/CodeGen/SystemZ/fp-abs-02.ll
M llvm/test/CodeGen/SystemZ/fp-abs-03.ll
M llvm/test/CodeGen/SystemZ/fp-abs-04.ll
M llvm/test/CodeGen/SystemZ/fp-copysign-01.ll
M llvm/test/CodeGen/SystemZ/fp-copysign-02.ll
M llvm/test/CodeGen/SystemZ/fp-copysign-03.ll
M llvm/test/CodeGen/SystemZ/fp-mul-08.ll
M llvm/test/CodeGen/SystemZ/fp-mul-10.ll
M llvm/test/CodeGen/SystemZ/fp-neg-01.ll
M llvm/test/CodeGen/SystemZ/fp-neg-02.ll
M llvm/test/CodeGen/Thumb2/mve-ctpop.ll
M llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
M llvm/test/CodeGen/X86/build-vector-128.ll
M llvm/test/CodeGen/X86/build-vector-256.ll
M llvm/test/CodeGen/X86/build-vector-512.ll
M llvm/test/CodeGen/X86/extractelement-load.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
M llvm/test/DebugInfo/NVPTX/debug-info.ll
M llvm/test/Instrumentation/ThreadSanitizer/capture.ll
M llvm/test/Transforms/FunctionAttrs/initializes.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-binop.ll
A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-shift.ll
M llvm/test/Transforms/InstCombine/and-fcmp.ll
M llvm/test/Transforms/InstCombine/clamp-to-minmax.ll
M llvm/test/Transforms/InstCombine/icmp.ll
A llvm/test/Transforms/InstCombine/max-min-canonicalize.ll
M llvm/test/Transforms/InstCombine/max_known_bits.ll
M llvm/test/Transforms/InstCombine/minmax-fold.ll
M llvm/test/Transforms/InstCombine/minmax-intrinsics.ll
M llvm/test/Transforms/InstCombine/sadd_sat.ll
M llvm/test/Transforms/InstCombine/select-min-max.ll
M llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-no-dotprod.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
M llvm/test/Transforms/LoopVectorize/X86/pr51366-sunk-instruction-used-outside-of-loop.ll
M llvm/test/Transforms/LoopVectorize/X86/small-size.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll
A llvm/test/Transforms/PGOProfile/memprof-dump-matched-alloc-site.ll
M llvm/test/Transforms/PGOProfile/memprof-dump-matched-call-sites.ll
M llvm/test/Transforms/PGOProfile/memprof.ll
A llvm/test/Transforms/Reassociate/canonicalize-made-change.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/preserve-inbounds.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep.ll
M llvm/test/tools/dsymutil/ARM/stmt-seq-macho.test
A llvm/test/tools/llvm-extract/extract-unnamed-bb.ll
M llvm/tools/llvm-extract/llvm-extract.cpp
M llvm/unittests/TargetParser/TripleTest.cpp
M llvm/utils/TableGen/DecoderEmitter.cpp
M llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Plugins/SymbolFile/DWARF/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ProfileData/BUILD.gn
M llvm/utils/vim/syntax/llvm.vim
M mlir/include/mlir/Dialect/GPU/Transforms/Passes.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/MemRef/Transforms/Passes.h
M mlir/include/mlir/Dialect/MemRef/Transforms/Passes.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaUtilOps.td
M mlir/include/mlir/Dialect/X86Vector/X86Vector.td
M mlir/include/mlir/Dialect/X86Vector/X86VectorDialect.h
M mlir/include/mlir/Dialect/X86Vector/X86VectorInterfaces.td
M mlir/include/mlir/Transforms/GreedyPatternRewriteDriver.h
M mlir/include/mlir/Transforms/Passes.td
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Conversion/TosaToMLProgram/TosaToMLProgram.cpp
M mlir/lib/Dialect/Affine/TransformOps/AffineTransformOps.cpp
M mlir/lib/Dialect/Affine/Transforms/AffineDataCopyGeneration.cpp
M mlir/lib/Dialect/Affine/Transforms/SimplifyAffineStructures.cpp
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/lib/Dialect/Affine/Utils/Utils.cpp
M mlir/lib/Dialect/Arith/Transforms/IntRangeOptimizations.cpp
M mlir/lib/Dialect/Bufferization/Pipelines/BufferizationPipelines.cpp
M mlir/lib/Dialect/Bufferization/Transforms/BufferDeallocationSimplification.cpp
M mlir/lib/Dialect/GPU/CMakeLists.txt
M mlir/lib/Dialect/GPU/Transforms/SubgroupReduceLowering.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandRealloc.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
M mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/NormalizeMemRefs.cpp
M mlir/lib/Dialect/MemRef/Transforms/ResolveShapedTypeResultDims.cpp
M mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp
M mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/lib/Dialect/Transform/IR/TransformOps.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/X86Vector/IR/CMakeLists.txt
M mlir/lib/Dialect/X86Vector/IR/X86VectorDialect.cpp
M mlir/lib/Dialect/X86Vector/Transforms/LegalizeForLLVMExport.cpp
M mlir/lib/Reducer/ReductionTreePass.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Transforms/Canonicalizer.cpp
M mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-pipeline.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
M mlir/test/Conversion/TosaToMLProgram/tosa-to-mlprogram.mlir
M mlir/test/Dialect/GPU/subgroup-reduce-lowering.mlir
M mlir/test/Dialect/LLVMIR/canonicalize.mlir
M mlir/test/Dialect/LLVMIR/invalid.mlir
M mlir/test/Dialect/LLVMIR/module-roundtrip.mlir
M mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/level_check.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/profile_pro_fp_unsupported.mlir
M mlir/test/Dialect/Tosa/profile_pro_int_unsupported.mlir
M mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
M mlir/test/Dialect/Tosa/variables.mlir
M mlir/test/Dialect/Tosa/verifier.mlir
M mlir/test/Dialect/Vector/canonicalize.mlir
M mlir/test/Dialect/Vector/invalid.mlir
M mlir/test/Dialect/X86Vector/legalize-for-llvm.mlir
M mlir/test/Dialect/X86Vector/roundtrip.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/matmul.mlir
M mlir/test/Target/LLVMIR/Import/module-flags.ll
M mlir/test/Target/LLVMIR/llvmir.mlir
M mlir/test/Target/LLVMIR/x86vector.mlir
M mlir/test/lib/Dialect/Affine/TestAffineDataCopy.cpp
M mlir/test/lib/Dialect/GPU/TestGpuRewrite.cpp
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
M mlir/test/python/pass_manager.py
M offload/DeviceRTL/CMakeLists.txt
M offload/DeviceRTL/src/Kernel.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/test/offloading/ompx_bare.c
M offload/test/offloading/ompx_bare_multi_dim.cpp
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/plugin_config.bzl
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
Merge branch 'main' into users/el-ev/cleanup-c-fn-noproto
Compare: https://github.com/llvm/llvm-project/compare/02b5829537c3...5bcde12fd143
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