[all-commits] [llvm/llvm-project] a2f00e: [RISCV] Add fixed-length patterns for disjoint or ...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a2f00e1f8f124667339b94ffa144c0ff0d6ae3b3
      https://github.com/llvm/llvm-project/commit/a2f00e1f8f124667339b94ffa144c0ff0d6ae3b3
  Author: Luke Lau <luke at igalia.com>
  Date:   2025-04-24 (Thu, 24 Apr 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll

  Log Message:
  -----------
  [RISCV] Add fixed-length patterns for disjoint or patterns for vwadd[u].v{v,x} (#136824)

This is the fixed-length equivalent of #136716.

The pattern we need to match is ({s,z}ext_vl (or_vl disjoint a, b)).
This only allows or_vls with an undef passthru, which allows us to
ignore its mask and vl and just take it from the {s,z}ext_vl.

A riscv_or_vl_is_add_oneuse PatFrag is added to mirror or_is_add in
RISCVInstrInfo.td.



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