[all-commits] [llvm/llvm-project] 4f7165: [clang-format] Fix a bug in parsing C-style cast o...
Peter Collingbourne via All-commits
all-commits at lists.llvm.org
Wed Apr 23 16:07:56 PDT 2025
Branch: refs/heads/users/pcc/spr/liverangeshrink-early-exit-when-encountering-a-code-motion-barrier
Home: https://github.com/llvm/llvm-project
Commit: 4f71655b64a815143d2aedb22b8f423f7ce99e29
https://github.com/llvm/llvm-project/commit/4f71655b64a815143d2aedb22b8f423f7ce99e29
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Fix a bug in parsing C-style cast of lambdas (#136099)
Fix #135959
Commit: 9efabbbbe58bd8bc2141ba1c914f79376e09cbcf
https://github.com/llvm/llvm-project/commit/9efabbbbe58bd8bc2141ba1c914f79376e09cbcf
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/lib/Format/FormatTokenLexer.cpp
M clang/lib/Format/FormatTokenLexer.h
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Fix a bug in lexing C++ UDL ending in $ (#136476)
Fix #61612
Commit: 037657de7e5ccd4a37054829874a209b82fb8be7
https://github.com/llvm/llvm-project/commit/037657de7e5ccd4a37054829874a209b82fb8be7
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Correctly annotate kw_operator in using decls (#136545)
Fix #136541
Commit: afc030dd30e377ca7bf225a97179fa1b64eedd28
https://github.com/llvm/llvm-project/commit/afc030dd30e377ca7bf225a97179fa1b64eedd28
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/unittests/Format/FormatTestJS.cpp
Log Message:
-----------
[clang-format] Don't test stability if JS format test fails (#136662)
Commit: 68d89e931619ce5c9bc6fffcbe2d5b5268047f3c
https://github.com/llvm/llvm-project/commit/68d89e931619ce5c9bc6fffcbe2d5b5268047f3c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/TargetParser/RISCVISAInfo.cpp
Log Message:
-----------
[RISCV] Remove stale comment. NFC
Commit: 34a4c58018730736b940c4db4d694feed3266f52
https://github.com/llvm/llvm-project/commit/34a4c58018730736b940c4db4d694feed3266f52
Author: Michele Scandale <michele.scandale at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/include/clang/AST/Type.h
M clang/lib/AST/Type.cpp
M clang/lib/CodeGen/CGExpr.cpp
Log Message:
-----------
[clang] Rework `hasBooleanRepresentation`. (#136038)
This is a follow-up of 13aac46332f607a38067b5ddd466071683b8c255.
This commit adjusts the implementation of `hasBooleanRepresentation` to
be somewhat aligned to `hasIntegerRepresentation`.
In particular vector of booleans should be handled in
`hasBooleanRepresentation`, while `_Atomic(bool)` should not.
Commit: 141c14c9522ba2bf7472d660d64928b9982b5f6e
https://github.com/llvm/llvm-project/commit/141c14c9522ba2bf7472d660d64928b9982b5f6e
Author: tangaac <tangyan01 at loongson.cn>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
A llvm/test/CodeGen/LoongArch/lasx/widen-shuffle-mask.ll
A llvm/test/CodeGen/LoongArch/lsx/widen-shuffle-mask.ll
Log Message:
-----------
[LoongArch] Pre-commit for widen shuffle mask (#136544)
Commit: 7547ad3a7bc1e249c240512438eb39581f58c8ef
https://github.com/llvm/llvm-project/commit/7547ad3a7bc1e249c240512438eb39581f58c8ef
Author: lntue <lntue at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M libc/src/math/generic/expm1f.cpp
Log Message:
-----------
[libc][math] Skip checking for exceptional values in expm1f when LIBC_MATH_SKIP_ACCURATE_PASS is set. (#130968)
Commit: 439f16a7e12f1aece321266e4fce760841bfcdf1
https://github.com/llvm/llvm-project/commit/439f16a7e12f1aece321266e4fce760841bfcdf1
Author: Christian Sigg <csigg at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] Port e112dccc8ba49425c575a6b15325f2cbeef5c606.
Commit: 3ccfbc8a002e1e0f64b5408d26bc42282afc194b
https://github.com/llvm/llvm-project/commit/3ccfbc8a002e1e0f64b5408d26bc42282afc194b
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M lldb/source/Core/Debugger.cpp
M lldb/test/API/functionalities/statusline/TestStatusline.py
Log Message:
-----------
[lldb] Make sure changing the separator takes immediate effect (#136779)
The setter is only used when changing the setting programmatically. When
using the settings command, we need to monitor SetPropertyValue.
Commit: 7b6801574d978ef418dd76257478cbbe5866b09f
https://github.com/llvm/llvm-project/commit/7b6801574d978ef418dd76257478cbbe5866b09f
Author: Henrich Lauko <xlauko at mail.muni.cz>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
Log Message:
-----------
[CIR] Infer MLIRContext in attr builders when possible (#136741)
Mirrors incubator changes from https://github.com/llvm/clangir/pull/1582
Commit: 5080a0251fe3352d26560075a9b3b8c9acb13d23
https://github.com/llvm/llvm-project/commit/5080a0251fe3352d26560075a9b3b8c9acb13d23
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
A llvm/test/CodeGen/RISCV/pr101786.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/X86/ispow2.ll
A llvm/test/CodeGen/X86/pr94829.ll
M llvm/test/CodeGen/X86/vector-popcnt-128.ll
M llvm/test/CodeGen/X86/vector-popcnt-256-ult-ugt.ll
M llvm/test/CodeGen/X86/vector-popcnt-256.ll
M llvm/test/CodeGen/X86/vector-popcnt-512-ult-ugt.ll
M llvm/test/CodeGen/X86/vector-popcnt-512.ll
A llvm/test/Transforms/CodeGenPrepare/unfold-pow2-test-vec.ll
A llvm/test/Transforms/CodeGenPrepare/unfold-pow2-test.ll
Log Message:
-----------
[CodeGenPrepare] Unfold slow ctpop when used in power-of-two test (#102731)
DAG combiner already does this transformation, but in some cases it does
not have a chance because either CodeGenPrepare or SelectionDAGBuilder
move icmp to a different basic block.
https://alive2.llvm.org/ce/z/ARzh99
Fixes #94829
Pull Request: https://github.com/llvm/llvm-project/pull/102731
Commit: 1a78ef9a9eddd73de7932f5c33a7a7ad7e8b1806
https://github.com/llvm/llvm-project/commit/1a78ef9a9eddd73de7932f5c33a7a7ad7e8b1806
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpState.cpp
M clang/lib/AST/ByteCode/InterpState.h
M clang/test/AST/ByteCode/c.c
M clang/test/AST/ByteCode/cxx11.cpp
M clang/test/AST/ByteCode/cxx23.cpp
M clang/test/AST/ByteCode/cxx26.cpp
Log Message:
-----------
[clang][bytecode] Allow casts from void* only in std::allocator calls (#136714)
Otherwise, add the missing diagnostic.
Commit: 832ca744f2f25a7a5334f2f04380c84e41f71678
https://github.com/llvm/llvm-project/commit/832ca744f2f25a7a5334f2f04380c84e41f71678
Author: Jim Lin <jim at andestech.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/test/Driver/riscv-cpus.c
M clang/test/Misc/target-invalid-cpu-note/riscv.c
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/RISCVProcessors.td
Log Message:
-----------
[RISCV] Add Andes N45/NX45 processor definition (#136670)
Andes N45/NX45 are 32/64bit in-order dual-issue 8-stage pipeline CPU
architecture implementing the RV[32|64]IMAFDC_Zba_Zbb_Zbs ISA
extensions. They are developed by Andes Technology
https://www.andestech.com, a RISC-V IP provider.
The overviews for N45/NX45:
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-n45/
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-nx45/
Scheduling model will be implemented in a later PR.
Commit: 30c47147262523663892836fee42e02f8f9366f5
https://github.com/llvm/llvm-project/commit/30c47147262523663892836fee42e02f8f9366f5
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/utils/generate-test-checks.py
Log Message:
-----------
[mlir][utils] Update generate-test-checks.py (#136757)
At the moment, the `CHECK-SAME` lines generated by
"generate-test-checks.py" (i.e. check-lines that correspond to the
preceeding `CHECK-LABEL` line) are indented to match the label length.
For example,
```mlir
func.func @batch_reduce_matmul_bcast_k_to_fill_missing_dims_A(%arg0: memref<5xf32>, %arg1: memref<2x5x7xf32>, %arg2: memref<3x7xf32>) {
linalg.batch_reduce_matmul indexing_maps = (...)
}
```
will lead to the following:
```mlir
// CHECK-LABEL: func.func @batch_reduce_matmul_bcast_k_to_fill_missing_dims_A(
// CHECK-SAME: %[[VAL_0:[0-9]+|[a-zA-Z$._-][a-zA-Z0-9$._-]*]]: memref<5xf32>,
// CHECK-SAME: %[[VAL_1:[0-9]+|[a-zA-Z$._-][a-zA-Z0-9$._-]*]]: memref<2x5x7xf32>,
// CHECK-SAME: %[[VAL_2:[0-9]+|[a-zA-Z$._-][a-zA-Z0-9$._-]*]]: memref<3x7xf32>) {
// CHECK: linalg.batch_reduce_matmul indexing_maps = (...)
```
This indentation is unnecasarilly deep. With this change, for labales
that are longer than 20 chars, the indentation is trimmed to 4 spaces:
```mlir
// CHECK-LABEL: func.func @batch_reduce_matmul_bcast_k_to_fill_missing_dims_A(
// CHECK-SAME: %[[VAL_0:[0-9]+|[a-zA-Z$._-][a-zA-Z0-9$._-]*]]: memref<5xf32>,
// CHECK-SAME: %[[VAL_1:[0-9]+|[a-zA-Z$._-][a-zA-Z0-9$._-]*]]: memref<2x5x7xf32>,
// CHECK-SAME: %[[VAL_2:[0-9]+|[a-zA-Z$._-][a-zA-Z0-9$._-]*]]: memref<3x7xf32>) {
// CHECK: linalg.batch_reduce_matmul indexing_maps = (...)
```
Commit: 665914fea1433409015a87fef2837218bcd21460
https://github.com/llvm/llvm-project/commit/665914fea1433409015a87fef2837218bcd21460
Author: Mythreya <git at mythreya.dev>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang-tools-extra/clangd/InlayHints.cpp
M clang-tools-extra/clangd/InlayHints.h
M clang-tools-extra/clangd/unittests/InlayHintTests.cpp
Log Message:
-----------
[clangd] Improve `BlockEnd` inlayhint presentation (#136106)
* Only show for blocks 10 lines or taller (including braces)
* Add parens for function call: "// if foo" -> "// if foo()" or "// if foo(...)"
* Print literal nullptr
* Escaping for abbreviated strings
Fixes https://github.com/clangd/clangd/issues/1807.
Based on the original PR at https://github.com/llvm/llvm-project/pull/72345.
Co-authored-by: daiyousei-qz <qyzheng2 at outlook.com>
Commit: 98b6f8dc699d789d834e5b6d810ed217f560aad0
https://github.com/llvm/llvm-project/commit/98b6f8dc699d789d834e5b6d810ed217f560aad0
Author: David Green <david.green at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/Support/InstructionCost.h
M llvm/include/llvm/Transforms/Utils/UnrollLoop.h
M llvm/lib/Analysis/CostModel.cpp
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Transforms/IPO/FunctionSpecialization.cpp
M llvm/lib/Transforms/IPO/PartialInlining.cpp
M llvm/lib/Transforms/Scalar/ConstantHoisting.cpp
M llvm/lib/Transforms/Scalar/LoopDataPrefetch.cpp
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
M llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/unittests/Support/InstructionCostTest.cpp
Log Message:
-----------
[CostModel] Remove optional from InstructionCost::getValue() (#135596)
InstructionCost is already an optional value, containing an Invalid
state that can be checked with isValid(). There is little point in
returning another optional from getValue(). Most uses do not make use of
it being a std::optional, dereferencing the value directly (either
isValid has been checked previously or the Cost is assumed to be valid).
The one case that does in AMDGPU used value_or which has been replaced
by a isValid() check.
Commit: ca3a5d37ef64668234cbce7236dd640a98e2d687
https://github.com/llvm/llvm-project/commit/ca3a5d37ef64668234cbce7236dd640a98e2d687
Author: jeremyd2019 <github at jdrake.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/cxa-atexit.cpp
Log Message:
-----------
[Clang] [Driver] use __cxa_atexit by default on Cygwin. (#135701)
GCC on Cygwin and MSYS2 are built with --enable-__cxa_atexit.
Adjust test to expect this change.
Commit: 1a99f7981f16461dc8e9add411abd1218435320e
https://github.com/llvm/llvm-project/commit/1a99f7981f16461dc8e9add411abd1218435320e
Author: Luke Lau <luke at igalia.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
Log Message:
-----------
[RISCV] Add tests for fixed-length vwadd[u].{w,v}v with disjoint or. NFC
Commit: da8f2d52423bb82b5d4e75cff3018704effe044f
https://github.com/llvm/llvm-project/commit/da8f2d52423bb82b5d4e75cff3018704effe044f
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
Revert "[clang-format] Allow breaking before kw___attribute (#128623)"
This reverts commit 8fc8a84e23471fe56214e68706addc712b5a2949, which caused a
regression.
Fixes #136675.
Commit: dfc60b2ceb50e75dc07bdda18ae74695f18b370c
https://github.com/llvm/llvm-project/commit/dfc60b2ceb50e75dc07bdda18ae74695f18b370c
Author: Christian Sigg <csigg at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] Also add SideEffectInterfaces dep to PtrDialect.
Fix for port of e112dcc.
Commit: 82049310385d5222527cf7d12984bd8d4f955dd1
https://github.com/llvm/llvm-project/commit/82049310385d5222527cf7d12984bd8d4f955dd1
Author: Luke Lau <luke at igalia.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
Log Message:
-----------
[RISCV] Add disjoint or patterns for vwadd[u].v{v,x} (#136716)
DAGCombiner::hoistLogicOpWithSameOpcodeHands will hoist
(or disjoint (ext a), (ext b)) -> (ext (or disjoint a, b))
So this adds patterns to match vwadd[u].v{v,x} in this case.
We have to teach the combine to preserve the disjoint flag.
Commit: dd3de590ebd63566a1a54eb0e2140c433a9add84
https://github.com/llvm/llvm-project/commit/dd3de590ebd63566a1a54eb0e2140c433a9add84
Author: David Green <david.green at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Analysis/InlineSizeEstimatorAnalysis.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
Log Message:
-----------
[CostModel] Fix InlineSizeEstimatorAnalysis after #135596
Fix a reference to getValue() being optional in InlineSizeEstimatorAnalysis, a
file that is not included in the default build. A "warning: enumerated and
non-enumerated type in conditional expression" warning is fixed in AMDGPU too.
Commit: ae47f2533709058d3442a34af783d8cd721b4177
https://github.com/llvm/llvm-project/commit/ae47f2533709058d3442a34af783d8cd721b4177
Author: Arseniy Zaostrovnykh <necto.ne at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/docs/StandardCPlusPlusModules.rst
Log Message:
-----------
[docs] Fix the use of word "dependent" and other typos in the C++ Modules Doc (#136719)
"Dependant BMI" / "Dependent BMI" was used incorrectly in the
documentation:
"Dependent BMI" refers to a BMI that depends on the current TU, but it
was used for the BMI that current TU depends on.
I replaced all the mentions with "BMI dependency".
Commit: d0cd6f3b9339326af01549ee09f17a6e9b54f505
https://github.com/llvm/llvm-project/commit/d0cd6f3b9339326af01549ee09f17a6e9b54f505
Author: David Green <david.green at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/arm64-tbl.ll
Log Message:
-----------
[AArch64] Fix tryToConvertShuffleOfTbl2ToTbl4 with non-buildvector input operands. (#135961)
It looks like this code is only considering buildvector inputs,
expecting the inputs to have at least 16 operands. This adds a check to
make sure that is true.
Fixes #135950
Commit: 91edbe223177504cf878340f37a36dfcee349cab
https://github.com/llvm/llvm-project/commit/91edbe223177504cf878340f37a36dfcee349cab
Author: wanglei <wanglei at loongson.cn>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
Log Message:
-----------
[lldb][LoongArch] Fix expression function call failure
After upgrading the default code model from small to medium on
LoongArch, function calls using expression may fail. This is because the
function call instruction has changed from `bl` to `pcalau18i + jirl`,
but `RuntimeDyld` does not handle out-of-range jumps for this
instruction sequence.
This patch fixes: #136561
Reviewed By: SixWeining
Pull Request: https://github.com/llvm/llvm-project/pull/136563
Commit: 8a57df6a5210d0c54ed482eb7230b7689a1f9cb9
https://github.com/llvm/llvm-project/commit/8a57df6a5210d0c54ed482eb7230b7689a1f9cb9
Author: Allin Lee <60502081+AllinLeeYL at users.noreply.github.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/IR/Value.h
M llvm/lib/IR/Value.cpp
A llvm/test/tools/llvm-extract/extract-unnamed-bb.ll
M llvm/tools/llvm-extract/llvm-extract.cpp
Log Message:
-----------
[llvm-extract] support unnamed bbs. (#135140)
Dear developer:
I have recently working with LLVM IR and I want to isolate basic blocks
using the command "llvm-extract". However, I found that the command
option "llvm-extract --bb func_name:bb_name" will only function when
dumping source code into IRs with options "-fno-discard-value-names".
That is to say, the "llvm-extract" command cannot support unnamed basic
blocks, which is a default output of the compiler. So, I made these
changes and hope they will make LLVM better.
Best regards,
Co-authored-by: Yilin Li <allinleeme at gmail.com>
Commit: 6db447f824d46956172b104f08105b25f9428f55
https://github.com/llvm/llvm-project/commit/6db447f824d46956172b104f08105b25f9428f55
Author: Iris Shi <0.0 at owo.li>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/test/Transforms/InstCombine/clamp-to-minmax.ll
A llvm/test/Transforms/InstCombine/max-min-canonicalize.ll
M llvm/test/Transforms/InstCombine/max_known_bits.ll
M llvm/test/Transforms/InstCombine/minmax-fold.ll
M llvm/test/Transforms/InstCombine/minmax-intrinsics.ll
M llvm/test/Transforms/InstCombine/sadd_sat.ll
M llvm/test/Transforms/InstCombine/select-min-max.ll
Log Message:
-----------
[InstCombine] Canonicalize `max(min(X, MinC), MaxC) -> min(max(X, MaxC), MinC)` (#136665)
Closes #121870.
https://alive2.llvm.org/ce/z/WjmAjz
https://alive2.llvm.org/ce/z/4KCjgL
Commit: 4a58071d87265dfccba72134b25cf4d1595d98c5
https://github.com/llvm/llvm-project/commit/4a58071d87265dfccba72134b25cf4d1595d98c5
Author: Diana Picus <Diana-Magda.Picus at amd.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineFrameInfo.h
M llvm/include/llvm/CodeGen/TargetFrameLowering.h
M llvm/lib/CodeGen/PrologEpilogInserter.cpp
M llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
A llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir
A llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll
A llvm/test/CodeGen/AMDGPU/vgpr-blocks-funcinfo.mir
M llvm/unittests/Target/AMDGPU/CMakeLists.txt
A llvm/unittests/Target/AMDGPU/LiveRegUnits.cpp
Log Message:
-----------
[AMDGPU] Support block load/store for CSR (#130013)
Add support for using the existing `SCRATCH_STORE_BLOCK` and
`SCRATCH_LOAD_BLOCK` instructions for saving and restoring callee-saved
VGPRs. This is controlled by a new subtarget feature, `block-vgpr-csr`.
It does not include WWM registers - those will be saved and restored
individually, just like before. This patch does not change the ABI.
Use of this feature may lead to slightly increased stack usage, because
the memory is not compacted if certain registers don't have to be
transferred (this will happen in practice for calling conventions where
the callee and caller saved registers are interleaved in groups of 8).
However, if the registers at the end of the block of 32 don't have to be
transferred, we don't need to use a whole 128-byte stack slot - we can
trim some space off the end of the range.
In order to implement this feature, we need to rely less on the
target-independent code in the PrologEpilogInserter, so we override
several new methods in `SIFrameLowering`. We also add new pseudos,
`SI_BLOCK_SPILL_V1024_SAVE/RESTORE`.
One peculiarity is that both the SI_BLOCK_V1024_RESTORE pseudo and the
SCRATCH_LOAD_BLOCK instructions will have all the registers that are not
transferred added as implicit uses. This is done in order to inform
LiveRegUnits that those registers are not available before the restore
(since we're not really restoring them - so we can't afford to scavenge
them). Unfortunately, this trick doesn't work with the save, so before
the save all the registers in the block will be unavailable (see the
unit test).
Commit: 48585caf727004678617dc34fa50383c3f4eb2de
https://github.com/llvm/llvm-project/commit/48585caf727004678617dc34fa50383c3f4eb2de
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/test/Transforms/InstCombine/icmp.ll
Log Message:
-----------
InstCombine: Avoid counting uses of constants (#136566)
Logically it does not matter; getFreelyInvertedImpl doesn't
depend on the value for the m_ImmConstant case.
This use count logic should probably sink into getFreelyInvertedImpl,
every use of this appears to just be a hasOneUse or hasNUse count,
so this could change to just be a use count threshold.
Commit: a1331704752c46cd4d954eb8682af230937fe5a6
https://github.com/llvm/llvm-project/commit/a1331704752c46cd4d954eb8682af230937fe5a6
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/Target/AMDGPU/BUILD.gn
Log Message:
-----------
[gn build] Port 4a58071d8726
Commit: 3cd6b86cc1e1fd1d8d62ca1bcb8498362a4f7b68
https://github.com/llvm/llvm-project/commit/3cd6b86cc1e1fd1d8d62ca1bcb8498362a4f7b68
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachinePipeliner.h
M llvm/lib/CodeGen/MachinePipeliner.cpp
A llvm/test/CodeGen/Hexagon/swp-alias-cross-iteration.mir
A llvm/test/CodeGen/Hexagon/swp-no-alias.mir
Log Message:
-----------
[MachinePipeliner] Use AliasAnalysis properly when analyzing loop-carried dependencies (#136691)
MachinePipeliner uses AliasAnalysis to collect loop-carried memory
dependencies. To analyze loop-carried dependencies, we need to
explicitly tell AliasAnalysis that the values may come from different
iterations. Before this patch, MachinePipeliner didn't do this, so some
loop-carried dependencies might be missed. For example, in the following
case, there is a loop-carried dependency from the load to the store, but
it wasn't considered.
```
def @f(ptr noalias %p0, ptr noalias %p1) {
entry:
br label %body
loop:
%idx0 = phi ptr [ %p0, %entry ], [ %p1, %body ]
%idx1 = phi ptr [ %p1, %entry ], [ %p0, %body ]
%v0 = load %idx0
...
store %v1, %idx1
...
}
```
Further, the handling of the underlying objects was not sound. If there
is no information about memory operands (i.e., `memoperands()` is
empty), it must be handled conservatively. However, Machinepipeliner
uses a dummy value (namely `UnknownValue`). It is distinguished from
other "known" objects, causing necessary dependencies to be missed.
(NOTE: in such cases, `buildSchedGraph` adds non-loop-carried
dependencies correctly, so perhaps a critical problem has not occurred.)
This patch fixes the above problems. This change has increased false
dependencies that didn't exist before. Therefore, this patch also
introduces additional alias checks with the underlying objects.
Split off from #135148
Commit: 0de2f64e652a1b8c1e051635c98fb2b69c6b2c62
https://github.com/llvm/llvm-project/commit/0de2f64e652a1b8c1e051635c98fb2b69c6b2c62
Author: Alex Rønne Petersen <alex at alexrp.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/test/Driver/Xclangas.s
Log Message:
-----------
[clang] XFAIL the `Xclangas.s` test on AIX. (#136744)
Clang on AIX does not use the integrated assembler.
https://github.com/llvm/llvm-project/pull/100714#issuecomment-2822056054
Commit: 11a3de7e98785b0df8f2010fb22c10c0590d2707
https://github.com/llvm/llvm-project/commit/11a3de7e98785b0df8f2010fb22c10c0590d2707
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/IR/RuntimeLibcalls.def
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/ARM/popcnt.ll
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
M llvm/test/CodeGen/RISCV/pr56457.ll
M llvm/test/CodeGen/RISCV/pr95271.ll
M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/RISCV/sextw-removal.ll
M llvm/test/CodeGen/Thumb2/mve-ctpop.ll
Log Message:
-----------
[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall (#101786)
This is a reland of #99752 with the bug fixed (see test diff in the
third commit in this PR).
All `popcount` libcalls return `int`, but `ISD::CTPOP` returns the type
of the argument, which can be wider than `int`. The fix is to make DAG
legalizer pass the correct return type to `makeLibCall` and sign-extend
the result afterwards.
Original commit message:
The main change is adding CTPOP to `RuntimeLibcalls.def` to allow
targets to use LibCall action for CTPOP. DAG legalizers are changed
accordingly.
Pull Request: https://github.com/llvm/llvm-project/pull/101786
Commit: 8e9ff8ea51b5a734df1314bd87ddb8dab31c2fbd
https://github.com/llvm/llvm-project/commit/8e9ff8ea51b5a734df1314bd87ddb8dab31c2fbd
Author: Jerry-Ge <jerry.ge at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaUtilOps.td
M mlir/lib/Conversion/TosaToMLProgram/TosaToMLProgram.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-pipeline.mlir
M mlir/test/Conversion/TosaToMLProgram/tosa-to-mlprogram.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/level_check.mlir
M mlir/test/Dialect/Tosa/variables.mlir
Log Message:
-----------
[mlir][tosa] Align Variable ops to match with TOSA v1.0 spec (#130680)
- updated AnyType:$value to Tosa_Tensor:$input1 and Tosa_Tensor:$output1
for VariableWrite and VriableRead Operators
- updated description discrepancies
- note: in the TOSA spec, we had var_shape attr, but it's already
included
in the TypeAttr:$type in MLIR
Signed-off-by: Jerry Ge <jerry.ge at arm.com>
Commit: a7999f3fba49b7b5da08afb070841f792ea1c796
https://github.com/llvm/llvm-project/commit/a7999f3fba49b7b5da08afb070841f792ea1c796
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
Log Message:
-----------
[NFC][AArch64TTI] Refactor instCombineSVEVectorMul into simplifySVEIntrinsicBinOp.
Commit: 3c3fb357a0ed4dbf640bdb6c61db2a430f7eb298
https://github.com/llvm/llvm-project/commit/3c3fb357a0ed4dbf640bdb6c61db2a430f7eb298
Author: TatWai Chong <tatwai.chong at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
M mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/level_check.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/profile_pro_fp_unsupported.mlir
M mlir/test/Dialect/Tosa/profile_pro_int_unsupported.mlir
M mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
M mlir/test/Dialect/Tosa/verifier.mlir
Log Message:
-----------
[mlir][tosa] Enhance CONV3D & DEPTHWISE_CONV2D verifier (#135738)
Verify the correctness of pad, stride, dilation, and dimension of
input/weight/bias/output.
Adapt and extend the existing conv2d error_if function to support
additional convolution variants.
Commit: 8c47f23232fc8b547f643d379175f322d01e4cbd
https://github.com/llvm/llvm-project/commit/8c47f23232fc8b547f643d379175f322d01e4cbd
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/docs/SPIRVUsage.rst
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroup_matrix_multiply_accumulate/subgroup_matrix_multiply_accumulate_generic.ll
Log Message:
-----------
[SPIRV] Support for the SPV_INTEL_subgroup_matrix_multiply_accumulate SPIR-V extension (#135225)
Adds support for the SPV_INTEL_subgroup_matrix_multiply_accumulate
SPIR-V extension according to
https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_subgroup_matrix_multiply_accumulate.asciidoc
Commit: 15d8b3cae9debc2bd7d27ca92ff599ba9fb30da5
https://github.com/llvm/llvm-project/commit/15d8b3cae9debc2bd7d27ca92ff599ba9fb30da5
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrGISel.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/lower-neon-vector-fcmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vector-fcmp.mir
M llvm/test/CodeGen/AArch64/arm64-zip.ll
M llvm/test/CodeGen/AArch64/select_cc.ll
Log Message:
-----------
[LLVM][ISel][AArch64 Remove AArch64ISD::FCM##z nodes. (#135817)
We can easily select compare-to-zero instructions without dedicated
nodes. The test changes show opportunities that were previous missed
because of the redundant complexity.
Commit: 37e8c6c6ee7c809e45d0e5b61c601a0bb91ca1c4
https://github.com/llvm/llvm-project/commit/37e8c6c6ee7c809e45d0e5b61c601a0bb91ca1c4
Author: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M bolt/lib/Core/MCPlusBuilder.cpp
M bolt/unittests/Core/MCPlusBuilder.cpp
Log Message:
-----------
[BOLT] Do not return Def-ed registers from MCPlusBuilder::getUsedRegs (#129890)
Update the implementation of `MCPlusBuilder::getUsedRegs` to match its
description in the header file, add unit tests.
Commit: c93af22d124ed70742fb692886ff26d8786f8c2d
https://github.com/llvm/llvm-project/commit/c93af22d124ed70742fb692886ff26d8786f8c2d
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineConstantPoolLoads - remove duplicate SDLoc. NFC.
Commit: 720a91183b16f94876adaa831d0a49a04d31420a
https://github.com/llvm/llvm-project/commit/720a91183b16f94876adaa831d0a49a04d31420a
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/preserve-inbounds.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep.ll
Log Message:
-----------
[SeparateConstOffsetFromGEP] Preserve inbounds flag based on ValueTracking and NUW (#130617)
If we know that the initial GEP was inbounds, and we change it to a
sequence of GEPs from the same base pointer where every offset is
non-negative, then the new GEPs are inbounds.
We can also preserve inbounds if the inbounds GEP and the involved additions are NUW.
For SWDEV-516125.
Commit: b0524f332958b6e593868533127fd0651bdcf553
https://github.com/llvm/llvm-project/commit/b0524f332958b6e593868533127fd0651bdcf553
Author: Ben Shi <2283975856 at qq.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/Basic/Targets/AVR.h
M clang/test/CodeGen/avr/avr-inline-asm-constraints.c
M clang/test/CodeGen/avr/avr-unsupported-inline-asm-constraints.c
M llvm/test/CodeGen/AVR/inline-asm/inline-asm-invalid.ll
Log Message:
-----------
[clang][AVR] Improve compatibility of inline assembly with avr-gcc (#136534)
Allow the value 64 to be round up to 0 for constraint 'I'.
Commit: 717efc0a994dfc5b2ed65ddb13b47fb917c9a467
https://github.com/llvm/llvm-project/commit/717efc0a994dfc5b2ed65ddb13b47fb917c9a467
Author: Luke Lau <luke at igalia.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
Log Message:
-----------
[RISCV] Support disjoint RISCVISD::OR_VL in combineOp_VLToVWOp_VL (#136820)
This handles combining fixed-length disjoint ors to vwadd[u].wv, as was
done for scalable vectors in #86929.
vwadd[u].vv patterns need to be handled separately with a pattern in a
separate patch due to the extends being sunk, see #136716.
Commit: 2a9f77f6bd48d757b2d45aadcb6cf76ef4b4ef32
https://github.com/llvm/llvm-project/commit/2a9f77f6bd48d757b2d45aadcb6cf76ef4b4ef32
Author: Björn Pettersson <bjorn.a.pettersson at ericsson.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/Reassociate.cpp
A llvm/test/Transforms/Reassociate/canonicalize-made-change.ll
Log Message:
-----------
[Reassociate] Invalidate analysis passes after canonicalizeOperands (#136835)
When ranking operands for an expression tree the reassociate pass also
perform canonicalization, putting constants on the right hand side. Such
transforms was however not registered as modifying the IR. So at the end
of the pass, if not having made any other changes, the pass returned
that all analyses should be kept.
With this patch we make sure to set MadeChange to true when modifying
the IR via canonicalizeOperands. This is to make sure analyses such as
DemandedBits are properly invalidated when instructions are modified.
Commit: 71ce9e26aec00e4af27a69ccfab8ca1773ed7018
https://github.com/llvm/llvm-project/commit/71ce9e26aec00e4af27a69ccfab8ca1773ed7018
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Sema/AnalysisBasedWarnings.h
M clang/lib/Sema/AnalysisBasedWarnings.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaExpr.cpp
A clang/test/Analysis/pragma-diag-control.cpp
Log Message:
-----------
Control analysis-based diagnostics with #pragma (#136323)
Previously, analysis-based diagnostics (like -Wconsumed) had to be
enabled at file scope in order to be run at the end of each function
body. This meant that they did not respect #pragma clang diagnostic
enabling or disabling the diagnostic.
Now, these pragmas can control the diagnostic emission.
Fixes #42199
Commit: 05b7e97c78ba375cc146c67a4539446f8bcb880c
https://github.com/llvm/llvm-project/commit/05b7e97c78ba375cc146c67a4539446f8bcb880c
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M flang/examples/FeatureList/FeatureList.cpp
M flang/include/flang/Lower/DirectivesCommon.h
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Semantics/symbol.h
M flang/include/flang/Support/Fortran.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/rewrite-directives.cpp
Log Message:
-----------
[flang][OpenMP] Extend common::AtomicDefaultMemOrderType enumeration (#136312)
Add "Acquire" and "Release", and rename it to OmpMemoryOrderType, since
memory order type is a concept extending beyond the
ATOMIC_DEFAULT_MEM_ORDER clause.
When processing a REQUIRES directive (in rewrite-directives.cpp), do not
add Acquire or Release to ATOMIC constructs, because handling of those
types depends on the OpenMP version, which is not available in that
file. This issue will be addressed later.
Commit: 013aab40511bf56a856643105e42c4204fe58f45
https://github.com/llvm/llvm-project/commit/013aab40511bf56a856643105e42c4204fe58f45
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-binop.ll
A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-shift.ll
Log Message:
-----------
[NFC][LLVM] Add test coverage for all binops to sve-intrinsic-simplify-binop.ll.
Also adds sve-intrinsic-simplify-shift.ll to test asr, shl and shr.
Commit: 0f32809139bd104adb2c1de4fa1044da78a7e5af
https://github.com/llvm/llvm-project/commit/0f32809139bd104adb2c1de4fa1044da78a7e5af
Author: arun-thmn <arun.thangamani at intel.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/X86Vector/X86Vector.td
M mlir/include/mlir/Dialect/X86Vector/X86VectorDialect.h
M mlir/include/mlir/Dialect/X86Vector/X86VectorInterfaces.td
M mlir/lib/Dialect/X86Vector/IR/CMakeLists.txt
M mlir/lib/Dialect/X86Vector/IR/X86VectorDialect.cpp
M mlir/lib/Dialect/X86Vector/Transforms/LegalizeForLLVMExport.cpp
M mlir/test/Dialect/X86Vector/legalize-for-llvm.mlir
M mlir/test/Dialect/X86Vector/roundtrip.mlir
M mlir/test/Target/LLVMIR/x86vector.mlir
Log Message:
-----------
Reland [mlir][x86vector] AVX Convert/Broadcast BF16 to F32 instructions (#136830)
Quick fix for the PR: https://github.com/llvm/llvm-project/pull/135143
which failed building on `amd` and `arm` bots build. See the logs in the
above PR for the errors.
Commit: 500cccca0cbcbb547e2a54b25162f20808b45af0
https://github.com/llvm/llvm-project/commit/500cccca0cbcbb547e2a54b25162f20808b45af0
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/Sema/AnalysisBasedWarnings.cpp
Log Message:
-----------
Remove spurious semicolon; NFC
Commit: a99e055030f0da61651e808cbb208bb39594cdc0
https://github.com/llvm/llvm-project/commit/a99e055030f0da61651e808cbb208bb39594cdc0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/BPF/BPFISelLowering.h
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.h
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
Log Message:
-----------
[DAG] shouldReduceLoadWidth - add optional<unsigned> byte offset argument (#136723)
Based off feedback for #129695 - we need to be able to determine the
load offset of smaller loads when trying to determine whether a multiple
use load should be split (in particular for AVX subvector extractions).
This patch adds a std::optional<unsigned> ByteOffset argument to
shouldReduceLoadWidth calls for where we know the constant offset to
allow targets to make use of it in future patches.
Commit: 1fd0b41b44603c190f507f222c16d9f98470f89d
https://github.com/llvm/llvm-project/commit/1fd0b41b44603c190f507f222c16d9f98470f89d
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
R lldb/test/Shell/SymbolFile/DWARF/range-lower-then-low-pc.s
M lldb/test/Shell/SymbolFile/DWARF/x86/discontinuous-inline-function.s
Log Message:
-----------
[lldb/DWARF] Remove "range lower than function low_pc" check (#132395)
The check is not correct for discontinuous functions, as one of the
blocks could very well begin before the function entry point. To catch
dead-stripped ranges, I check whether the functions is after the first
known code address. I don't print any error in this case as that is a
common/expected situation.
This avoids many errors like:
```
error: ld-linux-x86-64.so.2 0x00085f3b: adding range [0x0000000000001ae8-0x0000000000001b07) which has a
base that is less than the function's low PC 0x000000000001cfb0. Please file a bug and attach the file at
the start of this error message
```
when debugging binaries on debian trixie because the dynamic linker
(ld-linux) contains discontinuous functions.
If the block ranges is not a subrange of the enclosing block then this
will range will currently be added to the outer block as well (i.e., we
get the same behavior that's currently possible for non-subrange blocks
larger than function_low_pc). However, this code path is buggy and I'd
like to change that (#117725).
Commit: 94206c9700d52e1a9e42da10e32f0368f9503b44
https://github.com/llvm/llvm-project/commit/94206c9700d52e1a9e42da10e32f0368f9503b44
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/CMakeLists.txt
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.h
A lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndexSet.cpp
A lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndexSet.h
M lldb/unittests/SymbolFile/DWARF/DWARFIndexCachingTest.cpp
Log Message:
-----------
[lldb] Preparation for DWARF indexing speedup (#123732)
This is part of the work proposed in
<https://discourse.llvm.org/t/rfc-speeding-up-dwarf-indexing-again/83979>.
One of the change is that the there will be a different structure for
holding the partial indexes and the final (consolidated) index. To
prepare for this, I'm making the IndexSet structure a template. The
index cache encoding/decoding methods are changed into free functions,
as they only need to know how to work with the final index.
I've moved this functionality to a separate file as all this doesn't
really depend on the rest of the ManualDWARFIndex and it needs to be
public due to its use in the unit test (both of which indicate that it
could be a component of its own).
Commit: 4e073a11c24cc0abfe5a8eabd99f1e4762c89e2b
https://github.com/llvm/llvm-project/commit/4e073a11c24cc0abfe5a8eabd99f1e4762c89e2b
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/Plugins/SymbolFile/DWARF/BUILD.gn
Log Message:
-----------
[gn build] Port 94206c9700d5
Commit: 6bb2f90557fb2b4b216299cc2beb4afb641476aa
https://github.com/llvm/llvm-project/commit/6bb2f90557fb2b4b216299cc2beb4afb641476aa
Author: Diana Picus <Diana-Magda.Picus at amd.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineFrameInfo.h
M llvm/include/llvm/CodeGen/TargetFrameLowering.h
M llvm/lib/CodeGen/PrologEpilogInserter.cpp
M llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
R llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir
R llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll
R llvm/test/CodeGen/AMDGPU/vgpr-blocks-funcinfo.mir
M llvm/unittests/Target/AMDGPU/CMakeLists.txt
R llvm/unittests/Target/AMDGPU/LiveRegUnits.cpp
Log Message:
-----------
Revert "[AMDGPU] Support block load/store for CSR" (#136846)
Reverts llvm/llvm-project#130013 due to failures with expensive checks
on.
Commit: 673882cfbc5cf8425444811f92080bdd0b7cbb78
https://github.com/llvm/llvm-project/commit/673882cfbc5cf8425444811f92080bdd0b7cbb78
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/Target/AMDGPU/BUILD.gn
Log Message:
-----------
[gn build] Port 6bb2f90557fb
Commit: 14b38cf946c5b10039865f1aaedac8ea1ca06abb
https://github.com/llvm/llvm-project/commit/14b38cf946c5b10039865f1aaedac8ea1ca06abb
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/matmul.mlir
Log Message:
-----------
[mlir][vector] Update test post 136699 (nfc) (#136841)
Updates a test that I forgot to update in #136699. Failing bot:
* https://lab.llvm.org/buildbot/#/builders/143/builds/7166
Commit: 8292e050e62f69ae9aea68fafd011152eede7e4d
https://github.com/llvm/llvm-project/commit/8292e050e62f69ae9aea68fafd011152eede7e4d
Author: Wenju He <wenju.he at intel.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M libclc/CMakeLists.txt
Log Message:
-----------
[libclc] Build for OpenCL 3.0 (#135733)
This PR is modified cherry-pick of
https://github.com/intel/llvm/commit/cba338e5fb1c
This PR sets OpenCL language version to be the same, which is 3.0,
for every target and device, in order to unify the build process.
Target should define supported extensions and features via
setSupportedOpenCLOpts API.
llvm-diff shows one change to amdgcn--amdhsa.bc:
* ctz symbols are added since they are now enabled for amdgcn.
Commit: 1ce709cb845b8b0bc4625198afa7a26c0a198fe4
https://github.com/llvm/llvm-project/commit/1ce709cb845b8b0bc4625198afa7a26c0a198fe4
Author: Nicholas Guy <nicholas.guy at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-no-dotprod.ll
Log Message:
-----------
[LV] Fix crash when building partial reductions using types that aren't known scale factors (#136680)
Commit: a1f369e6309c8c6adaae886afc55817b97953641
https://github.com/llvm/llvm-project/commit/a1f369e6309c8c6adaae886afc55817b97953641
Author: Nicholas Guy <nicholas.guy at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
Log Message:
-----------
[AArch64][SVE] Add dot product lowering for PARTIAL_REDUCE_MLA node (#130933)
Add lowering in tablegen for PARTIAL_REDUCE_U/SMLA ISD nodes. Only
happens when the combine has been performed on the ISD node. Also adds
in check to only do the DAG combine when the node can then eventually be
lowered, so changes neon tests too.
---------
Co-authored-by: James Chesterman <james.chesterman at arm.com>
Commit: 386ff113f974967dee9d3fd654c2259a94c59b2e
https://github.com/llvm/llvm-project/commit/386ff113f974967dee9d3fd654c2259a94c59b2e
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
Log Message:
-----------
[flang][OpenMP] Use OmpMemoryOrderType enumeration in FAIL clause (#136313)
Make the FAIL clause contain OmpMemoryOrderType enumeration instead of
OmpClause. This simplifies the semantic checks of the FAIL clause.
Commit: 5b0cd17c386ecd126c7f0ab514413bab8222b421
https://github.com/llvm/llvm-project/commit/5b0cd17c386ecd126c7f0ab514413bab8222b421
Author: Virginia Cangelosi <virginia.cangelosi at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/include/clang/Basic/arm_sme.td
A clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
A clang/test/Sema/aarch64-sme2p2-instrinsics/acle_sme2p2_fp8_imm.cpp
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/SMEInstrFormats.td
A llvm/test/CodeGen/AArch64/sme2-intrinsics-mop4-fp8.ll
Log Message:
-----------
[Clang][llvm] Implement fp8 FMOP4A intrinsics (#130127)
Implement all mf8 FMOP4A instructions in clang and llvm following the
acle in https://github.com/ARM-software/acle/pull/381/files.
It also updates previous mop4 instructions from IntrNoMem to
IntrInaccessibleMemOnly
Commit: 92bba68634ec48c738d45bc86b05b1390aa82f4b
https://github.com/llvm/llvm-project/commit/92bba68634ec48c738d45bc86b05b1390aa82f4b
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/Frontend/OpenMP/OMPDeviceConstants.h
M offload/DeviceRTL/src/Kernel.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/test/offloading/ompx_bare.c
M offload/test/offloading/ompx_bare_multi_dim.cpp
Log Message:
-----------
[Offload] Fix handling of 'bare' mode when environment missing (#136794)
Summary:
We treated the missing kernel environment as a unique mode, but it was
kind of this random bool that was doing the same thing and it explicitly
expects the kernel environment to be zero. It broke after the previous
change since it used to default to SPMD and didn't handle zero in any of
the other cases despite being used. This fixes that and queries for it
without needing to consume an error.
Commit: 6d0d50f0ac0cb108a06558cb178a68fb78cfa06f
https://github.com/llvm/llvm-project/commit/6d0d50f0ac0cb108a06558cb178a68fb78cfa06f
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M offload/DeviceRTL/CMakeLists.txt
Log Message:
-----------
[OpenMP] Update the bitcode library install and search path (#136754)
Summary:
This was accidentally kept in the old location when we moved to the
new `lib/<triple>/` location for the DeviceRTL. Move this to reduce the
delta with https://github.com/llvm/llvm-project/pull/136729.
Commit: 91e1922d45bdefd444a2ba0484fd858e2ad80254
https://github.com/llvm/llvm-project/commit/91e1922d45bdefd444a2ba0484fd858e2ad80254
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
Log Message:
-----------
[DSE] Skip non-pointer args in initializes handling (NFCI)
Avoid performing AA queries on non-pointers.
Commit: 14dee0aeaaef2ebd5c3295edca4c5d3762464934
https://github.com/llvm/llvm-project/commit/14dee0aeaaef2ebd5c3295edca4c5d3762464934
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/NewGVN.cpp
Log Message:
-----------
[NewGVN] Avoid AA query on non-pointers (NFCI)
In order for the instruction result to alias with the pointer it
needs to be a pointer.
Commit: 01ee03c262519597307301715dc4d41e6d62b774
https://github.com/llvm/llvm-project/commit/01ee03c262519597307301715dc4d41e6d62b774
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Coroutines/CoroElide.cpp
Log Message:
-----------
[CoroElide] Avoid AA query on non-pointers (NFCI)
Commit: 208257f7e0f1e7bbf878753bb8a7554891b84380
https://github.com/llvm/llvm-project/commit/208257f7e0f1e7bbf878753bb8a7554891b84380
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Coroutines/CoroElide.cpp
Log Message:
-----------
[CoroElide] Remove unnecessary bitcast (NFCI)
No longer needed with opaque pointers.
Commit: eea1efed305fbeba5dc2b5e856d934ba8e57965c
https://github.com/llvm/llvm-project/commit/eea1efed305fbeba5dc2b5e856d934ba8e57965c
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
Log Message:
-----------
[InstrProfiling] Avoid unnecessary bitcast (NFC)
Not needed with opaque pointers.
Commit: 00934beb8e6b9a5fe04ff7805249706d0edc3c5b
https://github.com/llvm/llvm-project/commit/00934beb8e6b9a5fe04ff7805249706d0edc3c5b
Author: jyli0116 <jyli0116 at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/test/CodeGen/AArch64/fsh.ll
Log Message:
-----------
[AArch64] Funnel Shift now uses rev32/rev64 instructions (#136707)
Fixes #130469
Now uses REV32/REV64 instructions to complete operation.
New Output:
```
G1:
rev64 v0.4s, v0.4s
ret
G2:
rev32 v0.8h, v0.8h
ret
G3:
rev16 v0.16b, v0.16b
ret
G4:
rev32 v0.4h, v0.4h
ret
G5:
rev16 v0.8b, v0.8b
ret
```
Old Output:
```
G1:
shl v1.2d, v0.2d, #32
usra v1.2d, v0.2d, #32
mov v0.16b, v1.16b
ret
G2:
shl v1.4s, v0.4s, #16
usra v1.4s, v0.4s, #16
mov v0.16b, v1.16b
ret
G3:
rev16 v0.16b, v0.16b
ret
G4:
shl v1.2s, v0.2s, #16
usra v1.2s, v0.2s, #16
fmov d0, d1
ret
G5:
rev16 v0.8b, v0.8b
ret
```
Commit: 52cb1c93acdad4fa2aa0ce17691d7205cc9645f9
https://github.com/llvm/llvm-project/commit/52cb1c93acdad4fa2aa0ce17691d7205cc9645f9
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
Log Message:
-----------
[AArch64Arm64ECCallLowering] Remove unnecessary bitcasts (NFCI)
These are all pointer bitcasts, which are no longer necessary
with opaque pointers.
Commit: a2c1ff10eb930dd56be306dc0818d6ff31fff546
https://github.com/llvm/llvm-project/commit/a2c1ff10eb930dd56be306dc0818d6ff31fff546
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
Log Message:
-----------
[mlir][acc] Use consistent name for device_num operand (#136745)
`acc.set`, `acc.init`, and `acc.shutdown` take a `device_num` operand.
However, this was named inconsistently. Give it the same consistent name
for all aforementioned operations.
---------
Co-authored-by: erichkeane <ekeane at nvidia.com>
Commit: 4cc806f9f5b76b3ca42de29fb6a3affe9774d7f8
https://github.com/llvm/llvm-project/commit/4cc806f9f5b76b3ca42de29fb6a3affe9774d7f8
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
Log Message:
-----------
[AArch64Arm64ECCallLowering] Drop unnecessary pointer type members (NFC)
With opaque pointers, these are all the same type. Consolidate to
just PtrTy.
Commit: 5afe85982a6e911326c5df141c718b239edea9c8
https://github.com/llvm/llvm-project/commit/5afe85982a6e911326c5df141c718b239edea9c8
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
Log Message:
-----------
[OMPIRBuilder] Remove unnecessary pointer bitcasts (NFCI)
Not needed with opaque pointers.
Commit: 237ed0cffcd721f0ae48420f17db2e2da97fb625
https://github.com/llvm/llvm-project/commit/237ed0cffcd721f0ae48420f17db2e2da97fb625
Author: Christian Sigg <csigg at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] Port 0f32809139bd104adb2c1de4fa1044da78a7e5af.
Commit: e58d227b09d533e2df644f827cedff8e206e0bfc
https://github.com/llvm/llvm-project/commit/e58d227b09d533e2df644f827cedff8e206e0bfc
Author: Tobias Stadler <mail at stadler-tobias.de>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
A llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector.mir
Log Message:
-----------
[NFC][AArch64][GlobalISel] Add test coverage for vector load/store legalization (#134904)
Precommit tests for vector load/store legalization changes. This exposes
a miscompile in LegalizerHelper::reduceLoadStoreWidth for non-byte-sized
vector elements, which will be fixed in a follow-up patch.
The other tests are potential miscompilations due to unclear semantics
of vector load/stores, which will be addressed in a follow-up
discussion.
Commit: 46f18b7c6febe75b2cc0095f2227d935c14f70f2
https://github.com/llvm/llvm-project/commit/46f18b7c6febe75b2cc0095f2227d935c14f70f2
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M libcxxabi/test/test_demangle.pass.cpp
Log Message:
-----------
[ItaniumDemangle][test] Add test-cases for ref-qualified member pointer parameters
I noticed that there are test-cases that are commented out. But the
manglings for them seem to be impossible to generate from valid C++. I
added two test-cases generated from following C++ program:
```
struct X {
int func() const && { return 5; }
const int &&func2() { return 5; }
const int &&func3(const int &x) volatile { return 5; }
};
void f(int (X::*)() const &&, int const && (X::*)(),
int const && (X::*)(const int &) volatile) {}
int main() {
f(&X::func, &X::func2, &X::func3);
return 0;
}
```
Commit: 8158d43da33b33d260f2c43eb3f448f42b839b21
https://github.com/llvm/llvm-project/commit/8158d43da33b33d260f2c43eb3f448f42b839b21
Author: Dmitriy Smirnov <dmitriy.smirnov at arm.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
Log Message:
-----------
[TOSA] Rescale output_zp fix (#136116)
Patch corrects output_zp in case of usigned output
Commit: 8502ba1eb40acdb0eda1039807afc34db0c7084a
https://github.com/llvm/llvm-project/commit/8502ba1eb40acdb0eda1039807afc34db0c7084a
Author: lorenzo chelini <l.chelini at icloud.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/MemRef/Transforms/Passes.h
M mlir/include/mlir/Dialect/MemRef/Transforms/Passes.td
M mlir/lib/Dialect/Bufferization/Pipelines/BufferizationPipelines.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandRealloc.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
M mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/NormalizeMemRefs.cpp
M mlir/lib/Dialect/MemRef/Transforms/ResolveShapedTypeResultDims.cpp
M mlir/test/python/pass_manager.py
Log Message:
-----------
[MLIR][NFC] Retire let constructor for MemRef (#134788)
let constructor is legacy (do not use in tree!) since the tableGen
backend emits most of the glue logic to build a pass.
Note: The following constructor has been retired:
```cpp
std::unique_ptr<Pass> createExpandReallocPass(bool emitDeallocs = true);
```
To update your codebase, replace it with the new options-based API:
```cpp
memref::ExpandReallocPassOptions expandAllocPassOptions{
/*emitDeallocs=*/false};
pm.addPass(memref::createExpandReallocPass(expandAllocPassOptions));
```
Commit: 806d59eecd16dc35473638fd73ea0be8e59c6275
https://github.com/llvm/llvm-project/commit/806d59eecd16dc35473638fd73ea0be8e59c6275
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M libclc/generic/include/clc/image/image.h
Log Message:
-----------
[libclc] Fix unguarded use of image types (#136871)
Commit 8292e05 which switched the OpenCL C version to 3.0 exposed this
issue, which wasn't caught in pre-commit CI.
Commit: 6c561604336497cbeebc90f9066a9f474458a38d
https://github.com/llvm/llvm-project/commit/6c561604336497cbeebc90f9066a9f474458a38d
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M libclc/CMakeLists.txt
Log Message:
-----------
[libclc] Re-enable compiler warning (#136872)
libclc is now clean of code that triggers the
bitwise-conditional-parentheses warning, so we can finally remove the
workaround.
Commit: f11b3decdd603655d886061c0b2e26b64a6563d2
https://github.com/llvm/llvm-project/commit/f11b3decdd603655d886061c0b2e26b64a6563d2
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M flang/lib/Optimizer/CodeGen/TargetRewrite.cpp
M flang/test/Fir/CUDA/cuda-target-rewrite.mlir
Log Message:
-----------
[flang][cuda] Carry over the CUDA attribute in target rewrite (#136811)
Commit: 96519028d514853d429c2d09482ba0bd9a899c57
https://github.com/llvm/llvm-project/commit/96519028d514853d429c2d09482ba0bd9a899c57
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/source/Plugins/Language/CPlusPlus/LibCxxInitializerList.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxSpan.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxVariant.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxVector.cpp
Log Message:
-----------
[lldb][DataFormatters] Make data-formatters log to the DataFormatters channel
Currently the data-formatters log to either DataFormatters or Types. The
former is probably more sensible, so log there consistently from all
formatters.
Commit: cc6def4b7521676fd339936d027e48928e0ba398
https://github.com/llvm/llvm-project/commit/cc6def4b7521676fd339936d027e48928e0ba398
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M libc/src/stdio/printf_core/core_structs.h
Log Message:
-----------
[libc] Special case PPC double double for print (#136614)
Summary:
We use the storage class for `long double` in the printing
implementations. We don't fully support the PPC double double type,
which that maps to, but we can stub out just the support needed for the
print interface to works. This required using the internal interface for
storage type, but it should be good enough.
Fixes: https://github.com/llvm/llvm-project/issues/136596
Commit: ecb0daa72c442caeb4e295e1076d54c5e18101b2
https://github.com/llvm/llvm-project/commit/ecb0daa72c442caeb4e295e1076d54c5e18101b2
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/utils/TableGen/DecoderEmitter.cpp
Log Message:
-----------
[NFC][LLVM][TableGen] Eliminate inheritance from std::vector (#136573)
Commit: 79151244d6a501c027add60734ddfe4c609e75bb
https://github.com/llvm/llvm-project/commit/79151244d6a501c027add60734ddfe4c609e75bb
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Log Message:
-----------
[DAG] narrowExtractedVectorLoad - reuse existing SDLoc. NFC (#136870)
Commit: 2e389cb9aae0e9734fc8e16f6ebc6edb392d79a9
https://github.com/llvm/llvm-project/commit/2e389cb9aae0e9734fc8e16f6ebc6edb392d79a9
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M flang/test/Semantics/OpenACC/acc-data.f90
M llvm/include/llvm/Frontend/OpenACC/ACC.td
Log Message:
-----------
[Flang][OpenACC] Make async clause on data consistent with elsewhere (#136866)
in #136610 we agreed that all async clauses on compute constructs should
act as 'only 1 per device-type-group'. On `data`, it has the same
specification language, and the same real requirements, so it seems
sensible to make it work the same way.
Commit: 8abc917fe04140b6c6088a67e0398f637efde808
https://github.com/llvm/llvm-project/commit/8abc917fe04140b6c6088a67e0398f637efde808
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-04-24 (Thu, 24 Apr 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/test/Transforms/InstCombine/and-fcmp.ll
Log Message:
-----------
[InstCombine] Do not fold logical is_finite test (#136851)
This patch disables the fold for logical is_finite test (i.e., `and
(fcmp ord x, 0), (fcmp u* x, inf) -> fcmp o* x, inf`).
It is still possible to allow this fold for several logical cases (e.g.,
`stripSignOnlyFPOps(RHS0)` does not strip any operations). Since this
patch has no real-world impact, I decided to disable this fold for all
logical cases.
Alive2: https://alive2.llvm.org/ce/z/aH4LC7
Closes https://github.com/llvm/llvm-project/issues/136650.
Commit: 24c860547e8e595f8bf8d87b52544e2aff243f2e
https://github.com/llvm/llvm-project/commit/24c860547e8e595f8bf8d87b52544e2aff243f2e
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
Log Message:
-----------
AMDGPU/MC: Fix emitting absolute expressions (#136789)
When absolute MCExprs appear in normal instruction operands, we have to
emit them like a normal inline constant or literal. More generally, an
MCExpr that happens to have an absolute evaluation should be treated
exactly like an immediate operand here.
No test; I found this downstream, and I don't think it can be triggered
upstream yet.
Fixes: 16238669 ("[AMDGPU][MC] Support UC_VERSION_* constants. (#95618)")
Commit: 2f0cd0c68ef027f87f34f04141c083212fda2806
https://github.com/llvm/llvm-project/commit/2f0cd0c68ef027f87f34f04141c083212fda2806
Author: Mingming Liu <mingmingl at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/lib/ProfileData/InstrProf.cpp
M llvm/lib/ProfileData/InstrProfWriter.cpp
Log Message:
-----------
[NFCI] Move ProfOStream from InstrProfWriter.cpp to InstrProf.h/cpp (#136791)
ProfOStream is a wrapper class for output stream, and used by
InstrProfWriter.cpp to serialize various profiles, like PGO profiles and
MemProf.
This change proposes to move it into InstrProf.h/cpp. After this is in,
InstrProfWriter can dispatch serialization of various formats into
methods like `obj->serialize()`, and the serialization code could be
move out of InstrProfWriter.cpp into individual classes (each in a
smaller cpp file). One example is that we can gradually move
writeMemprof [1] into llvm/*/ProfileData/MemProf.h/cpp, where a couple
of classes already have `serialize/deserialize` methods.
[1]
https://github.com/llvm/llvm-project/blob/85b35a90770b6053f91d79ca685cdfa4bf6499a4/llvm/lib/ProfileData/InstrProfWriter.cpp#L774-L791
Commit: 1da856a685cf427ab1f5b810125c41e7859ed362
https://github.com/llvm/llvm-project/commit/1da856a685cf427ab1f5b810125c41e7859ed362
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndexSet.h
Log Message:
-----------
[lldb] Fix typo in ManualDWARFIndexSet.h
operator== wasn't used in production code, but the bad definition made
the tests vacuosly pass.
Commit: a83b4a2dc9706d9e898f3462b5c2ff5ed05589d2
https://github.com/llvm/llvm-project/commit/a83b4a2dc9706d9e898f3462b5c2ff5ed05589d2
Author: Justin Bogner <mail at justinbogner.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/include/llvm/Analysis/DXILResource.h
M llvm/lib/Target/DirectX/CMakeLists.txt
A llvm/lib/Target/DirectX/DXILForwardHandleAccesses.cpp
A llvm/lib/Target/DirectX/DXILForwardHandleAccesses.h
M llvm/lib/Target/DirectX/DirectX.h
M llvm/lib/Target/DirectX/DirectXPassRegistry.def
M llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/alloca.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/ambiguous.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/buffer-O0.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/cbuffer-access.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/undominated.ll
M llvm/test/CodeGen/DirectX/llc-pipeline.ll
Log Message:
-----------
[DirectX] Implement the ForwardHandleAccesses pass (#135378)
This pass attempts to forward resource handle creation to accesses of
the handle global. This avoids dependence on optimizations like CSE and
GlobalOpt for correctness of DXIL.
Fixes #134574.
Commit: ea5449ddd5d03da034eccb80e5ba1e44ee02e243
https://github.com/llvm/llvm-project/commit/ea5449ddd5d03da034eccb80e5ba1e44ee02e243
Author: erichkeane <ekeane at nvidia.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M clang/test/CIR/CodeGenOpenACC/data.c
M clang/test/SemaOpenACC/data-construct-async-clause.c
Log Message:
-----------
[OpenACC][CIR] Implement 'async'/'if' lowering for 'data' construct
These two are trivial, and work the same as the compute construct
versions of these, so this adds tests to do so, and adds them to the
implementation.
Commit: d7215c0ee2e4bca1ce87b956335ef6a2cddaf16f
https://github.com/llvm/llvm-project/commit/d7215c0ee2e4bca1ce87b956335ef6a2cddaf16f
Author: Jannick Kremer <jannick.kremer at mailbox.org>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/tools/libclang/CIndex.cpp
M clang/unittests/libclang/LibclangTest.cpp
Log Message:
-----------
[libclang/C++] Fix clang_File_isEqual for in-memory files (#135773)
Add tests for `clang_File_isEqual` (on-disk and in-memory)
Commit: 83c309b90550aa768ff9aa11b70898ee2c56b71e
https://github.com/llvm/llvm-project/commit/83c309b90550aa768ff9aa11b70898ee2c56b71e
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/include/clang/Sema/ScopeInfo.h
M clang/include/clang/Sema/SemaCUDA.h
M clang/lib/Sema/SemaCUDA.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaOverload.cpp
A clang/test/CodeGenCUDA/lambda-constexpr-capture.cu
Log Message:
-----------
[CUDA][HIP] capture possible ODR-used var (#136645)
In a lambda function, a call of a function may
resolve to host and device functions with different
signatures. Especially, a constexpr local variable may
be passed by value by the device function and
passed by reference by the host function, which
will cause the constexpr variable captured by
the lambda function in host compilation but
not in the device compilation. The discrepancy
in the lambda captures will violate ODR and
causes UB for kernels using these lambdas.
This PR fixes the issue by identifying
discrepancy of ODR/non-ODR usages of constexpr
local variables passed to host/device functions
and conservatively capture them.
Fixes: https://github.com/llvm/llvm-project/issues/132068
Commit: 1b6cbaa7b64f54b127d139d653468e213bae007e
https://github.com/llvm/llvm-project/commit/1b6cbaa7b64f54b127d139d653468e213bae007e
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/PrimType.h
M clang/test/AST/ByteCode/literals.cpp
Log Message:
-----------
[clang][bytecode] Refine diagnostics for volatile reads (#136857)
Differentiate between a volarile read via a lvalue-to-rvalue cast of a
volatile qualified subexpression and a read from a pointer with a
volatile base object.
Commit: 6dbc01e8015816e904687c03f0ea8afac817781d
https://github.com/llvm/llvm-project/commit/6dbc01e8015816e904687c03f0ea8afac817781d
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
M llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AMDGPU/fpext-free.ll
M llvm/test/CodeGen/AMDGPU/fpow.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/function-args.ll
M llvm/test/CodeGen/AMDGPU/function-returns.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.wave32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/lrint.ll
M llvm/test/CodeGen/AMDGPU/lround.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/strict_fpext.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
M llvm/test/CodeGen/AMDGPU/vector_rebroadcast.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vopc_dpp.mir
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
Log Message:
-----------
[AMDGPU][True16][CodeGen] update GFX11Plus codegen test with true16 flag (#135078)
This is a NFC patch.
This patch run a bulk update on CodeGen tests that are impacted by the
true16 features. This patch applies:
1. duplicate GFX11plus runlines and apply them with
"+mattr=+real-true16" and "+mattr=-real-true16"
2. update the test with the update script
For some GISEL runlines, the current CodeGen do not fully support the
true16 version. Still update the runlines, but comment out the failing
one, and added a "FIXME-TRUE16" comment to that test for easier
tracking. These test will be fixed in the following patches.
This is in a transition state that we support both
"+real-true16/-real-true16" in our code base. We plan to move to
"+real-true16" as default, and finally remove "-real-true16" mode and
test lines.
Commit: 1041d54bd4f693c1ac03077680ece67e03c99e22
https://github.com/llvm/llvm-project/commit/1041d54bd4f693c1ac03077680ece67e03c99e22
Author: John Harrison <harjohn at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/Handler/CancelRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/DisconnectRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/NextRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
M lldb/tools/lldb-dap/Protocol/ProtocolBase.h
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
M lldb/tools/lldb-dap/Transport.cpp
Log Message:
-----------
[lldb-dap] Updating the 'next' request handler use well structured types (#136642)
This updates the 'next' request to use well structured types. While
working on this I also simplified the 'RequestHandler' implementation to
better handle void responses by allowing requests to return a
'llvm::Error' instead of an 'llvm::Expected<std::monostate>'. This makes
it easier to write and understand request handles that have simple ack
responses.
Commit: 060f3f0dd1614b624b527e871019970e4303de11
https://github.com/llvm/llvm-project/commit/060f3f0dd1614b624b527e871019970e4303de11
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/include/clang/Frontend/CompilerInstance.h
M clang/include/clang/Lex/DependencyDirectivesScanner.h
M clang/include/clang/Lex/Preprocessor.h
M clang/include/clang/Lex/PreprocessorOptions.h
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningFilesystem.h
M clang/lib/Frontend/CompilerInstance.cpp
M clang/lib/Lex/PPLexerChange.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
M clang/unittests/Lex/PPDependencyDirectivesTest.cpp
Log Message:
-----------
[clang][deps] Make dependency directives getter thread-safe (#136178)
This PR fixes two issues in one go:
1. The dependency directives getter (a `std::function`) was being stored
in `PreprocessorOptions`. This goes against the principle where the
options classes are supposed to be value-objects representing the `-cc1`
command line arguments. This is fixed by moving the getter directly to
`CompilerInstance` and propagating it explicitly.
2. The getter was capturing the `ScanInstance` VFS. That's fine in
synchronous implicit module builds where the same VFS instance is used
throughout, but breaks down once you try to build modules asynchronously
(which forces the use of separate VFS instances). This is fixed by
explicitly passing a `FileManager` into the getter and extracting the
right instance of the scanning VFS out of it.
Commit: 385b07b5038ff65f084446a92849e54fd86bd3a7
https://github.com/llvm/llvm-project/commit/385b07b5038ff65f084446a92849e54fd86bd3a7
Author: Paul Kirth <paulkirth at google.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang-tools-extra/clang-doc/Serialize.cpp
Log Message:
-----------
[clang-doc][NFC] Remove else after return (#136443)
Commit: 0f5965fa9c67969e4de7374362b6af49bf400b3b
https://github.com/llvm/llvm-project/commit/0f5965fa9c67969e4de7374362b6af49bf400b3b
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/test/CIR/CodeGen/struct.c
M clang/test/CIR/CodeGen/struct.cpp
M clang/test/CIR/CodeGen/typedef.c
M clang/test/CIR/CodeGen/union.c
M clang/test/CIR/IR/struct.cir
Log Message:
-----------
[CIR] Introduce type aliases for records (#136387)
This introduces MLIR aliases for ClangIR record types. These are used in
the incubator and having skipped over them upstream is causing the tests
to diverge.
Commit: 3c9027c1d7aac0c1e54af13182f1b8f58d376115
https://github.com/llvm/llvm-project/commit/3c9027c1d7aac0c1e54af13182f1b8f58d376115
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M clang/lib/Serialization/ModuleManager.cpp
M clang/test/Modules/explicit-build.cpp
Log Message:
-----------
[clang][Modules] Clarify error message when size check fails in lookupModuleFile
Commit: dbb8434ff7b9bb414e2222cb8d9cddac599eadc6
https://github.com/llvm/llvm-project/commit/dbb8434ff7b9bb414e2222cb8d9cddac599eadc6
Author: Peter Collingbourne <peter at pcc.me.uk>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Log Message:
-----------
SelectionDAG: Add missing AddNodeIDCustom case for MDNodeSDNode.
Without this we ended up never deduplicating MDNodeSDNodes.
Reviewers: arsenm
Reviewed By: arsenm
Pull Request: https://github.com/llvm/llvm-project/pull/136805
Commit: 45a4d300f5505956d2319581a02a0ecc87ad4091
https://github.com/llvm/llvm-project/commit/45a4d300f5505956d2319581a02a0ecc87ad4091
Author: Peter Collingbourne <peter at pcc.me.uk>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M bolt/lib/Core/MCPlusBuilder.cpp
M bolt/unittests/Core/MCPlusBuilder.cpp
M clang-tools-extra/clang-doc/Serialize.cpp
M clang-tools-extra/clangd/InlayHints.cpp
M clang-tools-extra/clangd/InlayHints.h
M clang-tools-extra/clangd/unittests/InlayHintTests.cpp
M clang/docs/ReleaseNotes.rst
M clang/docs/StandardCPlusPlusModules.rst
M clang/include/clang/AST/Type.h
M clang/include/clang/Basic/arm_sme.td
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/Frontend/CompilerInstance.h
M clang/include/clang/Lex/DependencyDirectivesScanner.h
M clang/include/clang/Lex/Preprocessor.h
M clang/include/clang/Lex/PreprocessorOptions.h
M clang/include/clang/Sema/AnalysisBasedWarnings.h
M clang/include/clang/Sema/ScopeInfo.h
M clang/include/clang/Sema/SemaCUDA.h
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningFilesystem.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpState.cpp
M clang/lib/AST/ByteCode/InterpState.h
M clang/lib/AST/ByteCode/PrimType.h
M clang/lib/AST/Type.cpp
M clang/lib/Basic/Targets/AVR.h
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Format/FormatTokenLexer.cpp
M clang/lib/Format/FormatTokenLexer.h
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Frontend/CompilerInstance.cpp
M clang/lib/Lex/PPLexerChange.cpp
M clang/lib/Sema/AnalysisBasedWarnings.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaCUDA.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Serialization/ModuleManager.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
M clang/test/AST/ByteCode/c.c
M clang/test/AST/ByteCode/cxx11.cpp
M clang/test/AST/ByteCode/cxx23.cpp
M clang/test/AST/ByteCode/cxx26.cpp
M clang/test/AST/ByteCode/literals.cpp
A clang/test/Analysis/pragma-diag-control.cpp
M clang/test/CIR/CodeGen/struct.c
M clang/test/CIR/CodeGen/struct.cpp
M clang/test/CIR/CodeGen/typedef.c
M clang/test/CIR/CodeGen/union.c
M clang/test/CIR/CodeGenOpenACC/data.c
M clang/test/CIR/IR/struct.cir
A clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
M clang/test/CodeGen/avr/avr-inline-asm-constraints.c
M clang/test/CodeGen/avr/avr-unsupported-inline-asm-constraints.c
A clang/test/CodeGenCUDA/lambda-constexpr-capture.cu
M clang/test/Driver/Xclangas.s
M clang/test/Driver/cxa-atexit.cpp
M clang/test/Driver/riscv-cpus.c
M clang/test/Misc/target-invalid-cpu-note/riscv.c
M clang/test/Modules/explicit-build.cpp
A clang/test/Sema/aarch64-sme2p2-instrinsics/acle_sme2p2_fp8_imm.cpp
M clang/test/SemaOpenACC/data-construct-async-clause.c
M clang/tools/libclang/CIndex.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/FormatTestJS.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M clang/unittests/Lex/PPDependencyDirectivesTest.cpp
M clang/unittests/libclang/LibclangTest.cpp
M flang/examples/FeatureList/FeatureList.cpp
M flang/include/flang/Lower/DirectivesCommon.h
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Semantics/symbol.h
M flang/include/flang/Support/Fortran.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Optimizer/CodeGen/TargetRewrite.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/rewrite-directives.cpp
M flang/test/Fir/CUDA/cuda-target-rewrite.mlir
M flang/test/Semantics/OpenACC/acc-data.f90
M libc/src/math/generic/expm1f.cpp
M libc/src/stdio/printf_core/core_structs.h
M libclc/CMakeLists.txt
M libclc/generic/include/clc/image/image.h
M libcxxabi/test/test_demangle.pass.cpp
M lldb/source/Core/Debugger.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxInitializerList.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxSpan.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxVariant.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxVector.cpp
M lldb/source/Plugins/SymbolFile/DWARF/CMakeLists.txt
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.h
A lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndexSet.cpp
A lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndexSet.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
M lldb/test/API/functionalities/statusline/TestStatusline.py
R lldb/test/Shell/SymbolFile/DWARF/range-lower-then-low-pc.s
M lldb/test/Shell/SymbolFile/DWARF/x86/discontinuous-inline-function.s
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/Handler/CancelRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/DisconnectRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/NextRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
M lldb/tools/lldb-dap/Protocol/ProtocolBase.h
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
M lldb/tools/lldb-dap/Transport.cpp
M lldb/unittests/SymbolFile/DWARF/DWARFIndexCachingTest.cpp
M llvm/docs/ReleaseNotes.md
M llvm/docs/SPIRVUsage.rst
M llvm/include/llvm/Analysis/DXILResource.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/MachinePipeliner.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/Frontend/OpenACC/ACC.td
M llvm/include/llvm/Frontend/OpenMP/OMPDeviceConstants.h
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/include/llvm/IR/RuntimeLibcalls.def
M llvm/include/llvm/IR/Value.h
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/include/llvm/Support/InstructionCost.h
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/include/llvm/Transforms/Utils/UnrollLoop.h
M llvm/lib/Analysis/CostModel.cpp
M llvm/lib/Analysis/InlineSizeEstimatorAnalysis.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/PrologEpilogInserter.cpp
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/Value.cpp
M llvm/lib/ProfileData/InstrProf.cpp
M llvm/lib/ProfileData/InstrProfWriter.cpp
M llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrGISel.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/BPF/BPFISelLowering.h
M llvm/lib/Target/DirectX/CMakeLists.txt
A llvm/lib/Target/DirectX/DXILForwardHandleAccesses.cpp
A llvm/lib/Target/DirectX/DXILForwardHandleAccesses.h
M llvm/lib/Target/DirectX/DirectX.h
M llvm/lib/Target/DirectX/DirectXPassRegistry.def
M llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.h
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/lib/Transforms/Coroutines/CoroElide.cpp
M llvm/lib/Transforms/IPO/FunctionSpecialization.cpp
M llvm/lib/Transforms/IPO/PartialInlining.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/lib/Transforms/Scalar/ConstantHoisting.cpp
M llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
M llvm/lib/Transforms/Scalar/LoopDataPrefetch.cpp
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
M llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
M llvm/lib/Transforms/Scalar/NewGVN.cpp
M llvm/lib/Transforms/Scalar/Reassociate.cpp
M llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/lower-neon-vector-fcmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vector-fcmp.mir
M llvm/test/CodeGen/AArch64/arm64-tbl.ll
M llvm/test/CodeGen/AArch64/arm64-zip.ll
M llvm/test/CodeGen/AArch64/fsh.ll
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/select_cc.ll
A llvm/test/CodeGen/AArch64/sme2-intrinsics-mop4-fp8.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
M llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AMDGPU/fpext-free.ll
M llvm/test/CodeGen/AMDGPU/fpow.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/function-args.ll
M llvm/test/CodeGen/AMDGPU/function-returns.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.wave32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/lrint.ll
M llvm/test/CodeGen/AMDGPU/lround.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/strict_fpext.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
M llvm/test/CodeGen/AMDGPU/vector_rebroadcast.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vopc_dpp.mir
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/ARM/popcnt.ll
M llvm/test/CodeGen/AVR/inline-asm/inline-asm-invalid.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/alloca.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/ambiguous.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/buffer-O0.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/cbuffer-access.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/undominated.ll
M llvm/test/CodeGen/DirectX/llc-pipeline.ll
A llvm/test/CodeGen/Hexagon/swp-alias-cross-iteration.mir
A llvm/test/CodeGen/Hexagon/swp-no-alias.mir
A llvm/test/CodeGen/LoongArch/lasx/widen-shuffle-mask.ll
A llvm/test/CodeGen/LoongArch/lsx/widen-shuffle-mask.ll
M llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
A llvm/test/CodeGen/RISCV/pr101786.ll
M llvm/test/CodeGen/RISCV/pr56457.ll
M llvm/test/CodeGen/RISCV/pr95271.ll
M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
M llvm/test/CodeGen/RISCV/sextw-removal.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroup_matrix_multiply_accumulate/subgroup_matrix_multiply_accumulate_generic.ll
M llvm/test/CodeGen/Thumb2/mve-ctpop.ll
M llvm/test/CodeGen/X86/ispow2.ll
A llvm/test/CodeGen/X86/pr94829.ll
M llvm/test/CodeGen/X86/vector-popcnt-128.ll
M llvm/test/CodeGen/X86/vector-popcnt-256-ult-ugt.ll
M llvm/test/CodeGen/X86/vector-popcnt-256.ll
M llvm/test/CodeGen/X86/vector-popcnt-512-ult-ugt.ll
M llvm/test/CodeGen/X86/vector-popcnt-512.ll
A llvm/test/Transforms/CodeGenPrepare/unfold-pow2-test-vec.ll
A llvm/test/Transforms/CodeGenPrepare/unfold-pow2-test.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-binop.ll
A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-shift.ll
M llvm/test/Transforms/InstCombine/and-fcmp.ll
M llvm/test/Transforms/InstCombine/clamp-to-minmax.ll
M llvm/test/Transforms/InstCombine/icmp.ll
A llvm/test/Transforms/InstCombine/max-min-canonicalize.ll
M llvm/test/Transforms/InstCombine/max_known_bits.ll
M llvm/test/Transforms/InstCombine/minmax-fold.ll
M llvm/test/Transforms/InstCombine/minmax-intrinsics.ll
M llvm/test/Transforms/InstCombine/sadd_sat.ll
M llvm/test/Transforms/InstCombine/select-min-max.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-no-dotprod.ll
A llvm/test/Transforms/Reassociate/canonicalize-made-change.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/preserve-inbounds.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep.ll
A llvm/test/tools/llvm-extract/extract-unnamed-bb.ll
M llvm/tools/llvm-extract/llvm-extract.cpp
M llvm/unittests/Support/InstructionCostTest.cpp
M llvm/utils/TableGen/DecoderEmitter.cpp
M llvm/utils/gn/secondary/lldb/source/Plugins/SymbolFile/DWARF/BUILD.gn
M mlir/include/mlir/Dialect/MemRef/Transforms/Passes.h
M mlir/include/mlir/Dialect/MemRef/Transforms/Passes.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaUtilOps.td
M mlir/include/mlir/Dialect/X86Vector/X86Vector.td
M mlir/include/mlir/Dialect/X86Vector/X86VectorDialect.h
M mlir/include/mlir/Dialect/X86Vector/X86VectorInterfaces.td
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Conversion/TosaToMLProgram/TosaToMLProgram.cpp
M mlir/lib/Dialect/Bufferization/Pipelines/BufferizationPipelines.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandRealloc.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
M mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/NormalizeMemRefs.cpp
M mlir/lib/Dialect/MemRef/Transforms/ResolveShapedTypeResultDims.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/lib/Dialect/X86Vector/IR/CMakeLists.txt
M mlir/lib/Dialect/X86Vector/IR/X86VectorDialect.cpp
M mlir/lib/Dialect/X86Vector/Transforms/LegalizeForLLVMExport.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-pipeline.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
M mlir/test/Conversion/TosaToMLProgram/tosa-to-mlprogram.mlir
M mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/level_check.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/profile_pro_fp_unsupported.mlir
M mlir/test/Dialect/Tosa/profile_pro_int_unsupported.mlir
M mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
M mlir/test/Dialect/Tosa/variables.mlir
M mlir/test/Dialect/Tosa/verifier.mlir
M mlir/test/Dialect/X86Vector/legalize-for-llvm.mlir
M mlir/test/Dialect/X86Vector/roundtrip.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/matmul.mlir
M mlir/test/Target/LLVMIR/x86vector.mlir
M mlir/test/python/pass_manager.py
M mlir/utils/generate-test-checks.py
M offload/DeviceRTL/CMakeLists.txt
M offload/DeviceRTL/src/Kernel.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/test/offloading/ompx_bare.c
M offload/test/offloading/ompx_bare_multi_dim.cpp
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6-beta.1
[skip ci]
Commit: 923ffc37b598a407e419363e38b57beb0aaa01df
https://github.com/llvm/llvm-project/commit/923ffc37b598a407e419363e38b57beb0aaa01df
Author: Peter Collingbourne <peter at pcc.me.uk>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M bolt/lib/Core/MCPlusBuilder.cpp
M bolt/unittests/Core/MCPlusBuilder.cpp
M clang-tools-extra/clang-doc/Serialize.cpp
M clang-tools-extra/clangd/InlayHints.cpp
M clang-tools-extra/clangd/InlayHints.h
M clang-tools-extra/clangd/unittests/InlayHintTests.cpp
M clang/docs/ReleaseNotes.rst
M clang/docs/StandardCPlusPlusModules.rst
M clang/include/clang/AST/Type.h
M clang/include/clang/Basic/arm_sme.td
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/Frontend/CompilerInstance.h
M clang/include/clang/Lex/DependencyDirectivesScanner.h
M clang/include/clang/Lex/Preprocessor.h
M clang/include/clang/Lex/PreprocessorOptions.h
M clang/include/clang/Sema/AnalysisBasedWarnings.h
M clang/include/clang/Sema/ScopeInfo.h
M clang/include/clang/Sema/SemaCUDA.h
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningFilesystem.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpState.cpp
M clang/lib/AST/ByteCode/InterpState.h
M clang/lib/AST/ByteCode/PrimType.h
M clang/lib/AST/Type.cpp
M clang/lib/Basic/Targets/AVR.h
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Format/FormatTokenLexer.cpp
M clang/lib/Format/FormatTokenLexer.h
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Frontend/CompilerInstance.cpp
M clang/lib/Lex/PPLexerChange.cpp
M clang/lib/Sema/AnalysisBasedWarnings.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaCUDA.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Serialization/ModuleManager.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
M clang/test/AST/ByteCode/c.c
M clang/test/AST/ByteCode/cxx11.cpp
M clang/test/AST/ByteCode/cxx23.cpp
M clang/test/AST/ByteCode/cxx26.cpp
M clang/test/AST/ByteCode/literals.cpp
A clang/test/Analysis/pragma-diag-control.cpp
M clang/test/CIR/CodeGen/struct.c
M clang/test/CIR/CodeGen/struct.cpp
M clang/test/CIR/CodeGen/typedef.c
M clang/test/CIR/CodeGen/union.c
M clang/test/CIR/CodeGenOpenACC/data.c
M clang/test/CIR/IR/struct.cir
A clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
M clang/test/CodeGen/avr/avr-inline-asm-constraints.c
M clang/test/CodeGen/avr/avr-unsupported-inline-asm-constraints.c
A clang/test/CodeGenCUDA/lambda-constexpr-capture.cu
M clang/test/Driver/Xclangas.s
M clang/test/Driver/cxa-atexit.cpp
M clang/test/Driver/riscv-cpus.c
M clang/test/Misc/target-invalid-cpu-note/riscv.c
M clang/test/Modules/explicit-build.cpp
A clang/test/Sema/aarch64-sme2p2-instrinsics/acle_sme2p2_fp8_imm.cpp
M clang/test/SemaOpenACC/data-construct-async-clause.c
M clang/tools/libclang/CIndex.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/FormatTestJS.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M clang/unittests/Lex/PPDependencyDirectivesTest.cpp
M clang/unittests/libclang/LibclangTest.cpp
M flang/examples/FeatureList/FeatureList.cpp
M flang/include/flang/Lower/DirectivesCommon.h
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Semantics/symbol.h
M flang/include/flang/Support/Fortran.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Optimizer/CodeGen/TargetRewrite.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/rewrite-directives.cpp
M flang/test/Fir/CUDA/cuda-target-rewrite.mlir
M flang/test/Semantics/OpenACC/acc-data.f90
M libc/src/math/generic/expm1f.cpp
M libc/src/stdio/printf_core/core_structs.h
M libclc/CMakeLists.txt
M libclc/generic/include/clc/image/image.h
M libcxxabi/test/test_demangle.pass.cpp
M lldb/source/Core/Debugger.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxInitializerList.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxSpan.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxVariant.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxVector.cpp
M lldb/source/Plugins/SymbolFile/DWARF/CMakeLists.txt
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.h
A lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndexSet.cpp
A lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndexSet.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
M lldb/test/API/functionalities/statusline/TestStatusline.py
R lldb/test/Shell/SymbolFile/DWARF/range-lower-then-low-pc.s
M lldb/test/Shell/SymbolFile/DWARF/x86/discontinuous-inline-function.s
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/Handler/CancelRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/DisconnectRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/NextRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
M lldb/tools/lldb-dap/Protocol/ProtocolBase.h
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
M lldb/tools/lldb-dap/Transport.cpp
M lldb/unittests/SymbolFile/DWARF/DWARFIndexCachingTest.cpp
M llvm/docs/ReleaseNotes.md
M llvm/docs/SPIRVUsage.rst
M llvm/include/llvm/Analysis/DXILResource.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/MachinePipeliner.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/Frontend/OpenACC/ACC.td
M llvm/include/llvm/Frontend/OpenMP/OMPDeviceConstants.h
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/include/llvm/IR/RuntimeLibcalls.def
M llvm/include/llvm/IR/Value.h
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/include/llvm/Support/InstructionCost.h
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/include/llvm/Transforms/Utils/UnrollLoop.h
M llvm/lib/Analysis/CostModel.cpp
M llvm/lib/Analysis/InlineSizeEstimatorAnalysis.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/CodeGen/LiveRangeShrink.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/PrologEpilogInserter.cpp
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/Value.cpp
M llvm/lib/ProfileData/InstrProf.cpp
M llvm/lib/ProfileData/InstrProfWriter.cpp
M llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrGISel.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/BPF/BPFISelLowering.h
M llvm/lib/Target/DirectX/CMakeLists.txt
A llvm/lib/Target/DirectX/DXILForwardHandleAccesses.cpp
A llvm/lib/Target/DirectX/DXILForwardHandleAccesses.h
M llvm/lib/Target/DirectX/DirectX.h
M llvm/lib/Target/DirectX/DirectXPassRegistry.def
M llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.h
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/lib/Transforms/Coroutines/CoroElide.cpp
M llvm/lib/Transforms/IPO/FunctionSpecialization.cpp
M llvm/lib/Transforms/IPO/PartialInlining.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/lib/Transforms/Scalar/ConstantHoisting.cpp
M llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
M llvm/lib/Transforms/Scalar/LoopDataPrefetch.cpp
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
M llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
M llvm/lib/Transforms/Scalar/NewGVN.cpp
M llvm/lib/Transforms/Scalar/Reassociate.cpp
M llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/lower-neon-vector-fcmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vector-fcmp.mir
M llvm/test/CodeGen/AArch64/arm64-tbl.ll
M llvm/test/CodeGen/AArch64/arm64-zip.ll
M llvm/test/CodeGen/AArch64/fsh.ll
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/select_cc.ll
A llvm/test/CodeGen/AArch64/sme2-intrinsics-mop4-fp8.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
M llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AMDGPU/fpext-free.ll
M llvm/test/CodeGen/AMDGPU/fpow.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/function-args.ll
M llvm/test/CodeGen/AMDGPU/function-returns.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.wave32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/lrint.ll
M llvm/test/CodeGen/AMDGPU/lround.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/strict_fpext.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
M llvm/test/CodeGen/AMDGPU/vector_rebroadcast.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vopc_dpp.mir
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/ARM/popcnt.ll
M llvm/test/CodeGen/AVR/inline-asm/inline-asm-invalid.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/alloca.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/ambiguous.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/buffer-O0.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/cbuffer-access.ll
A llvm/test/CodeGen/DirectX/ForwardHandleAccesses/undominated.ll
M llvm/test/CodeGen/DirectX/llc-pipeline.ll
A llvm/test/CodeGen/Hexagon/swp-alias-cross-iteration.mir
A llvm/test/CodeGen/Hexagon/swp-no-alias.mir
A llvm/test/CodeGen/LoongArch/lasx/widen-shuffle-mask.ll
A llvm/test/CodeGen/LoongArch/lsx/widen-shuffle-mask.ll
M llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
A llvm/test/CodeGen/RISCV/pr101786.ll
M llvm/test/CodeGen/RISCV/pr56457.ll
M llvm/test/CodeGen/RISCV/pr95271.ll
M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
M llvm/test/CodeGen/RISCV/sextw-removal.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroup_matrix_multiply_accumulate/subgroup_matrix_multiply_accumulate_generic.ll
M llvm/test/CodeGen/Thumb2/mve-ctpop.ll
M llvm/test/CodeGen/X86/ispow2.ll
A llvm/test/CodeGen/X86/pr94829.ll
M llvm/test/CodeGen/X86/vector-popcnt-128.ll
M llvm/test/CodeGen/X86/vector-popcnt-256-ult-ugt.ll
M llvm/test/CodeGen/X86/vector-popcnt-256.ll
M llvm/test/CodeGen/X86/vector-popcnt-512-ult-ugt.ll
M llvm/test/CodeGen/X86/vector-popcnt-512.ll
A llvm/test/Transforms/CodeGenPrepare/unfold-pow2-test-vec.ll
A llvm/test/Transforms/CodeGenPrepare/unfold-pow2-test.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-binop.ll
A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-shift.ll
M llvm/test/Transforms/InstCombine/and-fcmp.ll
M llvm/test/Transforms/InstCombine/clamp-to-minmax.ll
M llvm/test/Transforms/InstCombine/icmp.ll
A llvm/test/Transforms/InstCombine/max-min-canonicalize.ll
M llvm/test/Transforms/InstCombine/max_known_bits.ll
M llvm/test/Transforms/InstCombine/minmax-fold.ll
M llvm/test/Transforms/InstCombine/minmax-intrinsics.ll
M llvm/test/Transforms/InstCombine/sadd_sat.ll
M llvm/test/Transforms/InstCombine/select-min-max.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-no-dotprod.ll
A llvm/test/Transforms/Reassociate/canonicalize-made-change.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/preserve-inbounds.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep.ll
A llvm/test/tools/llvm-extract/extract-unnamed-bb.ll
M llvm/tools/llvm-extract/llvm-extract.cpp
M llvm/unittests/Support/InstructionCostTest.cpp
M llvm/utils/TableGen/DecoderEmitter.cpp
M llvm/utils/gn/secondary/lldb/source/Plugins/SymbolFile/DWARF/BUILD.gn
M mlir/include/mlir/Dialect/MemRef/Transforms/Passes.h
M mlir/include/mlir/Dialect/MemRef/Transforms/Passes.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaUtilOps.td
M mlir/include/mlir/Dialect/X86Vector/X86Vector.td
M mlir/include/mlir/Dialect/X86Vector/X86VectorDialect.h
M mlir/include/mlir/Dialect/X86Vector/X86VectorInterfaces.td
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Conversion/TosaToMLProgram/TosaToMLProgram.cpp
M mlir/lib/Dialect/Bufferization/Pipelines/BufferizationPipelines.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandRealloc.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
M mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/NormalizeMemRefs.cpp
M mlir/lib/Dialect/MemRef/Transforms/ResolveShapedTypeResultDims.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/lib/Dialect/X86Vector/IR/CMakeLists.txt
M mlir/lib/Dialect/X86Vector/IR/X86VectorDialect.cpp
M mlir/lib/Dialect/X86Vector/Transforms/LegalizeForLLVMExport.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-pipeline.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
M mlir/test/Conversion/TosaToMLProgram/tosa-to-mlprogram.mlir
M mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/level_check.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/profile_pro_fp_unsupported.mlir
M mlir/test/Dialect/Tosa/profile_pro_int_unsupported.mlir
M mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
M mlir/test/Dialect/Tosa/variables.mlir
M mlir/test/Dialect/Tosa/verifier.mlir
M mlir/test/Dialect/X86Vector/legalize-for-llvm.mlir
M mlir/test/Dialect/X86Vector/roundtrip.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/matmul.mlir
M mlir/test/Target/LLVMIR/x86vector.mlir
M mlir/test/python/pass_manager.py
M mlir/utils/generate-test-checks.py
M offload/DeviceRTL/CMakeLists.txt
M offload/DeviceRTL/src/Kernel.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/test/offloading/ompx_bare.c
M offload/test/offloading/ompx_bare_multi_dim.cpp
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Address comments
Created using spr 1.3.6-beta.1
Compare: https://github.com/llvm/llvm-project/compare/b9cf38392ec4...923ffc37b598
To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications
More information about the All-commits
mailing list