[all-commits] [llvm/llvm-project] 6388a7: [RISCV] Check the extension type for atomic loads ...
Craig Topper via All-commits
all-commits at lists.llvm.org
Wed Apr 23 15:55:50 PDT 2025
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 6388a7acf7e31fdc7b9c168bd6ce0f4d25c98cd0
https://github.com/llvm/llvm-project/commit/6388a7acf7e31fdc7b9c168bd6ce0f4d25c98cd0
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-04-23 (Wed, 23 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
Log Message:
-----------
[RISCV] Check the extension type for atomic loads in isel patterns. (#137019)
Previously we ignored the extension type and only used the memory type.
The extension type on RISC-V today can only be nonextload, extload, or
sextload. It is ok to treat extload as the same as sextload so ignoring
the extension type is fine.
For #136502, we want to support zextload as well so we will need to
disambiguate based on the extension type.
I wanted to use IsAtomic/IsZeroExtLoad/IsSignExtLoad/IsAnyExtLoad flags
from PatFrags to autogenerate the predicates, but those aren't hooked up
properly in tablegen for ISD::ATOMIC_LOAD. Fixing that will impact other
targets as almost all of them also ignore the extension type.
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