[all-commits] [llvm/llvm-project] a1f369: [AArch64][SVE] Add dot product lowering for PARTIA...

[Nicholas Guy via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a1f369e6309c8c6adaae886afc55817b97953641
      https://github.com/llvm/llvm-project/commit/a1f369e6309c8c6adaae886afc55817b97953641
  Author: Nicholas Guy <nicholas.guy at arm.com>
  Date:   2025-04-23 (Wed, 23 Apr 2025)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/include/llvm/Target/TargetSelectionDAG.td
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
    M llvm/lib/CodeGen/TargetLoweringBase.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
    M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll

  Log Message:
  -----------
  [AArch64][SVE] Add dot product lowering for PARTIAL_REDUCE_MLA node (#130933)

Add lowering in tablegen for PARTIAL_REDUCE_U/SMLA ISD nodes. Only
happens when the combine has been performed on the ISD node. Also adds
in check to only do the DAG combine when the node can then eventually be
lowered, so changes neon tests too.

---------

Co-authored-by: James Chesterman <james.chesterman at arm.com>



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