[all-commits] [llvm/llvm-project] 717efc: [RISCV] Support disjoint RISCVISD::OR_VL in combin...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 717efc0a994dfc5b2ed65ddb13b47fb917c9a467
      https://github.com/llvm/llvm-project/commit/717efc0a994dfc5b2ed65ddb13b47fb917c9a467
  Author: Luke Lau <luke at igalia.com>
  Date:   2025-04-23 (Wed, 23 Apr 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll

  Log Message:
  -----------
  [RISCV] Support disjoint RISCVISD::OR_VL in combineOp_VLToVWOp_VL (#136820)

This handles combining fixed-length disjoint ors to vwadd[u].wv, as was
done for scalable vectors in #86929.

vwadd[u].vv patterns need to be handled separately with a pattern in a
separate patch due to the extends being sunk, see #136716.



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