[all-commits] [llvm/llvm-project] 820493: [RISCV] Add disjoint or patterns for vwadd[u].v{v, ...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 82049310385d5222527cf7d12984bd8d4f955dd1
      https://github.com/llvm/llvm-project/commit/82049310385d5222527cf7d12984bd8d4f955dd1
  Author: Luke Lau <luke at igalia.com>
  Date:   2025-04-23 (Wed, 23 Apr 2025)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll

  Log Message:
  -----------
  [RISCV] Add disjoint or patterns for vwadd[u].v{v,x} (#136716)

DAGCombiner::hoistLogicOpWithSameOpcodeHands will hoist

(or disjoint (ext a), (ext b)) -> (ext (or disjoint a, b))

So this adds patterns to match vwadd[u].v{v,x} in this case.

We have to teach the combine to preserve the disjoint flag.



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