[all-commits] [llvm/llvm-project] 832ca7: [RISCV] Add Andes N45/NX45 processor definition (#...

[Jim Lin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 832ca744f2f25a7a5334f2f04380c84e41f71678
      https://github.com/llvm/llvm-project/commit/832ca744f2f25a7a5334f2f04380c84e41f71678
  Author: Jim Lin <jim at andestech.com>
  Date:   2025-04-23 (Wed, 23 Apr 2025)

  Changed paths:
    M clang/test/Driver/riscv-cpus.c
    M clang/test/Misc/target-invalid-cpu-note/riscv.c
    M llvm/docs/ReleaseNotes.md
    M llvm/lib/Target/RISCV/RISCVProcessors.td

  Log Message:
  -----------
  [RISCV] Add Andes N45/NX45 processor definition (#136670)

Andes N45/NX45 are 32/64bit in-order dual-issue 8-stage pipeline CPU
architecture implementing the RV[32|64]IMAFDC_Zba_Zbb_Zbs ISA
extensions. They are developed by Andes Technology
https://www.andestech.com, a RISC-V IP provider.

The overviews for N45/NX45:
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-n45/
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-nx45/

Scheduling model will be implemented in a later PR.



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