[all-commits] [llvm/llvm-project] 4dbf67: [RISCV] Lower SEW<=32 vector_deinterleave(2) via v...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4dbf67de4050cad3371706b991eb9e3cd9d39482
      https://github.com/llvm/llvm-project/commit/4dbf67de4050cad3371706b991eb9e3cd9d39482
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2025-04-22 (Tue, 22 Apr 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll

  Log Message:
  -----------
  [RISCV] Lower SEW<=32 vector_deinterleave(2) via vunzip2{a,b} (#136463)

This is a continuation from 22d5890c and adds the neccessary logic to
handle SEW!=64 profitably. The interesting case is needing to handle
e.g. a single m1 which is split via extract_subvector into two operands,
and form that back into a single m1 operation - instead of letting the
vslidedown by vlenb/Constant sequence be generated. This is analogous to
the getSingleShuffleSrc for vnsrl, and we can share a bunch of code.



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