[all-commits] [llvm/llvm-project] 4c0ea4: [RISCV] Report error if Zilsd is used on RV64. (#1...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Tue Apr 22 09:06:24 PDT 2025
Branch: refs/heads/users/alexey-bataev/spr/slpprefer-segmeneteddeinterleaved-loads-to-strided-and-fix-codegen
Home: https://github.com/llvm/llvm-project
Commit: 4c0ea476c40f7e426c84c37aaf5787aa80fb5e3b
https://github.com/llvm/llvm-project/commit/4c0ea476c40f7e426c84c37aaf5787aa80fb5e3b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Report error if Zilsd is used on RV64. (#136577)
Fixes #136564.
Commit: 9968ba8652b8a2936858a1a307207a9c8690ee5c
https://github.com/llvm/llvm-project/commit/9968ba8652b8a2936858a1a307207a9c8690ee5c
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/add64-low-32-bits-known-zero.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/constrained-shift.ll
M llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll
M llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/ptrmask.ll
M llvm/test/CodeGen/AMDGPU/sdag-print-divergence.ll
M llvm/test/CodeGen/AMDGPU/sub64-low-32-bits-known-zero.ll
R llvm/test/CodeGen/AMDGPU/uniform-vgpr-to-sgpr-return.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
Log Message:
-----------
Revert "[AMDGPU] Insert readfirstlane in the function returns in sgpr. (#135326)"
This reverts commit 76ced7fa782f0d7db9efea871fa6de74706dd9cc since it breaks a
lot of bots.
Commit: c873ca25976d81f54421d9f4e24c5f700824d0d1
https://github.com/llvm/llvm-project/commit/c873ca25976d81f54421d9f4e24c5f700824d0d1
Author: royitaqi <royitaqi at users.noreply.github.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M lldb/include/lldb/Target/Statistics.h
M lldb/source/Target/Statistics.cpp
M lldb/test/API/commands/statistics/basic/TestStats.py
Log Message:
-----------
[lldb] Add symbol/table count into statistics (#136226)
# New stats
The following stats are added and are available in both "statistics
dump" command and in python API.
1. In summary:
1. Add `totalSymbolsLoaded`. The total number of symbols loaded in all
modules.
2. Add `totalSymbolTablesLoaded `. The total number symbol tables loaded
in all modules.
2. In each module's stats:
1. Add `symbolsLoaded`. The number of symbols loaded in the current
module.
# Example
Example `statistics dump` output:
```
(lldb) statistics dump
{
...,
"modules": [
{
"path": "/Users/<username>/demo/simple/a.out",
"symbolsLoaded": 6,
...
},
...
],
...
"totalSymbolTablesLoaded": 42,
"totalSymbolsLoaded": 32198
}
```
# Tests
**Manual test**: Built and ran lldb on a helloworld program. Ran
`statistics dump`. Verified the above stats.
**Unit test**: Ran the following tests:
```
$ bin/lldb-dotest -p TestStats.py ~/llvm-sand/external/llvm-project/lldb/test/API/commands/statistics/basic/
...
Ran 18 tests in 192.676s
OK (skipped=3)
```
Commit: e0c1e23b99e9719d0a01ab7dfc0807d891004bd4
https://github.com/llvm/llvm-project/commit/e0c1e23b99e9719d0a01ab7dfc0807d891004bd4
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
M llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/BPF/BPFTargetTransformInfo.h
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
M llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
Log Message:
-----------
[TTI] Constify BasicTTIImplBase::thisT() (NFCI) (#136575)
The main change is making `thisT` method `const`, the rest of the
changes is fixing compilation errors (*).
(*) There are two tricky methods, `getVectorInstrCost()` and
`getIntImmCost()`.
They have several overloads; some of these overloads are typically
pulled in to derived classes using the `using` directive, and then
hidden by methods in the derived class.
The compiler does not complain if the hiding methods are not marked as
`const`, which means that clients will use the methods from the base
class. If after this change your target fails cost model tests, this
must be the reason. To resolve the issue you need to make all hiding
overloads `const`. See the second commit in this PR.
Pull Request: https://github.com/llvm/llvm-project/pull/136575
Commit: 0ae9dac262afccea1e1a2e02520f737ab38b286c
https://github.com/llvm/llvm-project/commit/0ae9dac262afccea1e1a2e02520f737ab38b286c
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M clang/test/CIR/CodeGenOpenACC/kernels.c
M clang/test/CIR/CodeGenOpenACC/parallel.c
Log Message:
-----------
[OpenACC][CIR] Lower 'num_workers' for parallel/kernels (#136578)
This patch also includes the first one to handle 'device_type' properly,
which is where most of the 'challenge' here comes from.
>From the best I can tell: we must keep two lists of the same size, 1 of
all of the 'num_workers' items, and 1 of the 'device_type' value for
that 'num_workers'. Additionally, the 'device_type' list can only handle
single 'device_type' values, so we have to duplicate the 'num_workers'
items in cases where there are multiple applicable 'device_type' values.
This patch accomplishes this by keeping the two in sync, and saving the
current 'device_type' in the visitor.
Commit: 4b98955680e0aad33cad0e810f1daaa8bc7c0a23
https://github.com/llvm/llvm-project/commit/4b98955680e0aad33cad0e810f1daaa8bc7c0a23
Author: erichkeane <ekeane at nvidia.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
Log Message:
-----------
Fix capitalization re review from 0ae9dac
Commit: 99e4b3927c5b8700b818ca2436f3c8394245e97c
https://github.com/llvm/llvm-project/commit/99e4b3927c5b8700b818ca2436f3c8394245e97c
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/include/llvm/Analysis/LazyBlockFrequencyInfo.h
M llvm/include/llvm/InitializePasses.h
M llvm/lib/Analysis/AliasAnalysis.cpp
M llvm/lib/Analysis/Analysis.cpp
M llvm/lib/Analysis/AssumptionCache.cpp
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/BlockFrequencyInfo.cpp
M llvm/lib/Analysis/BranchProbabilityInfo.cpp
M llvm/lib/Analysis/CallGraph.cpp
M llvm/lib/Analysis/CycleAnalysis.cpp
M llvm/lib/Analysis/DXILMetadataAnalysis.cpp
M llvm/lib/Analysis/DXILResource.cpp
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/lib/Analysis/DomPrinter.cpp
M llvm/lib/Analysis/DominanceFrontier.cpp
M llvm/lib/Analysis/GlobalsModRef.cpp
M llvm/lib/Analysis/IRSimilarityIdentifier.cpp
M llvm/lib/Analysis/IVUsers.cpp
M llvm/lib/Analysis/LazyBlockFrequencyInfo.cpp
M llvm/lib/Analysis/LazyValueInfo.cpp
M llvm/lib/Analysis/LoopInfo.cpp
M llvm/lib/Analysis/LoopPass.cpp
M llvm/lib/Analysis/MemoryDependenceAnalysis.cpp
M llvm/lib/Analysis/MemorySSA.cpp
M llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
M llvm/lib/Analysis/OptimizationRemarkEmitter.cpp
M llvm/lib/Analysis/PhiValues.cpp
M llvm/lib/Analysis/PostDominators.cpp
M llvm/lib/Analysis/ProfileSummaryInfo.cpp
M llvm/lib/Analysis/RegionInfo.cpp
M llvm/lib/Analysis/RegionPrinter.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp
M llvm/lib/Analysis/ScopedNoAliasAA.cpp
M llvm/lib/Analysis/StackSafetyAnalysis.cpp
M llvm/lib/Analysis/StaticDataProfileInfo.cpp
M llvm/lib/Analysis/TargetLibraryInfo.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/TypeBasedAliasAnalysis.cpp
M llvm/lib/Analysis/UniformityAnalysis.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
Log Message:
-----------
[LLVM] Cleanup pass initialization for Analysis passes (#135858)
- Do not call pass initialization from pass constructors.
- Instead, pass initialization should happen in the `initializeAnalysis`
function.
- https://github.com/llvm/llvm-project/issues/111767
Commit: b7c521b922f8b81544ecb0ccff2847644cac3107
https://github.com/llvm/llvm-project/commit/b7c521b922f8b81544ecb0ccff2847644cac3107
Author: erichkeane <ekeane at nvidia.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M clang/test/CIR/CodeGenOpenACC/kernels.c
M clang/test/CIR/CodeGenOpenACC/parallel.c
Log Message:
-----------
[OpenACC][CIR] Lowering for 'vector_length' on compute constructs
This is the same as the 'num_workers', with slightly different names in
places, so we just do the same exact implementation. This extracts the
implementation as well, which should make it easier to reuse.
Commit: 1b4919d0824411ab1a4fb055b22532fd466541f7
https://github.com/llvm/llvm-project/commit/1b4919d0824411ab1a4fb055b22532fd466541f7
Author: Nico Weber <thakis at chromium.org>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/AArch64/Disassembler/BUILD.gn
Log Message:
-----------
[gn] port e1bb7f6ddec375
Commit: 8c83355d5baa6ecbb5884240df195826380ed952
https://github.com/llvm/llvm-project/commit/8c83355d5baa6ecbb5884240df195826380ed952
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Handle VPIRPhi in VPRecipeBase::isPhi (NFC).
Also handle VPIRPhi in VPRecipeBase::isPhi, to simplify existing code
dealing with VPIRPhis.
Suggested as part of https://github.com/llvm/llvm-project/pull/136455.
Commit: c1049e42a1beab9b240cec80418b3ce32c9da03e
https://github.com/llvm/llvm-project/commit/c1049e42a1beab9b240cec80418b3ce32c9da03e
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
Log Message:
-----------
[AMDGPU] Correct VOP3P encoding. NFC. (#136005)
VOP3P encoding field was defined as 9 bit in GFX8/GFX9 and opcode
was 7 bit, while it is 8 and 8 since GFX10. There are no changes
to instructions, but it fixes difference with SP3 in terms of
fields breakdown.
Commit: 56bf0e720288ae6ba6e8635c7ec12f1e7d6f783b
https://github.com/llvm/llvm-project/commit/56bf0e720288ae6ba6e8635c7ec12f1e7d6f783b
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M offload/DeviceRTL/CMakeLists.txt
M offload/DeviceRTL/src/Kernel.cpp
M offload/DeviceRTL/src/Mapping.cpp
M offload/include/Shared/Environment.h
Log Message:
-----------
[OpenMP] Remove dependency on LLVM include directory from DeviceRTL (#136359)
Summary:
Currently we depend on a single LLVM include directory. This is actually
only required to define one enum, which is highly unlikely to change.
THis patch makes the `Environment.h` include directory more hermetic so
we no long depend on other libraries. In exchange, we get a simpler
dependency list for the price of hard-coding `1` somewhere. I think it's
a valid trade considering that this flag is highly unlikely to change at
this point.
@ronlieb AMD version
https://gist.github.com/jhuber6/3313e6f957be14dc79fe85e5126d2cb3
Commit: 863ead29e92de800fe50e56958b6eba6ede023e9
https://github.com/llvm/llvm-project/commit/863ead29e92de800fe50e56958b6eba6ede023e9
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
A utils/bazel/llvm-project-overlay/libc/test/include/BUILD.bazel
Log Message:
-----------
[libc][bazel] Add a helper library with all deps of generated headers. (#136582)
Create "public_header_deps" that is a convenient way to express
dependencies of a generated headers as a single (and same) target. It's
also convenient to use it in unit tests - which is also demonstrated in
this PR by adding the BUILD.bazel placeholder for test/include unit
tests, and creating a libc_test target for one of these tests.
See issue #134780.
Commit: 704fc6542cf171c603bd387663a2de3a3fa9c4ff
https://github.com/llvm/llvm-project/commit/704fc6542cf171c603bd387663a2de3a3fa9c4ff
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Log Message:
-----------
[SelectionDAG] Prefer to use ATOMIC_LOAD extension type over getExtendForAtomicOps() in computeKnownBits/ComputeNumSignBits. (#136600)
If an ATOMIC_LOAD has ZEXTLOAD/SEXTLOAD extension type we should trust
that over getExtendForAtomicOps().
SystemZ is the only target that uses setAtomicLoadExtAction and they
return ANY_EXTEND from getExtendForAtomicOps(). So I'm not sure there's
a way to get a contradiction currently.
Note, type legalization uses getExtendForAtomicOps() when promoting
ATOMIC_LOAD so we may not need to check getExtendForAtomicOps() for
ATOMIC_LOAD. I have not done much investigating of this.
Commit: aa5cdc0600ac8157a80f54fa2555ae7dfd5fc520
https://github.com/llvm/llvm-project/commit/aa5cdc0600ac8157a80f54fa2555ae7dfd5fc520
Author: Thurston Dang <thurston at google.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
A llvm/test/Instrumentation/MemorySanitizer/X86/avx512fp16-arith-intrinsics.ll
A llvm/test/Instrumentation/MemorySanitizer/X86/avx512fp16-arith-vl-intrinsics.ll
A llvm/test/Instrumentation/MemorySanitizer/X86/avx512fp16-intrinsics.ll
Log Message:
-----------
[msan][NFCI] Add avx512fp16-{arith-intrinsics, arith-vl-intrinsics, intrinsics} tests (#136260)
Forked from llvm/test/CodeGen/X86/avx512fp16-{arith-intrinsics,
arith-vl-intrinsics, intrinsics}.ll
The tests show that many instructions are handled suboptimally or
heuristically, but this commit message is too narrow to contain them.
Commit: 1e803770a5a0d7e5a12511f6d505b779a1931724
https://github.com/llvm/llvm-project/commit/1e803770a5a0d7e5a12511f6d505b779a1931724
Author: lexi-nadia <me at lexibromfield.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/python/BUILD.bazel
Log Message:
-----------
[mlir][SMT] update Bazel configuration to match 697aa99 (#136616)
Update Bazel configuration to match
697aa9995c24a977425e672d76a4a434384b16e3.
Commit: a27f7ac5c4e44b495f52e8d77b68a164dd833fda
https://github.com/llvm/llvm-project/commit/a27f7ac5c4e44b495f52e8d77b68a164dd833fda
Author: gulfemsavrun <gulfem at google.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M clang/cmake/caches/Fuchsia-stage2.cmake
Log Message:
-----------
Revert "[Fuchsia] Disable PIC" (#136617)
Reverts llvm/llvm-project#136376 because it broke Fuchsia Clang
toolchain builders.
Commit: a945f5917cb01350487999b24b068e18111bfbfe
https://github.com/llvm/llvm-project/commit/a945f5917cb01350487999b24b068e18111bfbfe
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
R llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.fpmath.ll
A llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.path.ll
Log Message:
-----------
AMDGPU: Add global-isel checks and rename fptrunc.v2f16.fpmath.ll (#136609)
Also remove the checks with -enable-unsafe-fp-math (already in fptrunc.f16.ll)
Commit: 3ceb3d96ff166305f015f1f00b2740e148347532
https://github.com/llvm/llvm-project/commit/3ceb3d96ff166305f015f1f00b2740e148347532
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M flang/lib/Semantics/check-acc-structure.cpp
M flang/test/Semantics/OpenACC/acc-kernels.f90
M flang/test/Semantics/OpenACC/acc-parallel.f90
M flang/test/Semantics/OpenACC/acc-serial.f90
M llvm/include/llvm/Frontend/OpenACC/ACC.td
Log Message:
-----------
[flang][openacc] Make async clause behavior homogenous (#136610)
The `async` clause was not handed in a similar way on `serial`,
`parallel` and `kernels` directive. This patches updates the `ACC.td`
file and the flang semantic to make it homogenous.
Commit: 515564aa6ebeadc06eea03ff92aeda64727f1da5
https://github.com/llvm/llvm-project/commit/515564aa6ebeadc06eea03ff92aeda64727f1da5
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
Log Message:
-----------
[AMDGPU] Partially revert my llvm::less_second patch (#136615)
This patch partially reverts:
commit 5e1b0f97735083b6762834b83fdbb35e76002e03
Author: Kazu Hirata <kazu at google.com>
Date: Fri Apr 18 10:05:55 2025 -0700
to fix:
LLVM :: CodeGen/AMDGPU/sched-group-barrier-pipeline-solver.mir
LLVM :: CodeGen/AMDGPU/sched-group-barrier-pre-RA.mir
under LLVM_ENABLE_EXPENSIVE_CHECKS.
Commit: de0153da325b21340747d8a064906a8c1c2f95ea
https://github.com/llvm/llvm-project/commit/de0153da325b21340747d8a064906a8c1c2f95ea
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinHeaders.def
M clang/include/clang/Basic/BuiltinsAArch64.def
M clang/include/clang/Basic/BuiltinsARM.def
M clang/lib/Headers/arm_acle.h
M clang/lib/Sema/SemaARM.cpp
A clang/test/CodeGen/arm-former-microsoft-intrinsics-header-warning.c
A clang/test/CodeGen/arm-former-microsoft-intrinsics.c
M clang/test/CodeGen/arm-microsoft-intrinsics.c
A clang/test/CodeGen/arm64-former-microsoft-intrinsics-header-warning.c
A clang/test/CodeGen/arm64-former-microsoft-intrinsics.c
M clang/test/CodeGen/arm64-microsoft-intrinsics.c
M clang/test/CodeGen/builtins-arm-microsoft.c
M clang/test/Headers/Inputs/include/stdint.h
M clang/test/Headers/ms-intrin.cpp
Log Message:
-----------
[clang][ARM][AArch64] Define intrinsics guarded by __has_builtin on all platforms (#128222)
Instead of defining ARM ACLE intrinsics only on MSVC and guarding
wrapper functions in headers with `__has_builtin`, universally define
the intrinsics as target header builtins.
---------
Signed-off-by: Sarnie, Nick <nick.sarnie at intel.com>
Commit: 7810d8484413ae64029c93f8dfc43f77b0ba98c3
https://github.com/llvm/llvm-project/commit/7810d8484413ae64029c93f8dfc43f77b0ba98c3
Author: Sarah Spall <sarahspall at microsoft.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M clang/lib/CodeGen/Targets/DirectX.cpp
M clang/test/CodeGenHLSL/builtins/AppendStructuredBuffer-elementtype.hlsl
M clang/test/CodeGenHLSL/builtins/ConsumeStructuredBuffer-elementtype.hlsl
M clang/test/CodeGenHLSL/builtins/RWStructuredBuffer-elementtype.hlsl
M clang/test/CodeGenHLSL/builtins/StructuredBuffer-elementtype.hlsl
Log Message:
-----------
[HLSL] Boolean in a RawBuffer should be i32 and Boolean vector in a RawBuffer should be <N x i32> (#135848)
Instead of converting the type in a RawBuffer to its HLSL type using
'ConvertType', use 'ConvertTypeForMem'.
ConvertTypeForMem handles booleans being i32 and boolean vectors being <
N x i32 >.
Add tests to show booleans and boolean vectors in RawBuffers now have
the correct type of i32, and <N x i32> respectively.
Closes #135635
Commit: 8389d6fad76bd880f02bddce7f0f2612ff0afc40
https://github.com/llvm/llvm-project/commit/8389d6fad76bd880f02bddce7f0f2612ff0afc40
Author: Pranav Kant <prka at google.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M lld/ELF/ICF.cpp
M lld/ELF/SymbolTable.cpp
M lld/ELF/SymbolTable.h
A lld/test/ELF/aarch64-got-merging-icf.s
M lld/test/ELF/icf-preemptible.s
Log Message:
-----------
[lld] Merge equivalent symbols found during ICF (#134342)
Fixes a correctness issue for AArch64 when ADRP and LDR instructions are
outlined in separate sections and sections are fed to ICF for
deduplication.
See test case (based on
https://github.com/llvm/llvm-project/issues/129122) for details. All
rodata.* sections are folded into a single section with ICF. This leads
to all f2_* function sections getting folded into one (as their
relocation target symbols g* belong to .rodata.g* sections that have
already been folded into one). Since relocations still refer original g*
symbols, we end up creating duplicate GOT entry for all such symbols.
This PR addresses that by tracking such folded symbols and create one
GOT entry for all such symbols.
Fixes https://github.com/llvm/llvm-project/issues/129122
Co-authored by: @jyknight
Commit: 92c0b425ad4ca7f4c9b8f7f663e6e64d1e070353
https://github.com/llvm/llvm-project/commit/92c0b425ad4ca7f4c9b8f7f663e6e64d1e070353
Author: Princeton Ferro <pferro at nvidia.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
A llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
Log Message:
-----------
[NVPTX] add test case for vector reduction intrinsics (#136381)
Test how these intrinsics are handled by the NVPTX backend. Currently, these intrinsics are lowered to sequential reductions by the ExpandReductions pass.
Commit: 6d765e1c916aba7a038f5ace963001fca4fc9314
https://github.com/llvm/llvm-project/commit/6d765e1c916aba7a038f5ace963001fca4fc9314
Author: Owen Anderson <resistor at mac.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang-tools-extra/clangd/unittests/InlayHintTests.cpp
M clang/lib/AST/Decl.cpp
M clang/unittests/AST/AttrTest.cpp
Log Message:
-----------
Reapply 19c708c "FunctionDecl::getFunctionTypeLoc: ignore function type attributes (#118420)" (#136484)
Avoid using PreservesMost in the testcase as it is not supported on all
targets.
Original PR #118290.
Co-authored-by: Robert Dazi <14996868+v01dXYZ at users.noreply.github.com>
Co-authored-by: v01dxyz <v01dxyz at v01d.xyz>
Commit: 3ca2fa704e149ca22bd9739101ee7d5c498eb1a6
https://github.com/llvm/llvm-project/commit/3ca2fa704e149ca22bd9739101ee7d5c498eb1a6
Author: Theo de Magalhaes <theodemagalhaes at icloud.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M clang/lib/AST/RecordLayoutBuilder.cpp
M clang/test/SemaCXX/windows-Wpadded-bitfield.cpp
Log Message:
-----------
[CLANG][MS-STRUCT] bitfield padding warning presents padding to exact bit count (#136062)
Aims to fix #131647.
Commit: c40d3a411ce3f0a35ae4f3d2f0e1e7df45673856
https://github.com/llvm/llvm-project/commit/c40d3a411ce3f0a35ae4f3d2f0e1e7df45673856
Author: Maryam Moghadas <maryammo at ca.ibm.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsPowerPC.td
M llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
M llvm/test/CodeGen/PowerPC/dmf-outer-product.ll
M llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
M llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
M llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
Log Message:
-----------
[PowerPC] Add dense math bfloat16 floating-point outer-product accumulate to DMR instructions (#133109)
This patch adds the following Dense Math Facility bfloat16
floating-point calculation instructions: dmxvbf16gerx2,
dmxvbf16gerx2pp,dmxvbf16gerx2pn, dmxvbf16gerx2np, dmxvbf16gerx2nn,
pmdmxvbf16gerx2, pmdmxvbf16gerx2pp, pmdmxvbf16gerx2pn,
pmdmxvbf16gerx2np, pmdmxvbf16gerx2nn, along with their corresponding
intrinsics and tests.
Commit: 56910a8b1b302ebf37e9d30bd200091fd23dc232
https://github.com/llvm/llvm-project/commit/56910a8b1b302ebf37e9d30bd200091fd23dc232
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.h
M llvm/test/CodeGen/NVPTX/bug21465.ll
M llvm/test/CodeGen/NVPTX/forward-ld-param.ll
M llvm/test/CodeGen/NVPTX/lower-args-gridconstant.ll
M llvm/test/CodeGen/NVPTX/lower-args.ll
M llvm/test/CodeGen/NVPTX/lower-byval-args.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/nvptx-basic.ll.expected
Log Message:
-----------
[NVPTX] Improve kernel byval parameter lowering (#136008)
This change introduces a new pattern for lowering kernel byval
parameters in `NVPTXLowerArgs`. Each byval argument is wrapped in a call
to a new intrinsic, `@llvm.nvvm.internal.addrspace.wrap`. This intrinsic
explicitly equates to no instructions and is removed during operation
legalization in SDAG. However, it allows us to change the addrspace of
the arguments to 101 to reflect the fact that they will occupy this
space when lowered by `LowerFormalArgs` in `NVPTXISelLowering`.
Optionally, if a generic pointer to a param is needed, a standard
`addrspacecast` is used. This approach offers several advantages:
- Exposes addrspace optimizations: By using a standard `addrspacecast`
back to generic space we allow InferAS to optimize this instruction,
potentially sinking it through control flow or in other ways unsupported
by `NVPTXLowerArgs`. This is demonstrated in several existing tests.
- Clearer, more consistent semantics: Previously an `addrspacecast` from
generic to param space was implicitly a no-op. This is problematic
because it's not reciprocal with the inverse cast, violating LLVM
semantics. Further it is very confusing given the existence of
`cvta.to.param`. After this change the cast equates to this instruction.
- Allow for the removal of all nvvm.ptr.* intrinsics: In a follow-up
change the nvvm.ptr.gen.to.param and nvvm.ptr.param.to.gen intrinsics
may be removed.
Commit: e79d8f6892aa138bfef65334817c24d3d9881855
https://github.com/llvm/llvm-project/commit/e79d8f6892aa138bfef65334817c24d3d9881855
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M flang/include/flang/Lower/DirectivesCommon.h
M flang/include/flang/Optimizer/Builder/DirectivesCommon.h
M flang/lib/Lower/OpenACC.cpp
M flang/test/Lower/OpenACC/acc-bounds.f90
M flang/test/Lower/OpenACC/acc-enter-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-enter-data.f90
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
Log Message:
-----------
[flang][acc] Update stride calculation to include inner-dimensions (#136613)
The acc.bounds operation allows specifying stride - but it did not
clarify what it meant. The dialect was updated to specifically note that
stride must capture inner dimension sizes when specified for outer
dimensions.
Flang lowering was also updated for OpenACC to adhere to this. This was
already the case for descriptor-based arrays - but now this is also
being done for all arrays.
Commit: 53e62c654a3fe181686f1ccd960d2e2b981e4313
https://github.com/llvm/llvm-project/commit/53e62c654a3fe181686f1ccd960d2e2b981e4313
Author: Hubert Tong <hubert.reinterpretcast at gmail.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M compiler-rt/test/profile/AIX/pgo-lto-bcdtor-function-section.test
Log Message:
-----------
[compiler-rt][profile][tests][NFC] Avoid using a.out from PATH (#136465)
Fix use of `a.out` from the PATH by specifying `./a.out`.
Commit: d2fedd67debf011cec7465e0c7ac330dfb548b72
https://github.com/llvm/llvm-project/commit/d2fedd67debf011cec7465e0c7ac330dfb548b72
Author: Augie Fackler <augie at google.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp
Log Message:
-----------
[NVPTX] mark unused variable introduced by 56910a8b1b302ebf37e9d30bd200091fd23dc232 [NFC]
Commit: d1f4f52aa6f2276da8880b5003f220ce6211ad44
https://github.com/llvm/llvm-project/commit/d1f4f52aa6f2276da8880b5003f220ce6211ad44
Author: Thurston Dang <thurston at google.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512fp16-arith-intrinsics.ll
Log Message:
-----------
[msan] Handle x86.avx512fp16.{add,sub.mul,div,min,max}.ph.512 (#136619)
These are handled similarly to x86_avx512_(min|max)_p[sd]_512 intrinsics
(https://github.com/llvm/llvm-project/pull/124421) i.e., using
maybeHandleSimpleNomemIntrinsic, with the last parameter being the
rounding method.
Updates the test from https://github.com/llvm/llvm-project/pull/136260
Commit: d5b40c71f6be972f677de5d9886f91866df007b5
https://github.com/llvm/llvm-project/commit/d5b40c71f6be972f677de5d9886f91866df007b5
Author: royitaqi <royitaqi at users.noreply.github.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M lldb/include/lldb/Symbol/ObjectFile.h
M lldb/include/lldb/Symbol/SymbolFile.h
M lldb/include/lldb/Symbol/SymbolFileOnDemand.h
M lldb/source/Core/Module.cpp
M lldb/source/Symbol/ObjectFile.cpp
M lldb/source/Symbol/SymbolFile.cpp
M lldb/test/API/commands/statistics/basic/TestStats.py
M lldb/unittests/Symbol/LineTableTest.cpp
M lldb/unittests/Symbol/SymtabTest.cpp
Log Message:
-----------
[lldb] Avoid force loading symbols in statistics collection (#136236)
Currently, `DebuggerStats::ReportStatistics()` calls
`Module::GetSymtab(/*can_create=*/false)`, but then the latter calls
`SymbolFile::GetSymtab()`. This will load symbols if haven't yet. See
stacktrace below.
The problem is that `DebuggerStats::ReportStatistics` should be
read-only. This is especially important because it reports stats for
symtab parsing/indexing time, which could be affected by the reporting
itself if it's not read-only.
This patch fixes this problem by adding an optional parameter
`SymbolFile::GetSymtab(bool can_create = true)` and receive the `false`
value passed down from `Module::GetSymtab(/*can_create=*/false)` when
the call was initiated from `DebuggerStats::ReportStatistics()`.
Commit: a1db2c64918efa3d74dfdb402b8cff30bc555521
https://github.com/llvm/llvm-project/commit/a1db2c64918efa3d74dfdb402b8cff30bc555521
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
Log Message:
-----------
[RISCV] Remove duplicate call to MFI.getStackID(FI). NFC
Reuse existing local variable.
Commit: 2cdf474f12090919e5b14c6ef922e5d5df407418
https://github.com/llvm/llvm-project/commit/2cdf474f12090919e5b14c6ef922e5d5df407418
Author: Teresa Johnson <tejohnson at google.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
A llvm/test/Transforms/MemProfContextDisambiguation/mergenodes.ll
A llvm/test/Transforms/MemProfContextDisambiguation/mergenodes2.ll
M llvm/test/Transforms/MemProfContextDisambiguation/overlapping-contexts.ll
Log Message:
-----------
[MemProf] Merge callee clones as needed before assigning functions (#135702)
We perform cloning for each allocation node separately. However, this
sometimes results in a situation where the same node calls multiple
clones of the same callee, created for different allocations. This
causes issues when assigning functions to these clones, as each node can
in reality only call a single callee clone.
To address this, before assigning functions, merge callee clone nodes as
needed using a post order traversal from the allocations. We attempt to
use existing clones as the merge node when legal, and to share them
among callers with the same properties (callers calling the same set of
callee clone nodes for the same allocations).
Without this fix, in some cases incorrect function assignment will lead
to calling the wrong allocation clone. In fact, this showed up in an
existing test, that I didn't notice as it existed to test earlier parts
of the cloning process.
Commit: 08b4c52540727455194b0cf0f6310f391e87c2a5
https://github.com/llvm/llvm-project/commit/08b4c52540727455194b0cf0f6310f391e87c2a5
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M lldb/include/lldb/Symbol/ObjectFile.h
M lldb/include/lldb/Symbol/SymbolFile.h
M lldb/include/lldb/Symbol/SymbolFileOnDemand.h
M lldb/source/Core/Module.cpp
M lldb/source/Symbol/ObjectFile.cpp
M lldb/source/Symbol/SymbolFile.cpp
M lldb/test/API/commands/statistics/basic/TestStats.py
M lldb/unittests/Symbol/LineTableTest.cpp
M lldb/unittests/Symbol/SymtabTest.cpp
Log Message:
-----------
Revert "[lldb] Avoid force loading symbols in statistics collection (#136236)"
This reverts commit d5b40c71f6be972f677de5d9886f91866df007b5.
This change broke greendragon lldb test:
lldb-api :: commands/statistics/basic/TestStats.py
And is therefore being reverted.
Commit: 2b44eb9f56a51a25391319541de750bb9b5c1fc9
https://github.com/llvm/llvm-project/commit/2b44eb9f56a51a25391319541de750bb9b5c1fc9
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/test/TableGen/VarLenDecoder.td
Log Message:
-----------
[LLVM][TableGen] Fix VarlenDecoder.td to not used fixed opcode values (#136632)
Commit: c7ea01b8a0382c21da1f64a9bf077c951096db8e
https://github.com/llvm/llvm-project/commit/c7ea01b8a0382c21da1f64a9bf077c951096db8e
Author: Peter Collingbourne <peter at pcc.me.uk>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
M llvm/test/Transforms/LowerTypeTests/aarch64-jumptable.ll
M llvm/test/Transforms/LowerTypeTests/cfi-direct-call1.ll
M llvm/test/Transforms/LowerTypeTests/function-arm-thumb.ll
M llvm/test/Transforms/LowerTypeTests/function-thumb-bti.ll
M llvm/test/Transforms/LowerTypeTests/function.ll
M llvm/test/Transforms/LowerTypeTests/x86-jumptable.ll
M llvm/test/Transforms/MergeFunc/cfi-thunk-merging.ll
Log Message:
-----------
LowerTypeTests: Switch to emitting one inline asm call per jump table entry.
With the previous approach of emitting one inline asm call for all jump
table entries we would encounter SelectionDAG's limit on the number
of operands per node (65536) when the number of jump table entries
exceeded that number. Fix the problem by switching to one inline asm
per jump table entry so that each DAG node only needs one operand.
Reviewers: fmayer, vitalybuka
Reviewed By: fmayer
Pull Request: https://github.com/llvm/llvm-project/pull/136265
Commit: 698cd48db9c2058442e5e6355a77e91e3456ec2c
https://github.com/llvm/llvm-project/commit/698cd48db9c2058442e5e6355a77e91e3456ec2c
Author: Jim Lin <jim at andestech.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
Log Message:
-----------
[RISCV] Fix Lsb > Msb case in (sra (sext_inreg X, _), C) for th.ext (#136287)
According the
[spec](https://github.com/XUANTIE-RV/thead-extension-spec/releases/tag/2.3.0),
the operation of `th.ext rd, rs1, msb, lsb` is
reg[rd] := sign_extend(reg[rs1][msb:lsb])
The spec doesn't specify if lsb is greater than msb.
I don't think lsb can be greater than msb. So that If the shift-right
amount is greater than msb, we can set lsb equal to msb to extract the
bit rs1[msb] and sign-extend it.
Commit: ddb8870a5f396f2f17462f878fb7c0cffc879ce4
https://github.com/llvm/llvm-project/commit/ddb8870a5f396f2f17462f878fb7c0cffc879ce4
Author: Jim Lin <jim at andestech.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
Log Message:
-----------
[RISCV] Remove the FIXME for using sraiw+and. NFC.
https://github.com/llvm/llvm-project/pull/102034 has implemented it.
Commit: 46e734746db7176f6e32b3c98beacf1e94fced37
https://github.com/llvm/llvm-project/commit/46e734746db7176f6e32b3c98beacf1e94fced37
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M flang/include/flang/Optimizer/Dialect/CUF/CUFOps.td
M flang/lib/Lower/Bridge.cpp
M flang/lib/Optimizer/Dialect/CUF/CUFOps.cpp
M flang/test/Lower/CUDA/cuda-kernel-loop-directive.cuf
Log Message:
-----------
[flang][cuda] Update stream type for cuf kernel op (#136627)
Update the type of the stream operand to be similar to KernelLaunchOp.
Commit: b144258b0c0cc63dffba00a911d6539f00ed07bb
https://github.com/llvm/llvm-project/commit/b144258b0c0cc63dffba00a911d6539f00ed07bb
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Parse/Parser.h
M clang/lib/Parse/ParseExpr.cpp
M clang/test/AST/ast-dump-recovery.cpp
M clang/test/AST/new-unknown-type.cpp
M clang/test/Parser/cxx-concepts-requires-clause.cpp
Log Message:
-----------
[Clang] Improve error recovery for invalid calls (#136295)
It doesn't make sense that we only build a RecoveryExpr for expressions
with invalid trailing commas. This patch extends it so that we now
always build up a RecoveryExpr whenever the call contains anything
invalid. As a result, we can back out HasTrailingComma.
There is only one diagnostic change as to concepts, where a RecoveryExpr
than an ExprError is now used to model an invalid requires clause, for
which we suggest adding parentheses around it. (This looks like what GCC
diagnoses)
Commit: 0014b49482c0862c140149c650d653b4e41fa9b4
https://github.com/llvm/llvm-project/commit/0014b49482c0862c140149c650d653b4e41fa9b4
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
M llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/BPF/BPFTargetTransformInfo.h
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.h
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
M llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h
M llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.cpp
M llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h
M llvm/lib/Target/Mips/MipsTargetTransformInfo.cpp
M llvm/lib/Target/Mips/MipsTargetTransformInfo.h
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SPIRV/SPIRVTargetTransformInfo.h
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
M llvm/lib/Target/VE/VETargetTransformInfo.h
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
Log Message:
-----------
[TTI] Make all interface methods const (NFCI) (#136598)
Making `TargetTransformInfo::Model::Impl` `const` makes sure all
interface methods are `const`, in `BasicTTIImpl`, its bases, and in all
derived classes.
Pull Request: https://github.com/llvm/llvm-project/pull/136598
Commit: 9e26c797ae9699fba8bd62af99ab3ad6f9b16462
https://github.com/llvm/llvm-project/commit/9e26c797ae9699fba8bd62af99ab3ad6f9b16462
Author: Liao Chunyu <chunyu at iscas.ac.cn>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.rst
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVSystemOperands.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/features-info.ll
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/test/MC/RISCV/machine-csr-names.s
M llvm/test/MC/RISCV/rv32-machine-csr-names.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Add smcntrpmf extension (#136556)
spec: https://github.com/riscvarchive/riscv-smcntrpmf
Commit: 497382ee07100f3698621fc48b66a0bd50a1ca2a
https://github.com/llvm/llvm-project/commit/497382ee07100f3698621fc48b66a0bd50a1ca2a
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-04-21 (Mon, 21 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Log Message:
-----------
[SelectionDAG] Make the FoldingSet profile in getAtomic match AddNodeIDCustom. (#136651)
In theory, the mismatch would have made CSE of AtomicSDNodes not work,
but I don't know how to test it.
Commit: 784dc16088885ebb28437ae2dbb90dcfd5df0457
https://github.com/llvm/llvm-project/commit/784dc16088885ebb28437ae2dbb90dcfd5df0457
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef][IR] Fix default AS documentation for allocas without explicit AS (#135942)
So far, the Language Reference said that the alloca address space from
the datalayout is used if no explicit address space is provided, which
is not what the LLParser and the AsmWriter implement. This patch adjusts
the documentation to match the implementation: The default AS 0 is used
if none is explicitly specified.
This is an alternative to PR #135786, which would change the parser's
behavior to match the Language Reference instead.
Commit: 53927ab726e6d0dfb3255498b6d0b130adeafb8c
https://github.com/llvm/llvm-project/commit/53927ab726e6d0dfb3255498b6d0b130adeafb8c
Author: Henrich Lauko <xlauko at mail.muni.cz>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
Log Message:
-----------
[CIR] Make ZeroAttr use AttrBuilderWithInferredContext (#136604)
This mirrors incubator changes from https://github.com/llvm/clangir/pull/1576
Commit: 0ca2d4d10451874b1d107e89c32eb7fd95e1a608
https://github.com/llvm/llvm-project/commit/0ca2d4d10451874b1d107e89c32eb7fd95e1a608
Author: Kirill Chibisov <contact at kchibisov.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/test/Dialect/EmitC/transforms.mlir
M mlir/test/Target/Cpp/expressions.mlir
Log Message:
-----------
[mlir][emitc] mark `emitc.load` with `CExpression` (#130802)
Follow the `call` and `call_opaque` operations, as well as `apply`,
which already are marked as `CExpression` even though they have side
effects.
Even though `emitc.load` can be included inside the `emitc.expression`,
the inlining and `--form-expression` pass won't actually inline them
inside other expression due to it having a side effect, thus unless the
user manually writes the `emitc.load` inside the `emitc.expression` it
won't appear there.
--
It was brought
https://github.com/llvm/llvm-project/pull/91475#issuecomment-2302529428
and while there was some opposition due to `load` having a side effect,
`emitc` already allows all the rest operations that have it, so for
consistency reasons, enabling it doesn't really hurt from my point of
view. Especially given that `--form-expression` doesn't allow
it to really inline inside other expressions, which makes sense, since
if the users want such behavior, they should explicitly opt-in.
Commit: 8639b365a5988932973a82ffe5e620a9c8ef9039
https://github.com/llvm/llvm-project/commit/8639b365a5988932973a82ffe5e620a9c8ef9039
Author: Henrich Lauko <xlauko at mail.muni.cz>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/lib/CIR/Dialect/IR/CIRMemorySlot.cpp
Log Message:
-----------
[CIR] Make UndefAttr use AttrBuilderWithInferredContext (#136605)
This mirrors incubator changes from https://github.com/llvm/clangir/pull/1577
Commit: 2d3bbb6aafbc74ef6fc51286f09def0f0e35fe14
https://github.com/llvm/llvm-project/commit/2d3bbb6aafbc74ef6fc51286f09def0f0e35fe14
Author: Matthias Springer <me at m-sp.org>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M mlir/include/mlir/IR/Builders.h
M mlir/lib/IR/Builders.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
Log Message:
-----------
[mlir][Transforms] Dialect conversion: Erase materialized constants instead of rollback (#136489)
When illegal (and not legalizable) constant operations are materialized
during a dialect conversion as part of op folding, these operations must
be deleted again. This used to be implemented via the rollback
mechanism. This commit switches the implementation to regular rewriter
API usage: simply delete the materialized constants with `eraseOp`.
This commit is in preparation of the One-Shot Dialect Conversion
refactoring, which will disallow IR rollbacks.
This commit also adds a new optional parameter to `OpBuilder::tryFold`
to get hold of the materialized constant ops.
Commit: 56f5bcb0350b8af44aa5f65ccf865a464df2cc4a
https://github.com/llvm/llvm-project/commit/56f5bcb0350b8af44aa5f65ccf865a464df2cc4a
Author: Henrich Lauko <xlauko at mail.muni.cz>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/Dialect/IR/CIRMemorySlot.cpp
Log Message:
-----------
[CIR] Let ConstantOp builder infer its type automatically (#136606)
This mirrors incubator changes from https://github.com/llvm/clangir/pull/1578
Commit: 8bc0d4d1ccb708d20413876258885a48d3ca6b3d
https://github.com/llvm/llvm-project/commit/8bc0d4d1ccb708d20413876258885a48d3ca6b3d
Author: Matthias Springer <me at m-sp.org>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/Transforms/Utils/DialectConversion.cpp
Log Message:
-----------
[mlir][Transforms] Dialect conversion: Add flag to disable rollback (#136490)
This commit adds a new flag to `ConversionConfig` to disallow the
rollback of IR modification. This commit is in preparation of the
One-Shot Dialect Conversion refactoring, which will remove the ability
to roll back IR modifications from the conversion driver.
RFC:
https://discourse.llvm.org/t/rfc-a-new-one-shot-dialect-conversion-driver/79083/46
By default, this flag is set to "true". I.e., the rollback of IR
modifications is allowed. When set to "false", the conversion driver
will report a fatal LLVM error when an IR rollback is requested. The
name of the rolled back pattern is included in the error message.
Moreover, the original IR is no longer restored after a failed
conversion.
Example:
```
within split at llvm-project/mlir/test/Conversion/ArithToSPIRV/fast-math.mlir:1 offset :11:8: error: pattern '(anonymous namespace)::CmpFOpNanKernelPattern' produced IR that could not be legalized
%0 = arith.cmpf ord, %arg0, %arg1 fastmath<fast> : f32
^
within split at llvm-project/mlir/test/Conversion/ArithToSPIRV/fast-math.mlir:1 offset :11:8: note: see current operation: %1 = "arith.cmpf"(%arg0, %arg1) <{fastmath = #arith.fastmath<fast>, predicate = 7 : i64}> : (f32, f32) -> i1
pattern '(anonymous namespace)::CmpFOpNanKernelPattern' rollback of IR modifications requested
UNREACHABLE executed at llvm-project/mlir/lib/Transforms/Utils/DialectConversion.cpp:1231!
```
The majority of patterns in MLIR have already been updated such that
they do not trigger any rollbacks, but a few SPIRV patterns remain. More
information in the RFC.
Commit: a22ad659cd0665669d89fae174f9e6a83d1a446d
https://github.com/llvm/llvm-project/commit/a22ad659cd0665669d89fae174f9e6a83d1a446d
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M lldb/include/lldb/Host/Config.h.cmake
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.h
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
Log Message:
-----------
[lldb/cmake] Normalize use of HAVE_LIBCOMPRESSION (#135528)
I *think* this was the reason behind the failures in
2fd860c1f559c0b0be66cc000e38270a04d0a1a3: the clang include tool showed
the Config.h headers as unused, and because the macro was referenced
through an `#ifdef`, its removal didn't cause build failures. Switching
to `#cmakedefine01` + `#if` should make sure this does not happen again.
According to D48977, the `#ifndef`+`#cmakedefine` patterns is due to
some files redefining the macro themselves. I no longer see any such
files in the source tree (there also were no files like that in the
source tree at the revision mentioned, but the macro *was* defined in
the hand-maintained XCode project we had at the time).
Commit: f541a3aad8e70b613ea411bf2d3e64a220f98e82
https://github.com/llvm/llvm-project/commit/f541a3aad8e70b613ea411bf2d3e64a220f98e82
Author: Frederik Harwath <frederik.harwath at amd.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
A llvm/test/CodeGen/AMDGPU/si-instr-info-vopc-exec.mir
Log Message:
-----------
[AMDGPU] SIInstrInfo: Fix resultDependsOnExec for VOPC instructions (#134629)
SIInstrInfo::resultDependsOnExec assumes that operand 0 of a comparison
is always the destination of the instruction. This is not true for
instructions in VOPC form where it is "src0". This led to a crash in
machine-cse.
---------
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
Commit: ef72b936262bc712d65756df1ad3ee095c794e0e
https://github.com/llvm/llvm-project/commit/ef72b936262bc712d65756df1ad3ee095c794e0e
Author: David Sherwood <david.sherwood at arm.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-intrinsic-calls.ll
Log Message:
-----------
[LV] Use requested calling convention for vector math routines (#136122)
Some vector math routines, e.g. ArmPL, specify a particular
calling convention on the routines which can help improve
performance by specifying what registers have to be preserved
across the call.
Commit: 3334c3597dd51f5a102e5005738e3bf4ef7530e2
https://github.com/llvm/llvm-project/commit/3334c3597dd51f5a102e5005738e3bf4ef7530e2
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
M llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/BPF/BPFTargetTransformInfo.h
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
M llvm/lib/Target/VE/VETargetTransformInfo.h
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
Log Message:
-----------
[TTI] Fix discrepancies in prototypes between interface and implementations (NFCI) (#136655)
These are not diagnosed because implementations hide the methods of the base class rather than overriding them.
This works as long as a hiding function is callable with the same arguments as the same function from the base class.
Pull Request: https://github.com/llvm/llvm-project/pull/136655
Commit: a35f940b876a09211f3e68dd25d00271b7195145
https://github.com/llvm/llvm-project/commit/a35f940b876a09211f3e68dd25d00271b7195145
Author: Christian Kandeler <christian.kandeler at qt.io>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang-tools-extra/clangd/unittests/XRefsTests.cpp
M clang/lib/Index/IndexBody.cpp
Log Message:
-----------
[clangd] Support operators new and delete in textDocument/references (#135620)
Commit: c3f815ba82defc84244a9688fd2578da513340fb
https://github.com/llvm/llvm-project/commit/c3f815ba82defc84244a9688fd2578da513340fb
Author: anjenner <161845516+anjenner at users.noreply.github.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M lldb/source/Core/DataFileCache.cpp
M llvm/include/llvm/Support/Caching.h
M llvm/lib/CGData/CodeGenData.cpp
M llvm/lib/Debuginfod/Debuginfod.cpp
M llvm/lib/LTO/LTOBackend.cpp
M llvm/lib/Support/Caching.cpp
M llvm/tools/gold/gold-plugin.cpp
M llvm/tools/llvm-lto2/llvm-lto2.cpp
M llvm/unittests/Support/CMakeLists.txt
A llvm/unittests/Support/Caching.cpp
Log Message:
-----------
Modify the localCache API to require an explicit commit on CachedFile… (#136121)
…Stream.
CachedFileStream has previously performed the commit step in its
destructor, but this means its only recourse for error handling is
report_fatal_error. Modify this to add an explicit commit() method, and
call this in the appropriate places with appropriate error handling for
the location.
Currently the destructor of CacheStream gives an assert failure in Debug
builds if commit() was not called. This will help track down any
remaining uses of the API that assume the old destructior behaviour. In
Release builds we fall back to the previous behaviour and call
report_fatal_error if the commit fails.
This is version 2 of this PR, superseding reverted PR
https://github.com/llvm/llvm-project/pull/115331 . I have incorporated a
change to the testcase to make it more reliable on Windows, as well as
two follow-up changes
(https://github.com/llvm/llvm-project/commit/df79000896101acc9b8d7435e59f767b36c00ac8
and
https://github.com/llvm/llvm-project/commit/b0baa1d8bd68a2ce2f7c5f2b62333e410e9122a1)
that were also reverted when 115331 was reverted.
---------
Co-authored-by: Augie Fackler <augie at google.com>
Co-authored-by: Vitaly Buka <vitalybuka at google.com>
Commit: 382263376fcfed967f5bc17400d9e4542b37801c
https://github.com/llvm/llvm-project/commit/382263376fcfed967f5bc17400d9e4542b37801c
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M lldb/docs/resources/build.rst
Log Message:
-----------
[lldb][docs] Repeat required Python version number
We do say it in the table below but if you didn't
want any optional stuff you'd miss it.
Commit: 278c429d11e63bc709ea8c537b23c4e350ce2a07
https://github.com/llvm/llvm-project/commit/278c429d11e63bc709ea8c537b23c4e350ce2a07
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
Log Message:
-----------
[ValueTracking] Drop ucmp/scmp from getIntrinsicRange() (NFCI)
After #135642 we have a range attribute on the intrinsic declaration,
so we should not need the special handling here.
Commit: 4bcc414af3782c333f3d535c0e0a92e6120868f5
https://github.com/llvm/llvm-project/commit/4bcc414af3782c333f3d535c0e0a92e6120868f5
Author: Robert Konicar <rkonicar at mail.muni.cz>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/SMT/IR/SMTAttributes.td
M mlir/include/mlir/IR/BuiltinAttributes.td
M mlir/include/mlir/TableGen/AttrOrTypeDef.h
M mlir/lib/Dialect/SMT/IR/SMTAttributes.cpp
M mlir/lib/TableGen/AttrOrTypeDef.cpp
A mlir/test/mlir-tblgen/apint-param-error.td
M mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp
Log Message:
-----------
[MLIR][TableGen] Error on APInt parameter without custom comparator (#135970)
The error is triggered when an attribute or type uses an APInt typed
parameter with the generated equality operator. If the compared APInts
have different bit widths the equality operator triggers an assert. This
is dangerous, since `StorageUniquer` for types and attributes uses the
equality operator when a hash collision appears. As such, it is
necessary to use custom provided comarator or `APIntParameter` that
already has it.
This commit also replaces uses of the raw `APInt` parameter with the
`APIntParameter` and removes the no longer necessary custom StorageClass
for the `BitVectorAttr` from the SMT dialect that was a workaround for
the described issue.
---------
Co-authored-by: Tobias Gysi <tobias.gysi at nextsilicon.com>
Commit: d8b0e616b746a6c7bdd0492f2f349105028684b0
https://github.com/llvm/llvm-project/commit/d8b0e616b746a6c7bdd0492f2f349105028684b0
Author: Nathan Gauër <brioche at google.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
M llvm/test/CodeGen/SPIRV/pointers/getelementptr-downcast-vector.ll
Log Message:
-----------
[SPIR-V] Fix OpVectorShuffle operands on load (#135954)
The generated OpVectorShuffle was wrong, as the indices we pass are not
to select the vector to sample from, but the position in the vector.
Commit: e12681ae733e8341c161534d4d4de2611573b616
https://github.com/llvm/llvm-project/commit/e12681ae733e8341c161534d4d4de2611573b616
Author: Hans Wennborg <hans at chromium.org>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/test/Driver/cl-options.c
Log Message:
-----------
[clang-cl] Parse the /dynamicdeopt option
which was mentioned in
https://devblogs.microsoft.com/cppblog/cpp-dynamic-debugging-full-debuggability-for-optimized-builds/
(That post also mentions /d2DDTrimInlines, which we already parse via
a /d2 catch-all.)
Commit: adb671ea23af72c0fa1acd42103a5e9ca413d729
https://github.com/llvm/llvm-project/commit/adb671ea23af72c0fa1acd42103a5e9ca413d729
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.h
Log Message:
-----------
[lldb] Clean up StartDebugserverProcess before I start refactoring it (#135342)
- use early exits where possible
- avoid the listen thread by using Socket APIs which allow separate
"listen" and "accept" steps
- use formatv-like log statements
There "should" be no functional changes from this patch.
Commit: a86f4ee774e6d2eb9f38502ddda65842179a246a
https://github.com/llvm/llvm-project/commit/a86f4ee774e6d2eb9f38502ddda65842179a246a
Author: Yuval Deutscher <yuvald at sweet.security>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M lldb/test/API/commands/platform/launchgdbserver/TestPlatformLaunchGDBServer.py
M lldb/tools/lldb-server/SystemInitializerLLGS.h
Log Message:
-----------
[lldb] Use correct path for debugserver (#131609)
This solves an issue that arises when running lldb-server through a
symlink which is not named exactly `lldb-server`. For example, in many
distros lldb-server is packaged as e.g.
`/usr/lib/llvm-19/bin/lldb-server` which is then accessed through a
symlink such as `/usr/bin/lldb-server-19`.
It turns out that there is a cascade of bugs here:
* `GetShlibDir` attempts to locate the LLVM library directory by calling
`GetModuleFileSpecForHostAddress` on the address of the function
`ComputeSharedLibraryDirectory`, assuming that it is inside
`liblldb.so`. However, in every packaging I've seen of lldb-server the
function `ComputeSharedLibraryDirectory` is statically linked into the
`lldb-server` binary and is not in `liblldb.so`.
* When run through a symlink, `GetModuleFileSpecForHostAddress` on an
address that is in `lldb-server` returns the path of the symlink, not
the path of the binary itself. So we get e.g. `/usr/bin/` and not
`/usr/lib/llvm-19/bin/`.
* `GetDebugserverPath` attempts to concat `"lldb-server"` to the
directory we obtained, and thus fails when the symlink is not named
exactly `lldb-server`.
* Ironically, the reason that this works in the first place is precisely
because `GetModuleFileSpecForHostAddress` returns an incorrect path -
when the server is run as `lldb-server-19 ...` it returns
`"lldb-server-19"` which then causes `ComputePathRelativeToLibrary` to
fail and then `ComputeSupportExeDirectory` falls back to just using
`GetProgramFileSpec` instead (which is the only option that actually
yields a correct path).
Commit: 9efd798a278a7ddda3b88365558ceb655c329d11
https://github.com/llvm/llvm-project/commit/9efd798a278a7ddda3b88365558ceb655c329d11
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
Log Message:
-----------
[TTI] Make the rest of TTI::Concept/TTI::Model methods const (NFC) (#136668)
This will simplify future changes.
Commit: 112ffe7c621e8bf145c5c5926e36f3af9e0fd045
https://github.com/llvm/llvm-project/commit/112ffe7c621e8bf145c5c5926e36f3af9e0fd045
Author: Sylvestre Ledru <sylvestre at debian.org>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/include/clang/Driver/Distro.h
M clang/lib/Driver/Distro.cpp
Log Message:
-----------
Add support of the next Ubuntu (Ubuntu 25.10 - Questing Quokka)
Commit: 97eb416c65863cdf25ec3fa19ed056aac38d1013
https://github.com/llvm/llvm-project/commit/97eb416c65863cdf25ec3fa19ed056aac38d1013
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M flang/lib/Parser/unparse.cpp
A flang/test/Parser/OpenMP/cancel.f90
M llvm/include/llvm/Frontend/Directive/DirectiveBase.td
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/TableGen/DirectiveEmitter.h
M llvm/utils/TableGen/Basic/DirectiveEmitter.cpp
Log Message:
-----------
[flang][Parser][OpenMP] Fix unparser for cancellation_construct_type (#136001)
Previously the unparser would print like
```
!$OMP CANCEL CANCELLATION_CONSTRUCT_TYPE(SECTIONS)
```
This is not valid Fortran. I have fixed it to print without the clause
name.
Commit: c1940cd0deef84c9cbbf6966d956b8fef4519efa
https://github.com/llvm/llvm-project/commit/c1940cd0deef84c9cbbf6966d956b8fef4519efa
Author: Nathan Gauër <brioche at google.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
M llvm/test/CodeGen/SPIRV/pointers/getelementptr-downcast-struct.ll
M llvm/test/CodeGen/SPIRV/pointers/getelementptr-downcast-vector.ll
A llvm/test/CodeGen/SPIRV/pointers/store-struct.ll
Log Message:
-----------
[SPIR-V] Add store legalization for ptrcast (#135369)
This commits adds handling for spv.ptrcast result being used in a store
instruction, modifying the store to operate on the source type.
Commit: 8f8853a5743fe204b390f0276cb6d0266e4b9a9b
https://github.com/llvm/llvm-project/commit/8f8853a5743fe204b390f0276cb6d0266e4b9a9b
Author: quic_hchandel <quic_hchandel at quicinc.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
A llvm/test/CodeGen/RISCV/xqcia.ll
Log Message:
-----------
[RISCV] Add ISel patterns for Xqcia instructions (#136548)
This patch adds instruction selection patterns for generating the
integer arithmetic instructions.
Commit: a095ebc58c9f7cd0d39796ed0aabc63b23ed88ce
https://github.com/llvm/llvm-project/commit/a095ebc58c9f7cd0d39796ed0aabc63b23ed88ce
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/vector-select.ll
Log Message:
-----------
[LLVM][CostModel][AArch64] Remove magic numbers from f16 vector compares. (#135795)
The PR also extends the code to cover bfloat vector compares that are
also promoted to float.
NOTE: There is a bail out for the compares that are scalarised that will
be removed by https://github.com/llvm/llvm-project/pull/135398.
Commit: d7d170656404e1cb29a51689fd66a12bc060c630
https://github.com/llvm/llvm-project/commit/d7d170656404e1cb29a51689fd66a12bc060c630
Author: Ebuka Ezike <yerimyah1 at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M lldb/include/lldb/Core/IOHandler.h
M lldb/include/lldb/Host/Editline.h
M lldb/include/lldb/Interpreter/CommandInterpreter.h
M lldb/source/Core/Debugger.cpp
M lldb/source/Core/IOHandler.cpp
M lldb/source/Host/common/Editline.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/test/API/terminal/TestEditline.py
Log Message:
-----------
[lldb] Fix use-color settings not persistent (#135626)
Fixes https://github.com/llvm/llvm-project/issues/22981
If `settings set use-color` is changed when lldb is running it does not take effect.
This is fixes that.
---------
Signed-off-by: Ebuka Ezike <yerimyah1 at gmail.com>
Co-authored-by: Jonas Devlieghere <jonas at devlieghere.com>
Commit: 1a48e1df4541ccccdaf14a6ea379be004e319a09
https://github.com/llvm/llvm-project/commit/1a48e1df4541ccccdaf14a6ea379be004e319a09
Author: Mariusz Sikora <mariusz.sikora at amd.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
A llvm/test/CodeGen/AMDGPU/do-not-fold-copy.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
Log Message:
-----------
[AMDGPU] Do not fold COPY with implicit operands (#136003)
Folding may remove COPY from inside of the divergent loop.
Commit: ef926e7e49cab2d8087ed4ebdbdc686ac99e1c8f
https://github.com/llvm/llvm-project/commit/ef926e7e49cab2d8087ed4ebdbdc686ac99e1c8f
Author: Christian Sigg <csigg at google.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
Log Message:
-----------
[lldb][mlir] Port a22ad659cd0665669d89fae174f9e6a83d1a446d
Commit: c60f24dca96dad44afc60df3fcb80997737b6306
https://github.com/llvm/llvm-project/commit/c60f24dca96dad44afc60df3fcb80997737b6306
Author: Christian Sigg <csigg at google.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
Log Message:
-----------
[lldb][mlir] Fix port of a22ad65
Sorry, typo!
Commit: 7851b1bcf1f0966883d5598268f95d355718f9f5
https://github.com/llvm/llvm-project/commit/7851b1bcf1f0966883d5598268f95d355718f9f5
Author: Christian Sigg <csigg at google.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M mlir/lib/ExecutionEngine/CudaRuntimeWrappers.cpp
M mlir/lib/Target/LLVMIR/Dialect/GPU/SelectObjectAttr.cpp
A mlir/test/Integration/GPU/CUDA/concurrent-kernels.mlir
M mlir/test/Target/LLVMIR/gpu.mlir
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][gpu] Change GPU modules to globals (#135478)
Load/unload GPU modules in global ctors/dtors instead of each time when
launching a kernel.
Loading GPU modules is a heavy-weight operation and synchronizes the GPU
context. Now that the modules are loaded ahead of time, asynchronously
launched kernels can run concurrently, see
https://discourse.llvm.org/t/how-to-lower-the-combination-of-async-gpu-ops-in-gpu-dialect.
The implementations of `embedBinary()` and `launchKernel()` use slightly
different mechanics at the moment but I prefer to not change the latter
more than necessary as part of this PR. I will prepare a follow-up NFC
for `launchKernel()` to align them again.
Commit: 84cd0d3c38e40e4cb5e416684ecd84df914e19aa
https://github.com/llvm/llvm-project/commit/84cd0d3c38e40e4cb5e416684ecd84df914e19aa
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M lldb/source/Plugins/UnwindAssembly/x86/UnwindAssembly-x86.cpp
M lldb/source/Symbol/DWARFCallFrameInfo.cpp
M lldb/source/Symbol/UnwindPlan.cpp
M lldb/test/Shell/Unwind/Inputs/eh-frame-small-fde.s
M lldb/test/Shell/Unwind/eh-frame-small-fde.test
M lldb/unittests/Symbol/UnwindPlanTest.cpp
Log Message:
-----------
[lldb] Slide eh_frame unwind plan if it doesn't begin at function boundary (#135333)
This is mainly useful for discontinuous functions because individual
parts of the function will have separate FDE entries, which can begin
many megabytes from the start of the function. However, I'm separating
it out, because it turns out we already have a test case for the
situation where the FDE does not begin exactly at the function boundary.
The test works mostly by accident because the FDE starts only one byte
after the beginning of the function so it doesn't really matter whether
one looks up the unwind row using the function or fde offset. In this
patch, I beef up the test to catch this problem more reliably.
To make this work I've also needed to change a couple of places which
that an unwind plan always has a row at offset zero.
Commit: 3d91a71223801bb73ab3e4ff8ab3f883639ed79f
https://github.com/llvm/llvm-project/commit/3d91a71223801bb73ab3e4ff8ab3f883639ed79f
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticGroups.td
A clang/test/SemaCXX/cxx20-c99-designator.cpp
M clang/test/SemaCXX/decltype.cpp
Log Message:
-----------
Reorganize -Winitializer-overrides and -Wreorder-init-list (#136586)
These are both now grouped under -Wc99-designator as they both relate to
the C99 feature as it was introduced into C++20.
Fixes #47037
Commit: a25fdd7aca240c5e1a1051ee0509c9c6a4440009
https://github.com/llvm/llvm-project/commit/a25fdd7aca240c5e1a1051ee0509c9c6a4440009
Author: Pankaj Dwivedi <pankajkumar.divedi at amd.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/add64-low-32-bits-known-zero.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/constrained-shift.ll
M llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll
M llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/ptrmask.ll
M llvm/test/CodeGen/AMDGPU/sdag-print-divergence.ll
M llvm/test/CodeGen/AMDGPU/sub64-low-32-bits-known-zero.ll
A llvm/test/CodeGen/AMDGPU/uniform-vgpr-to-sgpr-return.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
Log Message:
-----------
Reapply "[AMDGPU] Insert readfirstlane in the function returns in sgpr." (#136678)
Reapply #135326 and fix the target-dependent constant check.
---------
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
Commit: 7f684c9fca76a166efe4e03c6e2bc969e8aed81b
https://github.com/llvm/llvm-project/commit/7f684c9fca76a166efe4e03c6e2bc969e8aed81b
Author: Jacques Pienaar <jpienaar at google.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M mlir/lib/Interfaces/ControlFlowInterfaces.cpp
M mlir/test/Dialect/SCF/invalid.mlir
Log Message:
-----------
[mlir] Avoid doublespace in error (NFC). (#136560)
This was resulting in 2 spaces in the error message.
Commit: e428afdfcf56ccadbbcff16e8fe52e51622baed7
https://github.com/llvm/llvm-project/commit/e428afdfcf56ccadbbcff16e8fe52e51622baed7
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/Support/BUILD.gn
Log Message:
-----------
[gn build] Port c3f815ba82de
Commit: 587206a442ebb656f9d72e7e0cc5845ef3a2f7ed
https://github.com/llvm/llvm-project/commit/587206a442ebb656f9d72e7e0cc5845ef3a2f7ed
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M lldb/test/API/commands/platform/launchgdbserver/TestPlatformLaunchGDBServer.py
Log Message:
-----------
[lldb] Avoid modifying the source tree in TestPlatformLaunchGDBServer
The test binary gets uploaded to the "remote" platform's working
directory which, by default is in the source tree. Change that.
Commit: 47903e3372b8ab942f0d36f135edba5a8de07cf9
https://github.com/llvm/llvm-project/commit/47903e3372b8ab942f0d36f135edba5a8de07cf9
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
A llvm/test/CodeGen/AMDGPU/insert-waitcnts-gfx12-wbinv.mir
Log Message:
-----------
[AMDGPU][InsertWaitCnts] Add test for global_wb/inv/wbinv tracking (#135339)
Commit: ec3a90509d7db3b32d6102351c86470d9799dc9b
https://github.com/llvm/llvm-project/commit/ec3a90509d7db3b32d6102351c86470d9799dc9b
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx942.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-store.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-gfx12-wbinv.mir
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-global-inv-wb.mir
Log Message:
-----------
[AMDGPU][InsertWaitCnts] Track global_wb/inv/wbinv (#135340)
wb/wbinv use storecnt, inv uses loadcnt.
Track them as VMEM_WRITE_ACCESS and VMEM_READ_ACCESS to avoid
InsertWaitCnt incorrectly eliminating the waitcnts after these instructions.
Solves SWDEV-526604
Commit: 2b712693886a2a8339c0452f12f06b676e946d49
https://github.com/llvm/llvm-project/commit/2b712693886a2a8339c0452f12f06b676e946d49
Author: Iris <0.0 at owo.li>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
Log Message:
-----------
[SelectionDAG][X86] Fold `sub(x, mul(divrem(x,y)[0], y))` to `divrem(x, y)[1]` (#136565)
Closes #51823.
Commit: 2e145f11c0bcfa2052416d96d682c75f33971a8c
https://github.com/llvm/llvm-project/commit/2e145f11c0bcfa2052416d96d682c75f33971a8c
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M flang-rt/CMakeLists.txt
M flang-rt/README.md
M flang-rt/cmake/modules/AddFlangRT.cmake
M flang-rt/lib/runtime/CMakeLists.txt
M libc/cmake/modules/LLVMLibCArchitectures.cmake
M libc/docs/gpu/building.rst
Log Message:
-----------
[LLVM] Replace use of `LLVM_RUNTIMES_TARGET` with `LLVM_DEFAULT_TARGET_TRIPLE` (#136208)
Summary:
For purposes of determining the triple, it's more correct to use
`LLVM_DEFAULT_TARGET_TRIPLE`.
Commit: 974a8ccb2b9f5b930ce47f65122b5a86481e57fe
https://github.com/llvm/llvm-project/commit/974a8ccb2b9f5b930ce47f65122b5a86481e57fe
Author: Muhammad Omair Javaid <omair.javaid at linaro.org>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M lldb/test/API/commands/statistics/basic/TestStats.py
Log Message:
-----------
[LLDB] Silence Windows buildbot failure caused by #136226
This patch temporarily silences a LLDB test failure caused by PR 136226.
The PR added symbol/table count statistics but caused failures in the
lldb-aarch64-windows buildbot where the reported number of symbols and
symbol tables were incorrectly showing as 0.
https://lab.llvm.org/buildbot/#/builders/141/builds/8084
Commit: a5cdbef5f06904fab27219955604a2759e4dd482
https://github.com/llvm/llvm-project/commit/a5cdbef5f06904fab27219955604a2759e4dd482
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M flang-rt/CMakeLists.txt
M flang-rt/README.md
M flang-rt/cmake/modules/AddFlangRT.cmake
M flang-rt/lib/runtime/CMakeLists.txt
M libc/cmake/modules/LLVMLibCArchitectures.cmake
M libc/docs/gpu/building.rst
Log Message:
-----------
Revert "[LLVM] Replace use of `LLVM_RUNTIMES_TARGET` with `LLVM_DEFAULT_TARGET_TRIPLE` (#136208)"
This reverts commit 2e145f11c0bcfa2052416d96d682c75f33971a8c.
Somehow causes some static assertions to fail?
Commit: dba8acde6d6a320dad42cdbfe7c8261938348e23
https://github.com/llvm/llvm-project/commit/dba8acde6d6a320dad42cdbfe7c8261938348e23
Author: Hans Wennborg <hans at chromium.org>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
Log Message:
-----------
Revert "[ValueTracking] Drop ucmp/scmp from getIntrinsicRange() (NFCI)"
This does seem to cause some functionality to change, see comment on
https://github.com/llvm/llvm-project/commit/278c429d11e63bc709ea8c537b23c4e350ce2a07
This reverts commit 278c429d11e63bc709ea8c537b23c4e350ce2a07.
Commit: 616e8cc1fa0319819aa6978af0af9a3e4896103a
https://github.com/llvm/llvm-project/commit/616e8cc1fa0319819aa6978af0af9a3e4896103a
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M lldb/test/API/commands/platform/launchgdbserver/TestPlatformLaunchGDBServer.py
M lldb/tools/lldb-server/SystemInitializerLLGS.h
Log Message:
-----------
Revert "[lldb] Use correct path for debugserver (#131609)"
This reverts commit a86f4ee774e6d2eb9f38502ddda65842179a246a and the fixup in
587206a442ebb656f9d72e7e0cc5845ef3a2f7ed because brakage on macos
(TestAutoInstallMainExecutable.py).
Commit: c9eb1ffcfe7cf8c9751afe436a6fcab9cb5b9c9b
https://github.com/llvm/llvm-project/commit/c9eb1ffcfe7cf8c9751afe436a6fcab9cb5b9c9b
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M clang/lib/Sema/SemaOpenACCClause.cpp
M clang/test/CIR/CodeGenOpenACC/kernels.c
M clang/test/CIR/CodeGenOpenACC/parallel.c
M clang/test/CIR/CodeGenOpenACC/serial.c
M clang/test/SemaOpenACC/compute-construct-async-clause.c
Log Message:
-----------
[OpenACC][CIR] Implement 'async' lowering. (#136626)
Async acts just like num_workers/vector_length in that it gets a new
variant per device_type and is lowered as an operand.
However, it has one additional complication, in that it can have a
variant that has no argument, which produces an attribute with the
correct devicetype.
Additionally, this syncronizes us with the implementation of flang,
which prohibits multiple 'async' clauses per-device_type.
Commit: cfeaa395970b7a2a2f0389d06a20d0970d591807
https://github.com/llvm/llvm-project/commit/cfeaa395970b7a2a2f0389d06a20d0970d591807
Author: Koakuma <koachan at protonmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/Sparc/SparcInstrVIS.td
A llvm/test/CodeGen/SPARC/multiply-extension.ll
M llvm/test/CodeGen/SPARC/smulo-128-legalisation-lowering.ll
M llvm/test/CodeGen/SPARC/umulo-128-legalisation-lowering.ll
Log Message:
-----------
Reapply "[SPARC] Use umulxhi to do extending 64x64->128 multiply when we have VIS3" (#135897) (#136475)
Update the tests to reflect the change in instruction ordering.
Otherwise there are no changes from the previous commit.
This reverts commit 5e9650ec2deb2f2bb6d5ad28e83bb6cd3c4189e4.
Commit: d20604e5b6792bd010dd4dfd36f3e836ae0fe7b2
https://github.com/llvm/llvm-project/commit/d20604e5b6792bd010dd4dfd36f3e836ae0fe7b2
Author: David Green <david.green at arm.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[CostModel] Plumb CostKind into getExtractWithExtendCost (#135523)
This will likely not affect much with the current uses of the function,
but if we have getExtractWithExtendCost we can plumb CostKind through it
in the same way as other costmodel functions.
Commit: e87aa0c6ab7b9d1abbf86e8df84053cd4de92656
https://github.com/llvm/llvm-project/commit/e87aa0c6ab7b9d1abbf86e8df84053cd4de92656
Author: Ivan Butygin <ivan.butygin at gmail.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/Arith/Utils/Utils.h
M mlir/include/mlir/Dialect/Vector/TransformOps/VectorTransformOps.td
M mlir/include/mlir/Dialect/Vector/Transforms/VectorRewritePatterns.h
M mlir/lib/Dialect/Arith/Utils/Utils.cpp
M mlir/lib/Dialect/Vector/TransformOps/VectorTransformOps.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp
M mlir/test/Dialect/Vector/vector-sink-transform.mlir
M mlir/test/Dialect/Vector/vector-sink.mlir
M mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
Log Message:
-----------
[mlir][vector] Sink vector.extract/splat into load/store ops (#134389)
```
vector.load %arg0[%arg1] : memref<?xf32>, vector<4xf32>
vector.extract %0[1] : f32 from vector<4xf32>
```
Gets converted to:
```
%c1 = arith.constant 1 : index
%0 = arith.addi %arg1, %c1 overflow<nsw> : index
%1 = memref.load %arg0[%0] : memref<?xf32>
```
```
%0 = vector.splat %arg2 : vector<1xf32>
vector.store %0, %arg0[%arg1] : memref<?xf32>, vector<1xf32>
```
Gets converted to:
```
memref.store %arg2, %arg0[%arg1] : memref<?xf32>
```
Commit: 278062f119795373c5e43a62280b4b6f2bffbd48
https://github.com/llvm/llvm-project/commit/278062f119795373c5e43a62280b4b6f2bffbd48
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/test/Transforms/CorrelatedValuePropagation/uscmp.ll
Log Message:
-----------
[CVP] Add test showing how a call-site range can pessimize opt (NFC)
Commit: d51b2785abf77978d9218a7b6fb5b8ec6c770c31
https://github.com/llvm/llvm-project/commit/d51b2785abf77978d9218a7b6fb5b8ec6c770c31
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/IR/Instructions.cpp
M llvm/test/Transforms/CorrelatedValuePropagation/uscmp.ll
Log Message:
-----------
[IR] Intersect call and fn range in CallBase::getRange()
To make sure that a larger range on the call-site does not suppress
information from a smaller range at the declaration.
Commit: 980531cac0988e509425e64fbd279ee98e25307c
https://github.com/llvm/llvm-project/commit/980531cac0988e509425e64fbd279ee98e25307c
Author: Luke Lau <luke at igalia.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
Log Message:
-----------
[VPlan] Fix MayReadFromMemory/MayWriteToMemory on VPWidenIntrinsicRecipe (#136684)
These seem to be the wrong way round, e.g. see the definition at
Instruction::mayReadFromMemory().
If an instruction only writes to memory then it's known to not read
memory, and so on.
Only noticed this when using VPWidenIntrinsicRecipe in a local patch and
wondered why it kept on getting DCEd despite the intrinsic writing to
memory.
Commit: c2ae5723b5418fa0f5901f2c21c2c905fa48a498
https://github.com/llvm/llvm-project/commit/c2ae5723b5418fa0f5901f2c21c2c905fa48a498
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/cxx11.cpp
Log Message:
-----------
[clang][bytecode] Allow reinterpret casts from/to the same pointer type (#136692)
Commit: c5a5f4330a0014b9beafef1c75cc66dba917fa09
https://github.com/llvm/llvm-project/commit/c5a5f4330a0014b9beafef1c75cc66dba917fa09
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
Log Message:
-----------
Reapply [ValueTracking] Drop ucmp/scmp from getIntrinsicRange() (NFCI)
Reapply after d51b2785abf77978d9218a7b6fb5b8ec6c770c31, which should
fix optimization regressions.
After #135642 we have a range attribute on the intrinsic declaration,
so we should not need the special handling here.
Commit: 901ac60db7d864c79aa34d93fc46f2635e3afd50
https://github.com/llvm/llvm-project/commit/901ac60db7d864c79aa34d93fc46f2635e3afd50
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
Log Message:
-----------
[RISCV] Use ri.vzip2{a,b} for interleave2 if available (#136364)
If XRivosVizip is available, the ri.vzip2a and ri.vzip2b instructions
can be used perform a interleave shuffle. This patch only effects the
intrinsic lowering (and thus scalable vectors). Fixed vectors go through
shuffle lowering and the zip2a (but not zip2b) case is already handled
there..
Commit: f010725e392c50700dec0dfe7ef3ff1ecfc517bd
https://github.com/llvm/llvm-project/commit/f010725e392c50700dec0dfe7ef3ff1ecfc517bd
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td
M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
M mlir/test/Dialect/Linalg/canonicalize.mlir
M mlir/test/Dialect/Linalg/vectorize-tensor-extract.mlir
Log Message:
-----------
[mlir][linalg] Add folder for `linalg.index` (#136640)
We know that the index of unit dims is always 0.
Commit: 0252d338fa9f4f2f1262b5f7d8158e3f5857fcaf
https://github.com/llvm/llvm-project/commit/0252d338fa9f4f2f1262b5f7d8158e3f5857fcaf
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/reused-scalar-repeated-in-node.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vectorizable-selects-uniform-cmps.ll
M llvm/test/Transforms/SLPVectorizer/X86/full-match-with-poison-scalar.ll
M llvm/test/Transforms/SLPVectorizer/X86/full-matched-bv-with-subvectors.ll
M llvm/test/Transforms/SLPVectorizer/X86/matched-nodes-updated.ll
M llvm/test/Transforms/SLPVectorizer/X86/memory-runtime-checks.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi-extracts-bv-combined.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduced-val-vectorized-in-transform.ll
M llvm/test/Transforms/SLPVectorizer/icmp-altopcode-after-reordering.ll
M llvm/test/Transforms/SLPVectorizer/reordering-single-phi.ll
Log Message:
-----------
[SLP]Model single unique value insert + shuffle as splat + select, where profitable
When we have the remaining unique scalar, that should be inserted into
non-poison vector and into non-zero position:
```
%vec1 = insertelement %vec, %v, pos1
%res = shuffle %vec1, poison, <0, 1, 2,..., pos1, pos1 + 1, ..., pos1,
...>
```
better to estimate if it is profitable to model it as is or model it as:
```
%bv = insertelement poison, %v, 0
%splat = shuffle %bv, poison, <poison, ..., 0, ..., 0, ...>
%res = shuffle %vec, %splat, <0, 1, 2,..., pos1 + VF, pos1 + 1, ...>
```
Reviewers: preames, hiraditya, RKSimon
Reviewed By: preames
Pull Request: https://github.com/llvm/llvm-project/pull/136590
Commit: a5f65e5a01987f5981ece8208cadd079ca2c8e54
https://github.com/llvm/llvm-project/commit/a5f65e5a01987f5981ece8208cadd079ca2c8e54
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-04-22 (Tue, 22 Apr 2025)
Changed paths:
M clang-tools-extra/clangd/unittests/InlayHintTests.cpp
M clang-tools-extra/clangd/unittests/XRefsTests.cpp
M clang/cmake/caches/Fuchsia-stage2.cmake
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/BuiltinHeaders.def
M clang/include/clang/Basic/BuiltinsAArch64.def
M clang/include/clang/Basic/BuiltinsARM.def
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/Driver/Distro.h
M clang/include/clang/Driver/Options.td
M clang/include/clang/Parse/Parser.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/Decl.cpp
M clang/lib/AST/RecordLayoutBuilder.cpp
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M clang/lib/CIR/Dialect/IR/CIRMemorySlot.cpp
M clang/lib/CodeGen/Targets/DirectX.cpp
M clang/lib/Driver/Distro.cpp
M clang/lib/Headers/arm_acle.h
M clang/lib/Index/IndexBody.cpp
M clang/lib/Parse/ParseExpr.cpp
M clang/lib/Sema/SemaARM.cpp
M clang/lib/Sema/SemaOpenACCClause.cpp
M clang/test/AST/ByteCode/cxx11.cpp
M clang/test/AST/ast-dump-recovery.cpp
M clang/test/AST/new-unknown-type.cpp
M clang/test/CIR/CodeGenOpenACC/kernels.c
M clang/test/CIR/CodeGenOpenACC/parallel.c
M clang/test/CIR/CodeGenOpenACC/serial.c
A clang/test/CodeGen/arm-former-microsoft-intrinsics-header-warning.c
A clang/test/CodeGen/arm-former-microsoft-intrinsics.c
M clang/test/CodeGen/arm-microsoft-intrinsics.c
A clang/test/CodeGen/arm64-former-microsoft-intrinsics-header-warning.c
A clang/test/CodeGen/arm64-former-microsoft-intrinsics.c
M clang/test/CodeGen/arm64-microsoft-intrinsics.c
M clang/test/CodeGen/builtins-arm-microsoft.c
M clang/test/CodeGenHLSL/builtins/AppendStructuredBuffer-elementtype.hlsl
M clang/test/CodeGenHLSL/builtins/ConsumeStructuredBuffer-elementtype.hlsl
M clang/test/CodeGenHLSL/builtins/RWStructuredBuffer-elementtype.hlsl
M clang/test/CodeGenHLSL/builtins/StructuredBuffer-elementtype.hlsl
M clang/test/Driver/cl-options.c
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Headers/Inputs/include/stdint.h
M clang/test/Headers/ms-intrin.cpp
M clang/test/Parser/cxx-concepts-requires-clause.cpp
M clang/test/Preprocessor/riscv-target-features.c
A clang/test/SemaCXX/cxx20-c99-designator.cpp
M clang/test/SemaCXX/decltype.cpp
M clang/test/SemaCXX/windows-Wpadded-bitfield.cpp
M clang/test/SemaOpenACC/compute-construct-async-clause.c
M clang/unittests/AST/AttrTest.cpp
M compiler-rt/test/profile/AIX/pgo-lto-bcdtor-function-section.test
M flang/include/flang/Lower/DirectivesCommon.h
M flang/include/flang/Optimizer/Builder/DirectivesCommon.h
M flang/include/flang/Optimizer/Dialect/CUF/CUFOps.td
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Optimizer/Dialect/CUF/CUFOps.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-acc-structure.cpp
M flang/test/Lower/CUDA/cuda-kernel-loop-directive.cuf
M flang/test/Lower/OpenACC/acc-bounds.f90
M flang/test/Lower/OpenACC/acc-enter-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-enter-data.f90
A flang/test/Parser/OpenMP/cancel.f90
M flang/test/Semantics/OpenACC/acc-kernels.f90
M flang/test/Semantics/OpenACC/acc-parallel.f90
M flang/test/Semantics/OpenACC/acc-serial.f90
M lld/ELF/ICF.cpp
M lld/ELF/SymbolTable.cpp
M lld/ELF/SymbolTable.h
A lld/test/ELF/aarch64-got-merging-icf.s
M lld/test/ELF/icf-preemptible.s
M lldb/docs/resources/build.rst
M lldb/include/lldb/Core/IOHandler.h
M lldb/include/lldb/Host/Config.h.cmake
M lldb/include/lldb/Host/Editline.h
M lldb/include/lldb/Interpreter/CommandInterpreter.h
M lldb/include/lldb/Target/Statistics.h
M lldb/source/Core/DataFileCache.cpp
M lldb/source/Core/Debugger.cpp
M lldb/source/Core/IOHandler.cpp
M lldb/source/Host/common/Editline.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.h
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
M lldb/source/Plugins/UnwindAssembly/x86/UnwindAssembly-x86.cpp
M lldb/source/Symbol/DWARFCallFrameInfo.cpp
M lldb/source/Symbol/UnwindPlan.cpp
M lldb/source/Target/Statistics.cpp
M lldb/test/API/commands/statistics/basic/TestStats.py
M lldb/test/API/terminal/TestEditline.py
M lldb/test/Shell/Unwind/Inputs/eh-frame-small-fde.s
M lldb/test/Shell/Unwind/eh-frame-small-fde.test
M lldb/unittests/Symbol/UnwindPlanTest.cpp
M llvm/docs/LangRef.rst
M llvm/docs/RISCVUsage.rst
M llvm/include/llvm/Analysis/LazyBlockFrequencyInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/Frontend/Directive/DirectiveBase.td
M llvm/include/llvm/Frontend/OpenACC/ACC.td
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/IntrinsicsPowerPC.td
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Support/Caching.h
M llvm/include/llvm/TableGen/DirectiveEmitter.h
M llvm/lib/Analysis/AliasAnalysis.cpp
M llvm/lib/Analysis/Analysis.cpp
M llvm/lib/Analysis/AssumptionCache.cpp
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/BlockFrequencyInfo.cpp
M llvm/lib/Analysis/BranchProbabilityInfo.cpp
M llvm/lib/Analysis/CallGraph.cpp
M llvm/lib/Analysis/CycleAnalysis.cpp
M llvm/lib/Analysis/DXILMetadataAnalysis.cpp
M llvm/lib/Analysis/DXILResource.cpp
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/lib/Analysis/DomPrinter.cpp
M llvm/lib/Analysis/DominanceFrontier.cpp
M llvm/lib/Analysis/GlobalsModRef.cpp
M llvm/lib/Analysis/IRSimilarityIdentifier.cpp
M llvm/lib/Analysis/IVUsers.cpp
M llvm/lib/Analysis/LazyBlockFrequencyInfo.cpp
M llvm/lib/Analysis/LazyValueInfo.cpp
M llvm/lib/Analysis/LoopInfo.cpp
M llvm/lib/Analysis/LoopPass.cpp
M llvm/lib/Analysis/MemoryDependenceAnalysis.cpp
M llvm/lib/Analysis/MemorySSA.cpp
M llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
M llvm/lib/Analysis/OptimizationRemarkEmitter.cpp
M llvm/lib/Analysis/PhiValues.cpp
M llvm/lib/Analysis/PostDominators.cpp
M llvm/lib/Analysis/ProfileSummaryInfo.cpp
M llvm/lib/Analysis/RegionInfo.cpp
M llvm/lib/Analysis/RegionPrinter.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp
M llvm/lib/Analysis/ScopedNoAliasAA.cpp
M llvm/lib/Analysis/StackSafetyAnalysis.cpp
M llvm/lib/Analysis/StaticDataProfileInfo.cpp
M llvm/lib/Analysis/TargetLibraryInfo.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/TypeBasedAliasAnalysis.cpp
M llvm/lib/Analysis/UniformityAnalysis.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CGData/CodeGenData.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/Debuginfod/Debuginfod.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/LTO/LTOBackend.cpp
M llvm/lib/Support/Caching.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
M llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/BPF/BPFTargetTransformInfo.h
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.h
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
M llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h
M llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.cpp
M llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h
M llvm/lib/Target/Mips/MipsTargetTransformInfo.cpp
M llvm/lib/Target/Mips/MipsTargetTransformInfo.h
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/NVPTX/NVPTXUtilities.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.h
M llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVSystemOperands.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
M llvm/lib/Target/SPIRV/SPIRVTargetTransformInfo.h
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/Sparc/SparcInstrVIS.td
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
M llvm/lib/Target/VE/VETargetTransformInfo.h
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Analysis/CostModel/AArch64/vector-select.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
A llvm/test/CodeGen/AMDGPU/do-not-fold-copy.mir
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx942.ll
R llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.fpmath.ll
A llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.path.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-store.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
A llvm/test/CodeGen/AMDGPU/insert-waitcnts-gfx12-wbinv.mir
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/sdag-print-divergence.ll
A llvm/test/CodeGen/AMDGPU/si-instr-info-vopc-exec.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-global-inv-wb.mir
M llvm/test/CodeGen/NVPTX/bug21465.ll
M llvm/test/CodeGen/NVPTX/forward-ld-param.ll
M llvm/test/CodeGen/NVPTX/lower-args-gridconstant.ll
M llvm/test/CodeGen/NVPTX/lower-args.ll
M llvm/test/CodeGen/NVPTX/lower-byval-args.ll
A llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
M llvm/test/CodeGen/PowerPC/dmf-outer-product.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/features-info.ll
M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
A llvm/test/CodeGen/RISCV/xqcia.ll
A llvm/test/CodeGen/SPARC/multiply-extension.ll
M llvm/test/CodeGen/SPARC/smulo-128-legalisation-lowering.ll
M llvm/test/CodeGen/SPARC/umulo-128-legalisation-lowering.ll
M llvm/test/CodeGen/SPIRV/pointers/getelementptr-downcast-struct.ll
M llvm/test/CodeGen/SPIRV/pointers/getelementptr-downcast-vector.ll
A llvm/test/CodeGen/SPIRV/pointers/store-struct.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
A llvm/test/Instrumentation/MemorySanitizer/X86/avx512fp16-arith-intrinsics.ll
A llvm/test/Instrumentation/MemorySanitizer/X86/avx512fp16-arith-vl-intrinsics.ll
A llvm/test/Instrumentation/MemorySanitizer/X86/avx512fp16-intrinsics.ll
M llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
M llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
M llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/test/MC/RISCV/machine-csr-names.s
M llvm/test/MC/RISCV/rv32-machine-csr-names.s
M llvm/test/TableGen/VarLenDecoder.td
M llvm/test/Transforms/CorrelatedValuePropagation/uscmp.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-intrinsic-calls.ll
M llvm/test/Transforms/LowerTypeTests/aarch64-jumptable.ll
M llvm/test/Transforms/LowerTypeTests/cfi-direct-call1.ll
M llvm/test/Transforms/LowerTypeTests/function-arm-thumb.ll
M llvm/test/Transforms/LowerTypeTests/function-thumb-bti.ll
M llvm/test/Transforms/LowerTypeTests/function.ll
M llvm/test/Transforms/LowerTypeTests/x86-jumptable.ll
A llvm/test/Transforms/MemProfContextDisambiguation/mergenodes.ll
A llvm/test/Transforms/MemProfContextDisambiguation/mergenodes2.ll
M llvm/test/Transforms/MemProfContextDisambiguation/overlapping-contexts.ll
M llvm/test/Transforms/MergeFunc/cfi-thunk-merging.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/reused-scalar-repeated-in-node.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vectorizable-selects-uniform-cmps.ll
M llvm/test/Transforms/SLPVectorizer/X86/full-match-with-poison-scalar.ll
M llvm/test/Transforms/SLPVectorizer/X86/full-matched-bv-with-subvectors.ll
M llvm/test/Transforms/SLPVectorizer/X86/matched-nodes-updated.ll
M llvm/test/Transforms/SLPVectorizer/X86/memory-runtime-checks.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi-extracts-bv-combined.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduced-val-vectorized-in-transform.ll
M llvm/test/Transforms/SLPVectorizer/icmp-altopcode-after-reordering.ll
M llvm/test/Transforms/SLPVectorizer/reordering-single-phi.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/nvptx-basic.ll.expected
M llvm/tools/gold/gold-plugin.cpp
M llvm/tools/llvm-lto2/llvm-lto2.cpp
M llvm/unittests/Support/CMakeLists.txt
A llvm/unittests/Support/Caching.cpp
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
M llvm/utils/TableGen/Basic/DirectiveEmitter.cpp
M llvm/utils/gn/secondary/llvm/lib/Target/AArch64/Disassembler/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Support/BUILD.gn
M mlir/include/mlir/Dialect/Arith/Utils/Utils.h
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/include/mlir/Dialect/SMT/IR/SMTAttributes.td
M mlir/include/mlir/Dialect/Vector/TransformOps/VectorTransformOps.td
M mlir/include/mlir/Dialect/Vector/Transforms/VectorRewritePatterns.h
M mlir/include/mlir/IR/Builders.h
M mlir/include/mlir/IR/BuiltinAttributes.td
M mlir/include/mlir/TableGen/AttrOrTypeDef.h
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/Dialect/Arith/Utils/Utils.cpp
M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
M mlir/lib/Dialect/SMT/IR/SMTAttributes.cpp
M mlir/lib/Dialect/Vector/TransformOps/VectorTransformOps.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp
M mlir/lib/ExecutionEngine/CudaRuntimeWrappers.cpp
M mlir/lib/IR/Builders.cpp
M mlir/lib/Interfaces/ControlFlowInterfaces.cpp
M mlir/lib/TableGen/AttrOrTypeDef.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/lib/Target/LLVMIR/Dialect/GPU/SelectObjectAttr.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/test/Dialect/EmitC/transforms.mlir
M mlir/test/Dialect/Linalg/canonicalize.mlir
M mlir/test/Dialect/Linalg/vectorize-tensor-extract.mlir
M mlir/test/Dialect/SCF/invalid.mlir
M mlir/test/Dialect/Vector/vector-sink-transform.mlir
M mlir/test/Dialect/Vector/vector-sink.mlir
A mlir/test/Integration/GPU/CUDA/concurrent-kernels.mlir
M mlir/test/Target/Cpp/expressions.mlir
M mlir/test/Target/LLVMIR/gpu.mlir
M mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
A mlir/test/mlir-tblgen/apint-param-error.td
M mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp
M offload/DeviceRTL/CMakeLists.txt
M offload/DeviceRTL/src/Kernel.cpp
M offload/DeviceRTL/src/Mapping.cpp
M offload/include/Shared/Environment.h
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
A utils/bazel/llvm-project-overlay/libc/test/include/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/python/BUILD.bazel
Log Message:
-----------
Rebase
Created using spr 1.3.5
Compare: https://github.com/llvm/llvm-project/compare/bc22a15eb2e7...a5f65e5a0198
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