[all-commits] [llvm/llvm-project] e87aa0: [mlir][vector] Sink vector.extract/splat into load...

[Ivan Butygin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e87aa0c6ab7b9d1abbf86e8df84053cd4de92656
      https://github.com/llvm/llvm-project/commit/e87aa0c6ab7b9d1abbf86e8df84053cd4de92656
  Author: Ivan Butygin <ivan.butygin at gmail.com>
  Date:   2025-04-22 (Tue, 22 Apr 2025)

  Changed paths:
    M mlir/include/mlir/Dialect/Arith/Utils/Utils.h
    M mlir/include/mlir/Dialect/Vector/TransformOps/VectorTransformOps.td
    M mlir/include/mlir/Dialect/Vector/Transforms/VectorRewritePatterns.h
    M mlir/lib/Dialect/Arith/Utils/Utils.cpp
    M mlir/lib/Dialect/Vector/TransformOps/VectorTransformOps.cpp
    M mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp
    M mlir/test/Dialect/Vector/vector-sink-transform.mlir
    M mlir/test/Dialect/Vector/vector-sink.mlir
    M mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp

  Log Message:
  -----------
  [mlir][vector] Sink vector.extract/splat into load/store ops (#134389)

```
vector.load %arg0[%arg1] : memref<?xf32>, vector<4xf32>
vector.extract %0[1] : f32 from vector<4xf32>
```
Gets converted to:
```
%c1 = arith.constant 1 : index
%0 = arith.addi %arg1, %c1 overflow<nsw> : index
%1 = memref.load %arg0[%0] : memref<?xf32>
```

```
%0 = vector.splat %arg2 : vector<1xf32>
vector.store %0, %arg0[%arg1] : memref<?xf32>, vector<1xf32>
```
Gets converted to:
```
memref.store %arg2, %arg0[%arg1] : memref<?xf32>
```



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