[all-commits] [llvm/llvm-project] 698cd4: [RISCV] Fix Lsb > Msb case in (sra (sext_inreg X, ...

[Jim Lin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 698cd48db9c2058442e5e6355a77e91e3456ec2c
      https://github.com/llvm/llvm-project/commit/698cd48db9c2058442e5e6355a77e91e3456ec2c
  Author: Jim Lin <jim at andestech.com>
  Date:   2025-04-22 (Tue, 22 Apr 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll

  Log Message:
  -----------
  [RISCV] Fix Lsb > Msb case in (sra (sext_inreg X, _), C) for th.ext (#136287)

According the
[spec](https://github.com/XUANTIE-RV/thead-extension-spec/releases/tag/2.3.0),
the operation of `th.ext rd, rs1, msb, lsb` is

  reg[rd] := sign_extend(reg[rs1][msb:lsb])

The spec doesn't specify if lsb is greater than msb.

I don't think lsb can be greater than msb. So that If the shift-right
amount is greater than msb, we can set lsb equal to msb to extract the
bit rs1[msb] and sign-extend it.



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