[all-commits] [llvm/llvm-project] 0e3e0b: [RISCV] Add processor definition for XiangShan-Kun...

[Chyaka via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0e3e0bf42c25b280d8caa455c6ae7e4a04d3667a
      https://github.com/llvm/llvm-project/commit/0e3e0bf42c25b280d8caa455c6ae7e4a04d3667a
  Author: Chyaka <lilium23187 at gmail.com>
  Date:   2025-04-21 (Mon, 21 Apr 2025)

  Changed paths:
    M clang/test/Driver/riscv-cpus.c
    M clang/test/Misc/target-invalid-cpu-note/riscv.c
    M llvm/docs/ReleaseNotes.md
    M llvm/lib/Target/RISCV/RISCVProcessors.td

  Log Message:
  -----------
  [RISCV] Add processor definition for XiangShan-KunMingHu-V2R2 (#123193)

XiangShan-KunMingHu is the third generation of Open-source
high-performance RISC-V processor developed by Beijing Institute of Open
Source Chip (BOSC) , and its latest version is V2R2.

The KunMingHu manual is now available at
https://github.com/OpenXiangShan/XiangShan-User-Guide/releases.
It will be updated on the official XiangShan documentation site:
https://docs.xiangshan.cc/zh-cn/latest

You can find the corresponding ISA extension from the XiangShan Github
repository:
https://github.com/OpenXiangShan/XiangShan/blob/master/src/main/scala/xiangshan/Parameters.scala

If you want to track the latest performance data of KunMingHu, please
check XiangShan Biweekly: https://docs.xiangshan.cc/zh-cn/latest/blog

This PR adds the processor definition for KunMingHu V2R2, developed by
the XSCC team https://github.com/orgs/OpenXiangShan/teams/xscc.

The scheduling model for XiangShan-KunMingHu V2R2 will be submitted in a
subsequent PR.

---------

Co-authored-by: Shenglin Tang <tangshenglin at ict.ac.cn>
Co-authored-by: Xu, Zefan <ceba_robot at outlook.com>
Co-authored-by: Tang Haojin <tanghaojin at outlook.com>



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