[all-commits] [llvm/llvm-project] 1f224d: [DebugInfo][IndVarSimplify] Propagate source loc w...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Fri Apr 18 11:27:02 PDT 2025
Branch: refs/heads/users/alexey-bataev/spr/slpimprove-reordering-of-the-alternate-nodes
Home: https://github.com/llvm/llvm-project
Commit: 1f224d889dfa89a293e3efa5b04740f634454370
https://github.com/llvm/llvm-project/commit/1f224d889dfa89a293e3efa5b04740f634454370
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyIndVar.cpp
A llvm/test/Transforms/IndVarSimplify/debugloc-rem-subst.ll
Log Message:
-----------
[DebugInfo][IndVarSimplify] Propagate source loc when simplifying rem (#135399)
When IndVarSimplify simplifies a rem of the induction variable to a cmp
and select, only the select currently receives the rem's source
location; this patch propagates it to the cmp as well.
Found using https://github.com/llvm/llvm-project/pull/107279.
Commit: 8210ca019839fc5430b3a95d7caf5c829df3232a
https://github.com/llvm/llvm-project/commit/8210ca019839fc5430b3a95d7caf5c829df3232a
Author: Koakuma <koachan at protonmail.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/Sparc/SparcISelLowering.h
M llvm/lib/Target/Sparc/SparcInstrVIS.td
A llvm/test/CodeGen/SPARC/ctlz.ll
Log Message:
-----------
[SPARC] Use lzcnt to implement CTLZ when we have VIS3
Reviewers: s-barannikov, brad0, rorth
Reviewed By: s-barannikov
Pull Request: https://github.com/llvm/llvm-project/pull/135715
Commit: 2ef01048624dc2a564d5925d082a72a51bb97c48
https://github.com/llvm/llvm-project/commit/2ef01048624dc2a564d5925d082a72a51bb97c48
Author: Koakuma <koachan at protonmail.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/Sparc/SparcInstrVIS.td
A llvm/test/CodeGen/SPARC/bitcast.ll
Log Message:
-----------
[SPARC] Use native bitcast instructions when we have VIS3
Reviewers: brad0, s-barannikov, rorth
Reviewed By: s-barannikov
Pull Request: https://github.com/llvm/llvm-project/pull/135716
Commit: 52e10e6c3bad782380c8a931aabca2800b53a85d
https://github.com/llvm/llvm-project/commit/52e10e6c3bad782380c8a931aabca2800b53a85d
Author: Arvind Sudarsanam <arvind.sudarsanam at intel.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M clang/docs/ClangOffloadPackager.rst
M clang/test/Driver/clang-sycl-linker-test.cpp
M clang/test/Driver/linker-wrapper.c
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M clang/tools/clang-sycl-linker/ClangSYCLLinker.cpp
M llvm/lib/Object/OffloadBinary.cpp
Log Message:
-----------
[SYCL] Add clang-linker-wrapper changes to call clang-sycl-linker for SYCL offloads (#135683)
This PR is one of the many PRs in the SYCL upstreaming effort focusing
on device code linking during the SYCL offload compilation process. RFC:
https://discourse.llvm.org/t/rfc-offloading-design-for-sycl-offload-kind-and-spir-targets/74088
Approved PRs so far:
1. [Clang][SYCL] Introduce clang-sycl-linker to link SYCL offloading
device code (Part 1 of many) -
[Link](https://github.com/llvm/llvm-project/pull/112245)
2. [clang-sycl-linker] Replace llvm-link with API calls -
[Link](https://github.com/llvm/llvm-project/pull/133797)
3. [SYCL][SPIR-V Backend][clang-sycl-linker] Add SPIR-V backend support
inside clang-sycl-linker -
[Link](https://github.com/llvm/llvm-project/pull/133967)
This PR adds SYCL device code linking support to clang-linker-wrapper.
### Summary for this PR
Device code linking happens inside clang-linker-wrapper. In the current
implementation, clang-linker-wrapper does the following:
1. Extracts device code. Input_1, Input_2,.....
5. Group device code according to target devices Inputs[triple_1] = ....
Inputs[triple_2] = ....
6. For each group, i.e. Inputs[triple_i], a. Gather all the offload
kinds found inside those inputs in ActiveOffloadKinds b. Link all images
inside Inputs[triple_i] by calling clang --target=triple_i .... c.
Create a copy of that linked image for each offload kind and add it to
Output[Kind] list.
In SYCL compilation flow, there is a deviation in Step 3b. We call
device code splitting inside the 'clang --target=triple_i ....' call and
the output is now a 'packaged' file containing multiple device images.
This deviation requires us to capture the OffloadKind during the linking
stage and pass it along to the linking function (clang), so that clang
can be called with a unique option '--sycl-link' that will help us to
call 'clang-sycl-linker' under the hood (clang-sycl-linker will do SYCL
specific linking).
Our current objective is to implement an end-to-end SYCL offloading flow
and get it working. We will eventually merge our approach with the
community flow.
Thanks
---------
Signed-off-by: Arvind Sudarsanam <arvind.sudarsanam at intel.com>
Commit: 9ed4c705ac1c5c8797f328694f6cd22fbcdae03b
https://github.com/llvm/llvm-project/commit/9ed4c705ac1c5c8797f328694f6cd22fbcdae03b
Author: Florian Mayer <fmayer at google.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M clang/lib/CodeGen/SanitizerMetadata.cpp
M clang/test/CodeGen/memtag-globals.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/unittests/IR/VerifierTest.cpp
Log Message:
-----------
[MTE] decide whether to tag global in AsmPrinter (#135891)
there are llvm passes that would invalidate the decision we make in
clang.
Commit: 6bac20b391edce2bde348e59f5be2143157304b5
https://github.com/llvm/llvm-project/commit/6bac20b391edce2bde348e59f5be2143157304b5
Author: Florian Mayer <fmayer at google.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M clang/test/CodeGen/memtag-globals-asm.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
Log Message:
-----------
[MTE] do not tag zero sized globals (#136020)
Commit: 386cc00d8d0a8c211b3d25d08fce4c7e6ae36059
https://github.com/llvm/llvm-project/commit/386cc00d8d0a8c211b3d25d08fce4c7e6ae36059
Author: Chao Chen <chao.chen at intel.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td
Log Message:
-----------
[MLIR][XeGPU] Update XeGPU doc (#136155)
Commit: 7866fc2bd9f5e87ffdccecd06f5f877b81218bcd
https://github.com/llvm/llvm-project/commit/7866fc2bd9f5e87ffdccecd06f5f877b81218bcd
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int.ll
Log Message:
-----------
[RISCV] Rewrite vrgather.vx undef, (vmv.s.x), 0, v0 as vmv.v.x (#136010)
This extends the DAG combine introduced in 336b2909 to handle the case
where the prior value is defined by a vmv.s.x instead of a vmv.v.x. If
the vrgather splats the single source element, and has no passthru we
can replace it with a vmv.v.x - which will in turn usually get folded
into a vmerge if a select follows.
Commit: 3133c956c57c5b952d3289323891dcdc252ea333
https://github.com/llvm/llvm-project/commit/3133c956c57c5b952d3289323891dcdc252ea333
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M clang/tools/clang-sycl-linker/ClangSYCLLinker.cpp
Log Message:
-----------
[clang-sycl-linker] Fix a warning
This patch fixes:
clang/tools/clang-sycl-linker/ClangSYCLLinker.cpp:368:14: error:
moving a local object in a return statement prevents copy elision
[-Werror,-Wpessimizing-move]
Commit: f9729859446180c1f0afc386513f7476f5f220e0
https://github.com/llvm/llvm-project/commit/f9729859446180c1f0afc386513f7476f5f220e0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineGatherScatter - use FoldConstantArithmetic for truncation of constant build vectors (#136033)
No need to explicitly check with BuildVectorSDNode::isConstant - FoldConstantArithmetic can handle this, including through bitcasts etc.
Commit: d56afced16f4274c1b142a77a3282760d051cea0
https://github.com/llvm/llvm-project/commit/d56afced16f4274c1b142a77a3282760d051cea0
Author: Nicolas van Kempen <nvankemp at gmail.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M clang-tools-extra/test/clang-tidy/checkers/bugprone/misplaced-operator-in-strlen-in-alloc.c
M clang-tools-extra/test/clang-tidy/checkers/google/explicit-constructor.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/definitions-in-headers.hpp
M clang-tools-extra/test/clang-tidy/checkers/misc/static-assert.c
M clang-tools-extra/test/clang-tidy/checkers/misc/unused-alias-decls.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/unused-using-decls.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/raw-string-literal-delimiter.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/raw-string-literal-replace-shorter.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/shrink-to-fit.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-transparent-functors.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-using.cpp
Log Message:
-----------
[NFC][clang-tidy] Remove {{^}} clauses in some tests (2/N) (#135824)
`check_clang_tidy` now matches full lines only, so `{{^}}` clauses are
no longer necessary.
I am splitting those changes over multiple PRs to make review easier.
Numbering them but the actual order doesn't matter.
Commit: 09680dc18d460d439a89a21c69c64508457602ec
https://github.com/llvm/llvm-project/commit/09680dc18d460d439a89a21c69c64508457602ec
Author: Nicolas van Kempen <nvankemp at gmail.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M clang-tools-extra/test/clang-tidy/checkers/abseil/string-find-startswith.cpp
M clang-tools-extra/test/clang-tidy/checkers/bugprone/reserved-identifier-c.c
M clang-tools-extra/test/clang-tidy/checkers/bugprone/reserved-identifier.cpp
M clang-tools-extra/test/clang-tidy/checkers/google/readability-casting.cpp
M clang-tools-extra/test/clang-tidy/checkers/llvm/qualified-auto.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/static-assert.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/make-unique-macros.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/unary-static-assert.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-bool-literals-ignore-macros.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-override-cxx98.cpp
Log Message:
-----------
[NFC][clang-tidy] Remove {{^}} clauses in some tests (3/N) (#135826)
`check_clang_tidy` now matches full lines only, so `{{^}}` clauses are
no longer necessary.
I am splitting those changes over multiple PRs to make review easier.
Numbering them but the actual order doesn't matter.
Commit: 8b46b98b916050e739cf3b740526e5c2f6936dad
https://github.com/llvm/llvm-project/commit/8b46b98b916050e739cf3b740526e5c2f6936dad
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
A llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.fpmath.ll
Log Message:
-----------
AMDGPU: Fix the double rounding issue in v2f64 -> v2f16 conversion (#135659)
On targets that support v_cvt_pk_f16_f32 instruction, if we make v2f64
-> v2f16 Legal, we will generate the following sequence of instructions:
v_cvt_f32_f64_e32 v1, s[6:7]
v_cvt_f32_f64_e32 v2, s[4:5]
v_cvt_pk_f16_f32 v1, v2, v1
It possibly returns imprecise results due to double rounding. This patch
fixes the issue by not setting the conversion Legal. While we may still
expect the above sequence of code when unsafe fpmath is set, I hope
https://github.com/llvm/llvm-project/pull/134738 can address that
performance concern.
Fixes: SWDEV-523856
Commit: e2c382346f3d3e04a784ad69cbe11ec575b26444
https://github.com/llvm/llvm-project/commit/e2c382346f3d3e04a784ad69cbe11ec575b26444
Author: Daniel Chen <cdchen at ca.ibm.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M flang/lib/Optimizer/CodeGen/Target.cpp
M flang/test/Fir/comdat.fir
M flang/test/Fir/target-rewrite-complex.fir
Log Message:
-----------
[flang] Add 32-bit AIX target specific in order to build 32-bit flang-rt (#136051)
Commit: 206321b47a877e503dc8bfec7037566da61157fc
https://github.com/llvm/llvm-project/commit/206321b47a877e503dc8bfec7037566da61157fc
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M clang/test/Driver/sanitizer-ld.c
Log Message:
-----------
Reapply "[NFC][CFI] Avoid clang error in CFI tests" (#136030) (#136177)
PR #136030 is expected to work after #136032.
This reverts commit 6b0c8c4acd31eba83bf20ab1cf8729b2153e383c.
Commit: 9d5f16308a2a1d778b9022c3a06a3cecc6d5e066
https://github.com/llvm/llvm-project/commit/9d5f16308a2a1d778b9022c3a06a3cecc6d5e066
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M lldb/source/Target/ThreadPlanStepOut.cpp
Log Message:
-----------
[lldb][nfc] Factor out code from ThreadPlanStepOut ctor (#136159)
A future patch will need to create a new constructor for this class, and
extracting code out of its sole existing constructor will make this
easier.
This commit creates a helper function for the code computing the target
frame to step out to.
Commit: 09069088ddf8cf0ae28dce7efe181d63cb132f3a
https://github.com/llvm/llvm-project/commit/09069088ddf8cf0ae28dce7efe181d63cb132f3a
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/test/Assembler/auto_upgrade_nvvm_intrinsics.ll
Log Message:
-----------
[NVPTX] Add auto-upgrade rules for fabs.{f,d,ftz.f} (#136150)
These auto-upgrade rules are required after these intrinsics were
removed in #135644
Commit: da959c92c5a46abd59d38d26d5e0758d48fb7f65
https://github.com/llvm/llvm-project/commit/da959c92c5a46abd59d38d26d5e0758d48fb7f65
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M flang/lib/Optimizer/Transforms/SimplifyIntrinsics.cpp
M flang/test/Transforms/simplifyintrinsics.fir
Log Message:
-----------
[flang] Fixed out-of-bounds access in SimplifyIntrinsics. (#136171)
When the mask is scalar, it is incorrect to cast it to
!fir.box<!fir.array<1xlogical<>>>, because the coordinate
operation will try to read the dim-1 stride from the box
to get the address of the first element. Even though
the stride value will be multiplied by 0, and does not matter,
it is still a read past the allocated box object.
Instead, we should just use box_addr to get the address
of the scalar mask.
Commit: 06963fb9c79ae012de5796b73bb810f8da09728e
https://github.com/llvm/llvm-project/commit/06963fb9c79ae012de5796b73bb810f8da09728e
Author: Brad Smith <brad at comstyle.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M openmp/runtime/src/kmp_config.h.cmake
M openmp/runtime/src/z_Linux_util.cpp
Log Message:
-----------
[OpenMP] Disable load balance on Haiku (#136082)
Haiku does not have a means of retrieving the desired information
and the -1 setting causes the code to fallback anyway.
Commit: 1042d9988764e16e5f6fd984d362042b2fadd0c6
https://github.com/llvm/llvm-project/commit/1042d9988764e16e5f6fd984d362042b2fadd0c6
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx-simulators/invalid-vector/TestDataFormatterLibcxxInvalidVectorSimulator.py
Log Message:
-----------
disable test on older compilers (#136186)
Commit: 85110ccee90380a9d2bc930fae8fb0fa395d58d6
https://github.com/llvm/llvm-project/commit/85110ccee90380a9d2bc930fae8fb0fa395d58d6
Author: Alexander Kornienko <alexfh at google.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP] Replace most uses of for_each with range-for loops. NFC (#136146)
This removes a bit of complexity from the code, where it doesn't seem to
be justified.
Commit: b30100b87f24847afd6407b4939a184ebcf16ef9
https://github.com/llvm/llvm-project/commit/b30100b87f24847afd6407b4939a184ebcf16ef9
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
M llvm/test/MC/RISCV/corev/XCVmem-invalid.s
Log Message:
-----------
[RISCV] Check that both registers of a CV Reg-Reg memory address are GPRs. (#136079)
The assembly parser was checking for any register instead of GPR.
I've removed the custom diagnostic message from the RegReg operand to
give a less confusing error on bad input. The mnemonics are shared with
other encodings that don't use reg-reg memory operand.
I also fixed the parsed operand location, but I'm not sure it matters.
Commit: 295e56c0a63a06f35629c8fbabc880e835146ff1
https://github.com/llvm/llvm-project/commit/295e56c0a63a06f35629c8fbabc880e835146ff1
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/test/Analysis/CostModel/RISCV/shuffle-permute.ll
Log Message:
-----------
[RISCV] Add a couple of cost model tests for shuffles requiring legalization
Commit: 1c35f8145a79b5693b1517d9f4517a1ade5a95e4
https://github.com/llvm/llvm-project/commit/1c35f8145a79b5693b1517d9f4517a1ade5a95e4
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M clang/lib/Sema/SemaARM.cpp
Log Message:
-----------
[clang][SemaARM][NFC] clang-format aarch64 builtin check (#136188)
Going to modify this code so needs formatting.
Signed-off-by: Sarnie, Nick <nick.sarnie at intel.com>
Commit: 9f9c1f93819d441c561d18a73a55bcb6d8a692df
https://github.com/llvm/llvm-project/commit/9f9c1f93819d441c561d18a73a55bcb6d8a692df
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M lldb/include/lldb/Target/ThreadPlanStepOut.h
M lldb/source/Target/ThreadPlanStepOut.cpp
Log Message:
-----------
[lldb][nfc] Split the constructor of ThreadPlanStepOut (#136160)
A subsequent commit will create a new constructor for ThreadPlanStepOut,
which needs to reuse much of the same logic of the existing constructor.
This commit places all of that reusable logic into a separate function.
Commit: 91f9f0fa1e3a776006fcbdb9a9c975682f35b10b
https://github.com/llvm/llvm-project/commit/91f9f0fa1e3a776006fcbdb9a9c975682f35b10b
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M flang/include/flang/Optimizer/Dialect/CUF/CUFOps.td
M flang/lib/Lower/ConvertCall.cpp
M flang/lib/Optimizer/Dialect/CUF/CUFOps.cpp
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/test/Fir/CUDA/cuda-launch.fir
M flang/test/Lower/CUDA/cuda-kernel-calls.cuf
Log Message:
-----------
[flang][cuda] Update cuf.kernel_launch stream and conversion (#136179)
Update `cuf.kernel_launch` to take the stream as a reference. Update the
conversion to insert the `cuf.stream_cast` op so the stream can be set
as dependency.
Commit: 91c2607aace5ce910d0514dc5627651eade9c7d0
https://github.com/llvm/llvm-project/commit/91c2607aace5ce910d0514dc5627651eade9c7d0
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M flang/lib/Lower/OpenACC.cpp
M flang/test/Lower/OpenACC/acc-kernels-loop.f90
M flang/test/Lower/OpenACC/acc-loop.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-private-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-private.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
Log Message:
-----------
[flang][acc] Avoid implicitly privatizing IVs already privatized (#136181)
When generating `acc.loop`, the IV was always implicitly privatized.
However, if the user explicitly privatized it, the IR generated wasn't
quite right.
For example:
```
!$acc loop private(i)
do i = 1, n
a(i) = b(i)
end do
```
The IR generated looked like:
```
%65 = acc.private varPtr(%19#0 : !fir.ref<i32>) -> !fir.ref<i32>
{implicit = true, name = "i"}
%66:2 = hlfir.declare %65 {uniq_name = "_QFEi"} : (!fir.ref<i32>) ->
(!fir.ref<i32>, !fir.ref<i32>)
%67 = acc.private varPtr(%66#0 : !fir.ref<i32>) -> !fir.ref<i32>
{name = "i"}
acc.loop private(@privatization_ref_i32 -> %65 : !fir.ref<i32>,
@privatization_ref_i32 -> %67 : !fir.ref<i32>) control(%arg0 : i32) =
(%c1_i32_46 : i32) to (%c10_i32_47 : i32) step (%c1_i32_48 : i32) {
fir.store %arg0 to %66#0 : !fir.ref<i32>
```
In order to fix this, we first process all of the clauses. Then when
attempting to generate implicit private IV, we look for an already
existing data clause operation.
The result is the following IR:
```
%65 = acc.private varPtr(%19#0 : !fir.ref<i32>) -> !fir.ref<i32>
{name = "i"}
%66:2 = hlfir.declare %65 {uniq_name = "_QFEi"} : (!fir.ref<i32>) ->
(!fir.ref<i32>, !fir.ref<i32>)
acc.loop private(@privatization_ref_i32 -> %65 : !fir.ref<i32>)
control(%arg0 : i32) = (%c1_i32_46 : i32) to (%c10_i32_47 : i32) step
(%c1_i32_48 : i32) {
fir.store %arg0 to %66#0 : !fir.ref<i32>
```
Commit: cdad39b7e007aa2a597f6fbeda28a6b269406916
https://github.com/llvm/llvm-project/commit/cdad39b7e007aa2a597f6fbeda28a6b269406916
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M clang/docs/LibASTImporter.rst
M llvm/docs/ProgrammersManual.rst
Log Message:
-----------
[llvm][docs] Replace `Optional<T>` with `std::optional<T>`
The `llvm::Optional` template is no more. Remove it from the error-handling section of LLVM the programmer's manual and the ASTImporter documentation.
Commit: 30013872190ca05eb00333adb989c9f74b1cf3ac
https://github.com/llvm/llvm-project/commit/30013872190ca05eb00333adb989c9f74b1cf3ac
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.h
A llvm/test/CodeGen/NVPTX/fp128-storage-type.ll
M llvm/test/CodeGen/NVPTX/global-variable-big.ll
Log Message:
-----------
[NVPTX] Basic support for fp128 as a storage type (#136006)
While fp128 operations are not natively supported in hardware, emulation
for them is supported by nvcc. This change adds basic support for
fp128 as a storage type allowing for lowering of IR containing these
types.
Fixes: https://github.com/llvm/llvm-project/issues/95471
Commit: b3a53cc721807f0cd0e3a1e6ddda03a85c774d4f
https://github.com/llvm/llvm-project/commit/b3a53cc721807f0cd0e3a1e6ddda03a85c774d4f
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp
M llvm/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp
Log Message:
-----------
[NFC][TableGen] Code cleanup in Wasm disassember emitter (#135992)
- Use range for loop to iterate over instructions.
- Emit generated code in anonymous namespace instead of `llvm` and
reduce the scope of this to just the type declarations.
- Emit generated tables as static constexpr
- Replace code to search in operand table with `std::search`.
- Skip the last "null" entry in PrefixTable and use range for loop to
search PrefixTable in the .cpp code.
- Do not generate `WebAssemblyInstructionTableSize` definition as its
already defined in the .cpp file.
- Remove {} for single statement loop/if/else bodies.
Commit: 7119b0cfd3678a16664d07e3c7b15399c4b3a321
https://github.com/llvm/llvm-project/commit/7119b0cfd3678a16664d07e3c7b15399c4b3a321
Author: Bangtian Liu <liubangtian at gmail.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M mlir/include/mlir-c/Dialect/Linalg.h
M mlir/lib/Bindings/Python/DialectLinalg.cpp
M mlir/lib/CAPI/Dialect/Linalg.cpp
M mlir/test/python/dialects/linalg/utils.py
Log Message:
-----------
[MLIR][CAPI][python] expose the python binding for linalgOp.getIndexingMaps (#136054)
This PR is mainly about exposing the python bindings for
`linalgOp.getIndexingMaps`.
---------
Signed-off-by: Bangtian Liu <liubangtian at gmail.com>
Commit: 889dad7f40932ea68c9e287e62441507f4f0f261
https://github.com/llvm/llvm-project/commit/889dad7f40932ea68c9e287e62441507f4f0f261
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M libcxxabi/src/demangle/ItaniumDemangle.h
M libcxxabi/src/demangle/Utility.h
M llvm/include/llvm/Demangle/ItaniumDemangle.h
M llvm/include/llvm/Demangle/Utility.h
M llvm/unittests/Demangle/ItaniumDemangleTest.cpp
M llvm/unittests/Demangle/OutputBufferTest.cpp
Log Message:
-----------
[ItaniumDemangle] Add customizable printLeft/printRight APIs to OutputBuffer (#133249)
This patch includes the necessary changes for the LLDB feature proposed
in
https://discourse.llvm.org/t/rfc-lldb-highlighting-function-names-in-lldb-backtraces/85309.
The TL;DR is that we want to track where certain parts of a demangled
name begin/end so we can highlight them in backtraces.
We introduce a new `printLeft`/`printRight` API on `OutputBuffer` that a
client (in our case LLDB) can implement to track state while printing
the demangle tree. This requires redirecting all calls to to
`printLeft`/`printRight` to the `OutputBuffer`. One quirk with the new
API is that `Utility.h` would now depend on `ItaniumDemangle.h` and
vice-versa. To keep these files header-only I made the definitions
`inline` and implement the new APIs in `ItaniumDemangle.h` (so the
definition of `Node` is available to them).
Also introduces `notifyInsertion`/`notifyDeletion` APIs that a client can override to respond to cases where the `OutputBuffer` changes arbitrary parts of the name.
Commit: a0b2a952266a22ed096a7670e33a611c145e3866
https://github.com/llvm/llvm-project/commit/a0b2a952266a22ed096a7670e33a611c145e3866
Author: vporpo <vporpodas at google.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/include/llvm/SandboxIR/Constant.h
M llvm/include/llvm/SandboxIR/Type.h
M llvm/include/llvm/SandboxIR/Value.h
M llvm/lib/SandboxIR/Type.cpp
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
Log Message:
-----------
[SandboxIR] Implement ConstantDataArray functions (#134729)
Mirrors LLVM IR.
Commit: 12becfff035a33141a0b2fb3ea5d5558738ce7eb
https://github.com/llvm/llvm-project/commit/12becfff035a33141a0b2fb3ea5d5558738ce7eb
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M lldb/include/lldb/Target/ThreadPlanStepOut.h
M lldb/source/Target/Thread.cpp
M lldb/source/Target/ThreadPlanStepOut.cpp
Log Message:
-----------
[lldb] Create ThreadPlanStepOut ctor that never skips frames (#136163)
The function QueueThreadPlanForStepOutNoShouldStop has the semantics of
"go this parent frame"; ThreadPlanStepOut needs to respect that, not
skipping over any frames it finds uninteresting. This commit creates a
constructor that respects such instruction.
Commit: e8b506b2469cfe61efdb3c919aaf2d6c54654782
https://github.com/llvm/llvm-project/commit/e8b506b2469cfe61efdb3c919aaf2d6c54654782
Author: Chao Chen <chao.chen at intel.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
M mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
M mlir/test/Dialect/XeGPU/invalid.mlir
M mlir/test/Dialect/XeGPU/ops.mlir
Log Message:
-----------
[MLIR][XeGPU] Switch to 1D representation for SIMT code (#135116)
This PR switches to using a 1D vector to represent SIMT code for simplification.
Commit: 1756fcb8b0192281db641d2038c03b96015e29d4
https://github.com/llvm/llvm-project/commit/1756fcb8b0192281db641d2038c03b96015e29d4
Author: Christopher Ferris <cferris1000 at users.noreply.github.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M compiler-rt/lib/scudo/standalone/CMakeLists.txt
M compiler-rt/lib/scudo/standalone/allocator_config.def
M compiler-rt/lib/scudo/standalone/combined.h
R compiler-rt/lib/scudo/standalone/local_cache.h
M compiler-rt/lib/scudo/standalone/primary32.h
M compiler-rt/lib/scudo/standalone/primary64.h
A compiler-rt/lib/scudo/standalone/size_class_allocator.h
M compiler-rt/lib/scudo/standalone/tests/combined_test.cpp
M compiler-rt/lib/scudo/standalone/tests/primary_test.cpp
M compiler-rt/lib/scudo/standalone/tests/tsd_test.cpp
M compiler-rt/lib/scudo/standalone/tsd.h
M compiler-rt/lib/scudo/standalone/tsd_shared.h
M compiler-rt/lib/scudo/standalone/type_traits.h
Log Message:
-----------
[scudo] Add primary option to enable/disable cache blocks. (#129794)
When configured this way, no primary blocks will be cached except the
batch class. Nothing else changes, no change in the page releasing
strategy.
Commit: 94aa4bfba57cd5df5489ceca5c1b4b59cfcc1288
https://github.com/llvm/llvm-project/commit/94aa4bfba57cd5df5489ceca5c1b4b59cfcc1288
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h
Log Message:
-----------
[NVPTX] Fix a warning
This patch fixes:
llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h:128:21: error: unused
variable '_' [-Werror,-Wunused-variable]
Commit: 209d8c8fa4fe16ef41003da17387f7c271002668
https://github.com/llvm/llvm-project/commit/209d8c8fa4fe16ef41003da17387f7c271002668
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M clang/lib/AST/ItaniumMangle.cpp
M clang/test/CodeGenCXX/mangle-template.cpp
Log Message:
-----------
[clang] fix unresolved dependent template specialization mangling (#136201)
This fixes a regression introduced in #133610 which was reported here
#133610 (comment) and in #136119
This redoes previous attempt in #135111
When mangling a DTST which appears in the prefix,
the template name is not actually relevant, as its prefix is part of the
nested name anyway, and a
substitution is not allowed at that position in any case.
Fixes #136119
Commit: 69b9ddc76418c6f60ce7751efb5beb1f3b3be3ff
https://github.com/llvm/llvm-project/commit/69b9ddc76418c6f60ce7751efb5beb1f3b3be3ff
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h
Log Message:
-----------
[Analysis] Restore the call to reserve (#136215)
commit 47d8fec9b8bd5425af17711317a41743a30a8cef
Author: Kazu Hirata <kazu at google.com>
Date: Wed Apr 16 19:30:01 2025 -0700
has removed the call to reserve here. This patch restores it as
std::vector::insert, called by llvm::append_range, may not be able to
deduce the size of the range. For example, std::vector in libc++
distinguishes has two versions of std::vector::insert depending on
whether the iterator is an input iterator or a foward iterator.
Commit: 20cd74a1c1555385e65d26ff22de7ef75fcb4090
https://github.com/llvm/llvm-project/commit/20cd74a1c1555385e65d26ff22de7ef75fcb4090
Author: Thurston Dang <thurston at google.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M clang/lib/Driver/SanitizerArgs.cpp
M clang/test/Driver/fsanitize.c
Log Message:
-----------
[sanitizer] Apply AlwaysIn/Out in parseSanitizeArgs (#129405)
For backwards compatibility, `parseSanitizeArgs`/`parseSanitizeTrapArgs` had an incomplete refactoring in
https://github.com/llvm/llvm-project/pull/119819, in order to accommodate the special case of vptr in -fsanitize=undefined and its interaction with -fsanitize-trap=undefined. Now that vptr is no longer part of -fsanitize=undefined (https://github.com/llvm/llvm-project/pull/121115), this patch changes parseSanitizeArgs to apply the AlwaysIn/Out invariants in parseSanitizeArgs, which allows simplifying calls to parseSanitizeArgs.
This is not quite NFC: it changes the error message of -fsanitize-trap=vptr.
Commit: 0abf227c13eb80f15659f747094df2db1c34d20d
https://github.com/llvm/llvm-project/commit/0abf227c13eb80f15659f747094df2db1c34d20d
Author: Ivan Butygin <ivan.butygin at gmail.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
M mlir/test/Dialect/AMDGPU/invalid.mlir
M mlir/test/Dialect/AMDGPU/ops.mlir
Log Message:
-----------
[mlir][amdgpu] Add `amdgpu.swizzle_bitmode` op (#135513)
High level wrapper on top of `rocdl.ds_swizzle`. Also some DPP op
cleanup while I'm at here.
Will do lowering in separate PR.
Commit: 2af5e01456954f145f9713c14394ef7f2fbcbebc
https://github.com/llvm/llvm-project/commit/2af5e01456954f145f9713c14394ef7f2fbcbebc
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
Log Message:
-----------
[BOLT][RISCV] Fix MCPlusBuilder instrumentation ifaces (#136211)
a) Due to the different capabilities of the functions implemented,
rename the createCmpJE function
b) Refactor the convertIndirectCallToLoad function to override the
interface.
Patch by WangJee, originally posted in #136129
Commit: 655b9db7b90236342a4085fed1fc910621f835e0
https://github.com/llvm/llvm-project/commit/655b9db7b90236342a4085fed1fc910621f835e0
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/HLFIRTools.h
M flang/lib/Optimizer/Builder/HLFIRTools.cpp
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
M flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
R flang/test/HLFIR/all-elemental.fir
R flang/test/HLFIR/any-elemental.fir
R flang/test/HLFIR/count-elemental.fir
R flang/test/HLFIR/maxloc-elemental.fir
R flang/test/HLFIR/maxval-elemental.fir
R flang/test/HLFIR/minloc-elemental.fir
R flang/test/HLFIR/minval-elemental.fir
A flang/test/HLFIR/simplify-hlfir-intrinsics-all.fir
A flang/test/HLFIR/simplify-hlfir-intrinsics-any.fir
A flang/test/HLFIR/simplify-hlfir-intrinsics-count.fir
A flang/test/HLFIR/simplify-hlfir-intrinsics-maxloc.fir
A flang/test/HLFIR/simplify-hlfir-intrinsics-maxval.fir
A flang/test/HLFIR/simplify-hlfir-intrinsics-minloc.fir
A flang/test/HLFIR/simplify-hlfir-intrinsics-minval.fir
Log Message:
-----------
[flang] Generalized simplification of HLFIR reduction ops. (#136071)
This change generalizes SumAsElemental inlining in
SimplifyHLFIRIntrinsics pass so that it can be applied
to ALL, ANY, COUNT, MAXLOC, MAXVAL, MINLOC, MINVAL, SUM.
This change makes the special handling of the reduction
operations in OptimizedBufferization redundant: once HLFIR
operations are inlined, the hlfir.elemental inlining should
do the rest of the job.
Commit: 9af61f500c438df9bcbe2eab47c89d25cc5db759
https://github.com/llvm/llvm-project/commit/9af61f500c438df9bcbe2eab47c89d25cc5db759
Author: Paul Kirth <paulkirth at google.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M clang/cmake/caches/Fuchsia-stage2.cmake
Log Message:
-----------
Revert "[Fuchsia] Not building llvm-mt when LIBXML2 is not enabled." (#136216)
Reverts llvm/llvm-project#135877
This is causing some problems on Fuchsia's windows CI. We'll need a
different solution to triage other builders.
https://ci.chromium.org/ui/p/fuchsia/builders/toolchain.ci/clang-windows-x64/b8717476961063994817/overview
Commit: f0f55453a2df8c984a7a824bb3face2d7ae18a7d
https://github.com/llvm/llvm-project/commit/f0f55453a2df8c984a7a824bb3face2d7ae18a7d
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h
M llvm/test/CodeGen/NVPTX/fp128-storage-type.ll
Log Message:
-----------
[NVPTX] Address warning and typo in fp128 support (#136207)
Commit: 767c8c1badc03881aa97ed145ed8f0335c5a1d17
https://github.com/llvm/llvm-project/commit/767c8c1badc03881aa97ed145ed8f0335c5a1d17
Author: vporpo <vporpodas at google.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/docs/SandboxIR.md
M llvm/docs/Vectorizers.rst
Log Message:
-----------
[docs][SandboxIR] Fix cross-reference to sandbox vectorizer (#133768)
The cross-reference used to point to a label in the auto-vectorization
document.
Commit: f39242ceed214dfcecd6b33f22f8301ae183c677
https://github.com/llvm/llvm-project/commit/f39242ceed214dfcecd6b33f22f8301ae183c677
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/HLFIRTools.h
M flang/lib/Optimizer/Builder/HLFIRTools.cpp
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
M flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
A flang/test/HLFIR/all-elemental.fir
A flang/test/HLFIR/any-elemental.fir
A flang/test/HLFIR/count-elemental.fir
A flang/test/HLFIR/maxloc-elemental.fir
A flang/test/HLFIR/maxval-elemental.fir
A flang/test/HLFIR/minloc-elemental.fir
A flang/test/HLFIR/minval-elemental.fir
R flang/test/HLFIR/simplify-hlfir-intrinsics-all.fir
R flang/test/HLFIR/simplify-hlfir-intrinsics-any.fir
R flang/test/HLFIR/simplify-hlfir-intrinsics-count.fir
R flang/test/HLFIR/simplify-hlfir-intrinsics-maxloc.fir
R flang/test/HLFIR/simplify-hlfir-intrinsics-maxval.fir
R flang/test/HLFIR/simplify-hlfir-intrinsics-minloc.fir
R flang/test/HLFIR/simplify-hlfir-intrinsics-minval.fir
Log Message:
-----------
Revert "[flang] Generalized simplification of HLFIR reduction ops." (#136218)
Reverts llvm/llvm-project#136071
Commit: 69ade7c090b59373a18c38b2c80c48f97a0afcde
https://github.com/llvm/llvm-project/commit/69ade7c090b59373a18c38b2c80c48f97a0afcde
Author: Elvis Wang <elvis.wang at sifive.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
Log Message:
-----------
[LV] Check if the VF is scalar by VFRange in `handleUncountableEarlyExit`. (#135294)
This patch check if the plan contains scalar VF by VFRange instead of
Plan.
This patch also clamp the range to contains either only scalar or only
vector VFs to prevent mis-compile.
Split from #113903.
Commit: 32311a6b68d3de4642599abe14922c686bdb30fc
https://github.com/llvm/llvm-project/commit/32311a6b68d3de4642599abe14922c686bdb30fc
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/HLFIRTools.h
M flang/lib/Optimizer/Builder/HLFIRTools.cpp
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
M flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
R flang/test/HLFIR/all-elemental.fir
R flang/test/HLFIR/any-elemental.fir
R flang/test/HLFIR/count-elemental.fir
R flang/test/HLFIR/maxloc-elemental.fir
R flang/test/HLFIR/maxval-elemental.fir
R flang/test/HLFIR/minloc-elemental.fir
R flang/test/HLFIR/minval-elemental.fir
A flang/test/HLFIR/simplify-hlfir-intrinsics-all.fir
A flang/test/HLFIR/simplify-hlfir-intrinsics-any.fir
A flang/test/HLFIR/simplify-hlfir-intrinsics-count.fir
A flang/test/HLFIR/simplify-hlfir-intrinsics-maxloc.fir
A flang/test/HLFIR/simplify-hlfir-intrinsics-maxval.fir
A flang/test/HLFIR/simplify-hlfir-intrinsics-minloc.fir
A flang/test/HLFIR/simplify-hlfir-intrinsics-minval.fir
Log Message:
-----------
Reland [flang] Generalized simplification of HLFIR reduction ops. (#136071)
This change generalizes SumAsElemental inlining in
SimplifyHLFIRIntrinsics pass so that it can be applied
to ALL, ANY, COUNT, MAXLOC, MAXVAL, MINLOC, MINVAL, SUM.
This change makes the special handling of the reduction
operations in OptimizedBufferization redundant: once HLFIR
operations are inlined, the hlfir.elemental inlining should
do the rest of the job.
Commit: f0621b31f8baee3013bec74b2789b9d5d9f9d08f
https://github.com/llvm/llvm-project/commit/f0621b31f8baee3013bec74b2789b9d5d9f9d08f
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
Log Message:
-----------
[Vectorize] Fix a warning
This patch fixes:
llvm/lib/Transforms/Vectorize/VPlanTransforms.h:31:1: error: class
'VFRange' was previously declared as a struct; this is valid, but
may result in linker errors under the Microsoft C++ ABI
[-Werror,-Wmismatched-tags]
Commit: bb67de671eeda3b763ed6f1af05bd921b0ad7a29
https://github.com/llvm/llvm-project/commit/bb67de671eeda3b763ed6f1af05bd921b0ad7a29
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/libc_build_rules.bzl
Log Message:
-----------
[libc][bazel] Enforce that libc hand-in-hand libs are headers-only. (#136219)
Extend Bazel rule implementation to enforce that all transitive
dependencies of libc_header_library targets (used to implement
hand-in-hand code sharing via headers) indeed only contain header files.
This fixes Bazel portion of PR #133126.
Commit: 62b9cbd8782b2ded15efed67ae10419e75ea0fa7
https://github.com/llvm/llvm-project/commit/62b9cbd8782b2ded15efed67ae10419e75ea0fa7
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
Log Message:
-----------
[RISCV] Simplify check lines in vector-deinterleave.ll [nfc]
RV32 and RV64 are unused. Output with zvfh vs zvfhmin are the same,
so just use the weaker predicate.
Commit: ebe084f927f14be707d3ca64dab0faaf6c0eee9d
https://github.com/llvm/llvm-project/commit/ebe084f927f14be707d3ca64dab0faaf6c0eee9d
Author: Volodymyr Sapsai <vsapsai at apple.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M clang/lib/Serialization/ASTWriter.cpp
A clang/test/Modules/non-modular-decl-use.c
Log Message:
-----------
[Modules] Fix the inconsistency of which `Decl` should be serialized for an identifier. (#135887)
Fixes the assertion failure
> Assertion failed: (DeclIDs.contains(D) && "Declaration not emitted!"),
function getDeclID, file ASTWriter.cpp, line 6873.
We prepare to serialize a `Decl` by adding it to `DeclIDs` in
`ASTWriter::GetDeclRef`. But the checks before this call aren't the same
as when we are actually serializing a `Decl` in
`ASTIdentifierTableTrait::EmitData` and
`ASTWriter::WriteIdentifierTable`. That's how we can end up serializing
a `Decl` not present in `DeclIDs` and hitting the assertion. With the
assertions disabled clang crashes when trying to use a deserialized null
`Decl`.
Fix by making the code checks before `ASTWriter::GetDeclRef` call
similar to those we have before the serialization.
rdar://139319683
Commit: 7f107c301963ad1070f2130f89655fd94f2c0714
https://github.com/llvm/llvm-project/commit/7f107c301963ad1070f2130f89655fd94f2c0714
Author: Sirish Pande <sirpande at amd.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/IndVarSimplify.cpp
M llvm/test/Transforms/IndVarSimplify/ARM/code-size.ll
M llvm/test/Transforms/IndVarSimplify/ARM/indvar-unroll-imm-cost.ll
M llvm/test/Transforms/IndVarSimplify/exit-count-select.ll
M llvm/test/Transforms/IndVarSimplify/exit_value_test3.ll
M llvm/test/Transforms/IndVarSimplify/finite-exit-comparisons.ll
M llvm/test/Transforms/IndVarSimplify/pr116483.ll
M llvm/test/Transforms/IndVarSimplify/pr63763.ll
M llvm/test/Transforms/IndVarSimplify/replace-loop-exit-folds.ll
M llvm/test/Transforms/IndVarSimplify/sentinel.ll
M llvm/test/Transforms/LoopUnroll/unroll-cleanup.ll
M llvm/test/Transforms/PhaseOrdering/ARM/arm_mean_q7.ll
Log Message:
-----------
[IndVarsSimplify] sinkUnusedInvariants is skipping instructions while sinking. (#135205)
While sinking instructions (that are loop invariant) from preheader to
the exit block, we are skipping instructions due to decrementing
instruction iterator twice.
Commit: ce0c472791647c61f3af97c16a8c61fb351417ea
https://github.com/llvm/llvm-project/commit/ce0c472791647c61f3af97c16a8c61fb351417ea
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/HLFIRTools.h
M flang/lib/Optimizer/Builder/HLFIRTools.cpp
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
M flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
A flang/test/HLFIR/all-elemental.fir
A flang/test/HLFIR/any-elemental.fir
A flang/test/HLFIR/count-elemental.fir
A flang/test/HLFIR/maxloc-elemental.fir
A flang/test/HLFIR/maxval-elemental.fir
A flang/test/HLFIR/minloc-elemental.fir
A flang/test/HLFIR/minval-elemental.fir
R flang/test/HLFIR/simplify-hlfir-intrinsics-all.fir
R flang/test/HLFIR/simplify-hlfir-intrinsics-any.fir
R flang/test/HLFIR/simplify-hlfir-intrinsics-count.fir
R flang/test/HLFIR/simplify-hlfir-intrinsics-maxloc.fir
R flang/test/HLFIR/simplify-hlfir-intrinsics-maxval.fir
R flang/test/HLFIR/simplify-hlfir-intrinsics-minloc.fir
R flang/test/HLFIR/simplify-hlfir-intrinsics-minval.fir
Log Message:
-----------
Revert "Reland [flang] Generalized simplification of HLFIR reduction ops. (#136071)"
This reverts commit 32311a6b68d3de4642599abe14922c686bdb30fc.
Commit: feb1fb5f0473eb949b35fb25e15c4d32465cd6d7
https://github.com/llvm/llvm-project/commit/feb1fb5f0473eb949b35fb25e15c4d32465cd6d7
Author: Chandler Carruth <chandlerc at gmail.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/test/Driver/clang-translation.c
Log Message:
-----------
Make the `-disable-free` flag more full featured (#136213)
This lets us pass `-no-disable-free` to re-enable freeing memory for
example. This is especially helpful for library users of Clang where it
is important to not slowly leak memory.
Commit: afc5cc060b8bc44b5fd3c0a4612ebc1a1dc70826
https://github.com/llvm/llvm-project/commit/afc5cc060b8bc44b5fd3c0a4612ebc1a1dc70826
Author: Michael Liao <michael.hliao at gmail.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/tools/yaml2obj/CMakeLists.txt
Log Message:
-----------
[yaml2obj] Fix shared build. NFC
Commit: 0f5c66c364a6702edf65214a4f975c3e3f326d9a
https://github.com/llvm/llvm-project/commit/0f5c66c364a6702edf65214a4f975c3e3f326d9a
Author: Michael Liao <michael.hliao at gmail.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
Log Message:
-----------
[OpenACC][CIR] Fix build error from CIR upstreaming
- 'DeviceTypeArgument' is defined as 'IdentifierLoc' instead of
'std::pair<IdentifierInfo *, SourceLocation>'.
Commit: 1dbc8ef5538e25f61664d807fda236f7d983cc69
https://github.com/llvm/llvm-project/commit/1dbc8ef5538e25f61664d807fda236f7d983cc69
Author: Oliver Hunt <oliver at apple.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M clang/test/Sema/ptrauth-qualifier.c
M clang/test/Sema/ptrauth.c
M clang/test/SemaObjC/ptrauth-qualifier.m
Log Message:
-----------
[clang][ptrauth] Make ptrauth feature detection tests more robust (#136204)
The existing test behavior checked for a warning being emitted under an
#if, but if the feature detection fails the #if fails and the warning is
not expected in the output.
I've made the test more explicit, and added comments to ensure no one
simply adds/moves any expected output around.
Commit: ca9ec7dfc3a5ebad9e5c25b30511b2ed73287f61
https://github.com/llvm/llvm-project/commit/ca9ec7dfc3a5ebad9e5c25b30511b2ed73287f61
Author: Harald van Dijk <harald.vandijk at codeplay.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M clang/include/clang/AST/RecordLayout.h
M clang/lib/AST/RecordLayoutBuilder.cpp
M clang/test/CodeGen/AArch64/args.cpp
M clang/test/CodeGen/aapcs64-align.cpp
M clang/test/CodeGen/arm-vfp16-arguments2.cpp
Log Message:
-----------
[ARM, AArch64] Fix passing of structures with aligned base classes (#135564)
RecordLayout::UnadjustedAlignment was documented as "Maximum of the
alignments of the record members in characters", but
RecordLayout::getUnadjustedAlignment(), which just returns
UnadjustedAlignment, was documented as getting "the record alignment in
characters, before alignment adjustement." These are not the same thing:
the former excludes alignment of base classes, the latter takes it into
account. ItaniumRecordLayoutBuilder::LayoutBase was setting it according
to the former, but the AAPCS calling convention handling, currently the
only user, relies on it being set according to the latter.
Fixes #135551.
Commit: 5e430afb84c3cbf285d8fe15c0ae23e0920e946b
https://github.com/llvm/llvm-project/commit/5e430afb84c3cbf285d8fe15c0ae23e0920e946b
Author: Fangrui Song <i at maskray.me>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/test/MC/LoongArch/Relocations/relocations.s
M llvm/test/MC/RISCV/fixups-binary-expression.s
M llvm/test/MC/RISCV/function-call.s
M llvm/test/MC/RISCV/linker-relaxation.s
M llvm/test/MC/RISCV/option-exact.s
M llvm/test/MC/RISCV/pseudo-jump.s
M llvm/test/MC/RISCV/relocations.s
M llvm/test/MC/RISCV/tail-call.s
M llvm/test/MC/RISCV/xqcilb-relocations.s
M llvm/test/MC/RISCV/xqcili-relocations.s
Log Message:
-----------
[test] Remove CHECK lines for MCAsmStreamer's fixup output
As mentioned in #136088 , the fixup output is a debug aid and should not
be used to test target-specific relocation generation implementation.
The llvm-mc -filetype=obj output is what truly matters.
Commit: c99ffe58af23251d83073b8ad002536edc3864ae
https://github.com/llvm/llvm-project/commit/c99ffe58af23251d83073b8ad002536edc3864ae
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M clang/lib/Format/FormatToken.h
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Fix a bug in FormatToken::isObjCAccessSpecifier() (#136109)
Fix #136092
Commit: 77721986d8bd48182ba355bf166a5fa3ffbfe6b6
https://github.com/llvm/llvm-project/commit/77721986d8bd48182ba355bf166a5fa3ffbfe6b6
Author: Michael Liao <michael.hliao at gmail.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M clang/unittests/Format/CMakeLists.txt
Log Message:
-----------
[clang-format] Fix shared build. NFC
Commit: b6dff5660092e4814fa2e2cc129ba0d05ce49a52
https://github.com/llvm/llvm-project/commit/b6dff5660092e4814fa2e2cc129ba0d05ce49a52
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
Log Message:
-----------
[RISCV] Add vizip check lines to (de)interleave tests
Reducing churn in advance of a change which makes better use of these.
Note that for very short fixed length shuffles, we already use the
vizip family instructions - but mostly in the form of zipeven/zipodd.
Commit: 50f9b34b5340cfb32d14920bb0d41a90f48ffc40
https://github.com/llvm/llvm-project/commit/50f9b34b5340cfb32d14920bb0d41a90f48ffc40
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-binop-splats.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
M llvm/test/CodeGen/RISCV/rvv/fold-scalar-load-crash.ll
M llvm/test/CodeGen/RISCV/rvv/pr125306.ll
Log Message:
-----------
[RISCV] Prefer vmv.s.x for build_vector a, undef, ..., undef (#136164)
If we have a build vector which could be either a splat or a scalar
insert, prefer the scalar insert. At high LMUL, this reduces vector
register pressure (locally, the use will likely still be aligned), and
the amount of work performed for the splat.
Commit: a04580f71b98bdb12100da66c9975e9a1001b4d6
https://github.com/llvm/llvm-project/commit/a04580f71b98bdb12100da66c9975e9a1001b4d6
Author: Shoreshen <372660931 at qq.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot2.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
Log Message:
-----------
[AMDGPU] Implement vop3p complex pattern optmization for gisel (#130234)
Seeking opportunities to optimize VOP3P instructions by altering opsel,
opsel_hi, neg, neg_hi bits
Tests differences:
1. fix op_sel_hi bit for inline constant:
1. `CodeGen/AMDGPU/packed-fp32.ll`
2. use neg bit to remove xor with 0x80008000
1. `CodeGen/AMDGPU/strict_fsub.f16.ll`
2. `CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fdot2.ll`
3. `CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll`
4. `CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot8.ll`
5. `CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot2.ll`
6. `CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll`
7. `CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot8.ll`
3. Remove xor 0x80008000, and use opsel, opsel_hi to remove alignbit
1. `CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot2.ll`
Commit: e5263e3ec83cf662f945a067ffc83e2ed76d9aed
https://github.com/llvm/llvm-project/commit/e5263e3ec83cf662f945a067ffc83e2ed76d9aed
Author: Shih-Po Hung <shihpo.hung at sifive.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LV][NFC] Clean up tail-folding check for early-exit loops (#133931)
This patch moves the check for a single latch exit from computeMaxVF()
to LoopVectorizationLegality::canFoldTailByMasking(), as it duplicates
the logic when foldTailByMasking() returns false.
It also updates the NoScalarEpilogueNeeded logic to return false for
loops that are neither single-latch-exit nor early-exit. This avoids
applying tail-folding in unsupported cases and prevents triggering
assertions during analysis.
Commit: 0977a7130b291304dae5cfd23575ea3a4b9922ed
https://github.com/llvm/llvm-project/commit/0977a7130b291304dae5cfd23575ea3a4b9922ed
Author: Maksim Panchenko <maks at fb.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M bolt/lib/Core/BinaryEmitter.cpp
M bolt/test/AArch64/lite-mode.s
Log Message:
-----------
[BOLT] Skip FDE emission for patch functions (#136224)
Patch functions are used to fix instructions in the original code, i.e.,
they are not functions in a traditional sense, but rather pieces of
emitted code that are embedded into real functions.
We used to emit FDEs for all functions, including patch functions.
However, FDEs for patches are not only unnecessary, but they can lead to
problems with libraries and runtimes that consume FDEs, e.g. C++
exception handling runtime.
Note that we use named patches to fix function entry points and in that
case they behave more like regular functions. Thus we issue FDEs for
those.
Commit: 5b2c743a2eb012d1e0649324ade83f23c6645a5b
https://github.com/llvm/llvm-project/commit/5b2c743a2eb012d1e0649324ade83f23c6645a5b
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVProfiles.td
Log Message:
-----------
[RISCV][NFC] Add Zicsr to profiles explicitly (#136134)
To avoid some misunstandings though Zicsr is implied by F/D.
Commit: a354564a64c6ab3cafa9e5e2b31f7f14d4e27d45
https://github.com/llvm/llvm-project/commit/a354564a64c6ab3cafa9e5e2b31f7f14d4e27d45
Author: Iris <0.0 at owo.li>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/test/MC/RISCV/rv32xtheadmempair-invalid.s
M llvm/test/MC/RISCV/rv64xtheadmempair-invalid.s
Log Message:
-----------
[RISCV] Strengthen register usage validation for XTheadMemPair loads (#136241)
Closes #136087
https://github.com/XUANTIE-RV/thead-extension-spec/blob/master/xtheadmempair/lwd.adoc
Commit: 594bfadbd683eab5e1cd40a450c25da2834f7768
https://github.com/llvm/llvm-project/commit/594bfadbd683eab5e1cd40a450c25da2834f7768
Author: tangaac <tangyan01 at loongson.cn>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
A llvm/test/CodeGen/LoongArch/lasx/broadcast-load.ll
A llvm/test/CodeGen/LoongArch/lsx/broadcast-load.ll
Log Message:
-----------
[LoongArch] Pre-commit for broadcast load (#136070)
Commit: a3f38f27cd78e1b2753a3f29489094cfd92198fe
https://github.com/llvm/llvm-project/commit/a3f38f27cd78e1b2753a3f29489094cfd92198fe
Author: Shoreshen <372660931 at qq.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot2.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
Log Message:
-----------
Revert "[AMDGPU] Implement vop3p complex pattern optmization for gisel" (#136249)
Reverts llvm/llvm-project#130234
Commit: 64de8528dbd89cdafe32d754f37cf3da4fb5403e
https://github.com/llvm/llvm-project/commit/64de8528dbd89cdafe32d754f37cf3da4fb5403e
Author: Finn Plummer <canadienfinn at gmail.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Parse/ParseHLSLRootSignature.h
M clang/lib/Parse/ParseHLSLRootSignature.cpp
M clang/unittests/Parse/ParseHLSLRootSignatureTest.cpp
M llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h
Log Message:
-----------
[HLSL][RootSignature] Implement initial parsing of the descriptor table clause params (#133800)
- Defines `ParseDescriptorTableClauseParams` to establish the pattern of
how we will parse parameters in root signatures. Namely, to use
recursive descent parsing in a way that follows closely to the EBNF
notation definition in the root signature spec.
- Implements parsing of two param types: `UInt32` and `Register` to
demonstrate the parsing implementation and allow for unit testing
- Changes the calling convention to use `std::optional` return values
instead of boolean error returns and parameters by reference
Part two of implementing:
https://github.com/llvm/llvm-project/issues/126569
---------
Co-authored-by: Finn Plummer <finnplummer at microsoft.com>
Commit: 2721f5af12bdf9af29969a86351fe485af00e648
https://github.com/llvm/llvm-project/commit/2721f5af12bdf9af29969a86351fe485af00e648
Author: Fehr Mathieu <mathieu.fehr at gmail.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/Vector/canonicalize.mlir
Log Message:
-----------
[mlir][vector] Prevent folding of OOB values in insert/extract (#135498)
Out of bound position values should not be folded in vector.extract and
vector.insert operations, as only in bounds constants and -1 are valid.
Fixes #134516
Commit: 6f0a35fbd3296d3f4154e19f189130edcd0980bd
https://github.com/llvm/llvm-project/commit/6f0a35fbd3296d3f4154e19f189130edcd0980bd
Author: Fangrui Song <i at maskray.me>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/include/llvm/MC/MCFixup.h
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
Log Message:
-----------
[AArch64] Use FirsRelocationKind+i fixup kinds to force relocations
For RELA targets, fixup kinds that force relocations (GOT, TLS, ALIGN,
RELAX, etc) can bypass `applyFixup` and be encoded as
`FirstRelocationKind+i`, as seen in LoongArch.
Commit: c134e99a2adf6ac3f0d7a5f15a2f384f174c80a5
https://github.com/llvm/llvm-project/commit/c134e99a2adf6ac3f0d7a5f15a2f384f174c80a5
Author: Finn Plummer <canadienfinn at gmail.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Parse/ParseHLSLRootSignature.h
M clang/lib/Parse/ParseHLSLRootSignature.cpp
M clang/unittests/Parse/ParseHLSLRootSignatureTest.cpp
M llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h
Log Message:
-----------
Revert "[HLSL][RootSignature] Implement initial parsing of the descriptor table clause params" (#136252)
Reverts llvm/llvm-project#133800
Reverting to resolve the introduce naming collisions.
Commit: 23324b8b109aed1f77cb20cef476b795f33b6835
https://github.com/llvm/llvm-project/commit/23324b8b109aed1f77cb20cef476b795f33b6835
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
M llvm/test/MC/RISCV/rv32xtheadmempair-invalid.s
Log Message:
-----------
[RISCV] Move checking for constant 3/4 for XTHeadMemPair to the instruction matching stage. (#136165)
This removes a special case from processInstruction and removes an
untested range diagnostic we would print if the constant didn't fit in 3
bits.
Commit: 8c5a307bd8d406e6167a5cd3ce3c74e2e3bfb2a6
https://github.com/llvm/llvm-project/commit/8c5a307bd8d406e6167a5cd3ce3c74e2e3bfb2a6
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Sema/Overload.h
M clang/lib/Sema/SemaCodeComplete.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/test/CXX/temp/temp.constr/temp.constr.atomic/constrant-satisfaction-conversions.cpp
M clang/test/SemaCUDA/function-overload.cu
M clang/test/SemaCXX/implicit-member-functions.cpp
A clang/test/SemaCXX/overload-resolution-deferred-templates.cpp
M clang/test/SemaTemplate/instantiate-function-params.cpp
M clang/test/Templight/templight-empty-entries-fix.cpp
Log Message:
-----------
[Clang] Bypass TAD during overload resolution if a perfect match exists (#136203)
This implements the same overload resolution behavior as GCC,
as described in https://wg21.link/p3606 (section 1-2, not 3)
If during overload resolution, there is a non-template candidate
that would be always be picked - because each of the argument
is a perfect match (ie the source and target types are the same),
we do not perform deduction for any template candidate
that might exists.
The goal is to be able to merge
https://github.com/llvm/llvm-project/pull/122423 without being too
disruptive.
This change means that the selection of the best viable candidate and
template argument deduction become interleaved.
To avoid rewriting half of Clang we store in OverloadCandidateSet
enough information to be able to deduce template candidates from
OverloadCandidateSet::BestViableFunction. Which means
the lifetime of any object used by template argument must outlive
a call to Add*Template*Candidate.
This two phase resolution is not performed for some initialization
as there are cases where template candidate are better match
in these cases per the standard. It's also bypassed for code completion.
The change has a nice impact on compile times
https://llvm-compile-time-tracker.com/compare.php?from=719b029c16eeb1035da522fd641dfcc4cee6be74&to=bf7041045c9408490c395230047c5461de72fc39&stat=instructions%3Au
Fixes https://github.com/llvm/llvm-project/issues/62096
Fixes https://github.com/llvm/llvm-project/issues/74581
Reapplies https://github.com/llvm/llvm-project/pull/133426
Commit: 49dfd72de0131e4c3f1270ef60ea54af43a3c96b
https://github.com/llvm/llvm-project/commit/49dfd72de0131e4c3f1270ef60ea54af43a3c96b
Author: Fangrui Song <i at maskray.me>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/test/MC/LoongArch/Relocations/relax-tls-le.s
Log Message:
-----------
[test] Remove CHECK lines for MCAsmStreamer's fixup output
Similar to 5e430afb84c3cbf285d8fe15c0ae23e0920e946b
Commit: 7088910b9f74d49a7e0a107a2261be90c1c8bd1b
https://github.com/llvm/llvm-project/commit/7088910b9f74d49a7e0a107a2261be90c1c8bd1b
Author: Fangrui Song <i at maskray.me>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/test/MC/AArch64/tls-relocs.s
Log Message:
-----------
MCAsmStreamer: Print relocation type number if applicable
The fixup output is a debug aid and should not be used to test
target-specific relocation generation implementation. The llvm-mc
-filetype=obj output is what truly matters.
Commit: d5f94c3915ace438359524b40cf84f3f54a0afae
https://github.com/llvm/llvm-project/commit/d5f94c3915ace438359524b40cf84f3f54a0afae
Author: Fangrui Song <i at maskray.me>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/test/MC/RISCV/rv32xtheadmempair-invalid.s
M llvm/test/MC/RISCV/rv64xtheadmempair-invalid.s
Log Message:
-----------
Revert "[RISCV] Strengthen register usage validation for XTheadMemPair loads (#136241)"
This reverts commit a354564a64c6ab3cafa9e5e2b31f7f14d4e27d45.
Broke tests
Commit: 65d16a8101f98199b5d2505c1e9fdf2df519814b
https://github.com/llvm/llvm-project/commit/65d16a8101f98199b5d2505c1e9fdf2df519814b
Author: Fangrui Song <i at maskray.me>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/lib/MC/MCAssembler.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
Log Message:
-----------
[RISCV] Simplify fixup kinds that force relocations
For RELA targets, fixup kinds that force relocations (GOT, TLS, ALIGN,
RELAX, etc) can bypass `applyFixup` and be encoded as
`FirstRelocationKind+i`, as seen in LoongArch. This patch removes
redundant fixup kinds and adopts the `FirstRelocationKind+i` encoding.
The `llvm-mc -show-encoding` output no longer displays descriptive fixup
names, as this information is removed from
`RISCVAsmBackend::getFixupKindInfo`. While a backend hook could be added
to call `llvm::object::getELFRelocationTypeName`, it's unnecessary since
the relocation in `-filetype=obj` output is what truly matters.
Pull Request: https://github.com/llvm/llvm-project/pull/136088
Commit: 59288761c9a8a3d5ecc70543ba09246497117f9e
https://github.com/llvm/llvm-project/commit/59288761c9a8a3d5ecc70543ba09246497117f9e
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/include/llvm/Support/UnicodeCharRanges.h
M llvm/lib/Target/Mips/Mips16HardFloat.cpp
M llvm/lib/Target/Mips/Mips16ISelLowering.cpp
M llvm/lib/Target/Mips/MipsCCState.cpp
M llvm/tools/llvm-cov/CodeCoverage.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
Log Message:
-----------
[llvm] Use llvm::binary_search (NFC) (#136228)
Commit: b07ee6acffd4c6c19093f8a5e9f8c6c594f3c90a
https://github.com/llvm/llvm-project/commit/b07ee6acffd4c6c19093f8a5e9f8c6c594f3c90a
Author: Peter Collingbourne <peter at pcc.me.uk>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
Log Message:
-----------
LowerTypeTests: Simplify pointer types.
Commit: 155fc76f20fec106d59701b3d320b74d46894b37
https://github.com/llvm/llvm-project/commit/155fc76f20fec106d59701b3d320b74d46894b37
Author: Iris <0.0 at owo.li>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/test/MC/RISCV/rv32xtheadmempair-invalid.s
M llvm/test/MC/RISCV/rv64xtheadmempair-invalid.s
Log Message:
-----------
Recommit "[RISCV] Strengthen register usage validation for XTheadMemPair loads (#136241)"
With test fix.
Closes #136087
https://github.com/XUANTIE-RV/thead-extension-spec/blob/master/xtheadmempair/lwd.adoc
Commit: 2b002d68044e6b482a898c1deff578f76fa9b8a1
https://github.com/llvm/llvm-project/commit/2b002d68044e6b482a898c1deff578f76fa9b8a1
Author: Nico Weber <thakis at chromium.org>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/utils/gn/secondary/compiler-rt/lib/scudo/standalone/BUILD.gn
Log Message:
-----------
[gn] port 1756fcb8b019
Commit: f28408f3af0d4533dd1d8048c5fdcdb14b934d05
https://github.com/llvm/llvm-project/commit/f28408f3af0d4533dd1d8048c5fdcdb14b934d05
Author: Fangrui Song <i at maskray.me>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/test/MC/AVR/inst-adiw.s
M llvm/test/MC/AVR/inst-andi.s
M llvm/test/MC/AVR/inst-brbc.s
M llvm/test/MC/AVR/inst-brbs.s
M llvm/test/MC/AVR/inst-brcc.s
M llvm/test/MC/AVR/inst-brcs.s
M llvm/test/MC/AVR/inst-breq.s
M llvm/test/MC/AVR/inst-brge.s
M llvm/test/MC/AVR/inst-brhc.s
M llvm/test/MC/AVR/inst-brhs.s
M llvm/test/MC/AVR/inst-brid.s
M llvm/test/MC/AVR/inst-brie.s
M llvm/test/MC/AVR/inst-brlo.s
M llvm/test/MC/AVR/inst-brlt.s
M llvm/test/MC/AVR/inst-brmi.s
M llvm/test/MC/AVR/inst-brne.s
M llvm/test/MC/AVR/inst-brpl.s
M llvm/test/MC/AVR/inst-brsh.s
M llvm/test/MC/AVR/inst-brtc.s
M llvm/test/MC/AVR/inst-brts.s
M llvm/test/MC/AVR/inst-brvc.s
M llvm/test/MC/AVR/inst-brvs.s
M llvm/test/MC/AVR/inst-call.s
M llvm/test/MC/AVR/inst-cbi.s
M llvm/test/MC/AVR/inst-cpi.s
M llvm/test/MC/AVR/inst-in.s
M llvm/test/MC/AVR/inst-jmp.s
M llvm/test/MC/AVR/inst-ldd.s
M llvm/test/MC/AVR/inst-ldi.s
M llvm/test/MC/AVR/inst-lds-tiny.s
M llvm/test/MC/AVR/inst-lds.s
M llvm/test/MC/AVR/inst-ori.s
M llvm/test/MC/AVR/inst-out.s
M llvm/test/MC/AVR/inst-rcall.s
M llvm/test/MC/AVR/inst-rjmp.s
M llvm/test/MC/AVR/inst-sbci.s
M llvm/test/MC/AVR/inst-sbi.s
M llvm/test/MC/AVR/inst-sbic.s
M llvm/test/MC/AVR/inst-sbis.s
M llvm/test/MC/AVR/inst-sbiw.s
M llvm/test/MC/AVR/inst-sbr.s
M llvm/test/MC/AVR/inst-std.s
M llvm/test/MC/AVR/inst-sts-tiny.s
M llvm/test/MC/AVR/inst-sts.s
M llvm/test/MC/AVR/inst-subi.s
M llvm/test/MC/AVR/modifiers.s
M llvm/test/MC/CSKY/basic-16bit.s
M llvm/test/MC/CSKY/basic.s
M llvm/test/MC/Sparc/sparc-assembly-exprs.s
M llvm/test/MC/Sparc/sparc-ctrl-instructions.s
M llvm/test/MC/Sparc/sparc-little-endian.s
M llvm/test/MC/Sparc/sparc-relocations.s
M llvm/test/MC/Sparc/sparc-synthetic-instructions.s
M llvm/test/MC/Sparc/sparc-tls-relocations.s
M llvm/test/MC/Sparc/sparc64-ctrl-instructions.s
M llvm/test/MC/Sparc/sparcv9-synthetic-instructions.s
Log Message:
-----------
[test] Remove CHECK lines for MCAsmStreamer's fixup output
The fixup output is a debug aid and should not be used to test
target-specific relocation generation implementation. The llvm-mc
-filetype=obj output is what truly matters.
Commit: a42ac55a79db071e7e6da385213c5486d4b14986
https://github.com/llvm/llvm-project/commit/a42ac55a79db071e7e6da385213c5486d4b14986
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
Log Message:
-----------
[IPO] Avoid repeated hash lookups (NFC) (#135750)
Commit: d27175d26e20ebc112b003c877692c06046d195b
https://github.com/llvm/llvm-project/commit/d27175d26e20ebc112b003c877692c06046d195b
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-17 (Thu, 17 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
Log Message:
-----------
[Scalar] Avoid repeated hash lookups (NFC) (#135751)
Commit: cc7fc9978fc8c9b8e1da2e283026feaf85807ea5
https://github.com/llvm/llvm-project/commit/cc7fc9978fc8c9b8e1da2e283026feaf85807ea5
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M clang/lib/Frontend/DiagnosticRenderer.cpp
M clang/lib/Sema/SemaExpr.cpp
Log Message:
-----------
[clang] Add source range to 'use of undeclared identifier' diagnostics (#117671)
Commit: e0a6905287050d57ea0413cba7f011803b1f65ef
https://github.com/llvm/llvm-project/commit/e0a6905287050d57ea0413cba7f011803b1f65ef
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M libcxx/include/__type_traits/is_signed.h
M libcxx/include/__type_traits/is_unsigned.h
Log Message:
-----------
[libc++] Simplify the generic implementation of is_{un}signed (#136095)
Commit: f4c76bba5909e9c3e542ac723b9a1c0f1c229e79
https://github.com/llvm/llvm-project/commit/f4c76bba5909e9c3e542ac723b9a1c0f1c229e79
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M clang/lib/CodeGen/Targets/AArch64.cpp
M clang/lib/Driver/XRayArgs.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaSYCL.cpp
M clang/tools/clang-installapi/ClangInstallAPI.cpp
M clang/tools/clang-installapi/Options.cpp
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
Log Message:
-----------
[clang] Use llvm::append_range (NFC) (#136256)
This patch replaces:
llvm::copy(Src, std::back_inserter(Dst));
with:
llvm::append_range(Dst, Src);
for breavity.
One side benefit is that llvm::append_range eventually calls
llvm::SmallVector::reserve if Dst is of llvm::SmallVector.
Commit: a1583522948f966d2393e84befdc2f7fea3bf7b4
https://github.com/llvm/llvm-project/commit/a1583522948f966d2393e84befdc2f7fea3bf7b4
Author: Yanzuo Liu <zwuis at outlook.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M .github/new-prs-labeler.yml
Log Message:
-----------
[Clang][GitHub][NFC] Auto-add clang:bytecode label for PR (#136148)
Commit: 802e7309c0ab7e9966f8a98eede0231d146c6a97
https://github.com/llvm/llvm-project/commit/802e7309c0ab7e9966f8a98eede0231d146c6a97
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M lldb/test/API/commands/expression/diagnostics/TestExprDiagnostics.py
Log Message:
-----------
[lldb] Fix TestExprDiagnostics test (#136269)
Add missing source ranges to the diagnostic output.
Commit: d1496313d7e2543f1506f71fbfd28a8e8d8a3d6e
https://github.com/llvm/llvm-project/commit/d1496313d7e2543f1506f71fbfd28a8e8d8a3d6e
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/include/llvm/CodeGen/CFIInstBuilder.h
M llvm/lib/Target/MSP430/MSP430FrameLowering.cpp
Log Message:
-----------
[CodeGen] Add another method to CFIInstBuilder (#136270)
Mainly for use by downstream targets, but it can find applications in
upstream code as well. Use it in MSP430 so that it doesn't look dead.
Commit: a99c978d1b35e30d9a0fe9db68b91e9f2815c8e9
https://github.com/llvm/llvm-project/commit/a99c978d1b35e30d9a0fe9db68b91e9f2815c8e9
Author: Corentin Jabot <corentinjabot at gmail.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M clang/include/clang/Sema/Overload.h
M clang/lib/Sema/SemaOverload.cpp
Log Message:
-----------
[Clang] Avoid dereferencing an invalid iterator
Fix msan builds after 8c5a307bd8
https://lab.llvm.org/buildbot/#/builders/94/builds/6321
Commit: 5db95fd6ca8cae62c6ab6acf17b00c3417d2018d
https://github.com/llvm/llvm-project/commit/5db95fd6ca8cae62c6ab6acf17b00c3417d2018d
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/lib/ProfileData/MemProfReader.cpp
Log Message:
-----------
[memprof] Avoid repeated hash lookups (NFC) (#136268)
Note that we don't have to worry about CallstackProfileData[Id]
default-constructing the value side of a new map entry. If that
happens, AccessHistogramSize > 0 wouldn't be true, and the new map
entry gets deleted right away.
Commit: 64ffecfc433d43a15e3d1d51886ff0e0a876a547
https://github.com/llvm/llvm-project/commit/64ffecfc433d43a15e3d1d51886ff0e0a876a547
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
Log Message:
-----------
[DAG] isKnownNeverNaN - add DemandedElts element mask to isKnownNeverNaN calls (#135952)
Matches what we've done for computeKnownBits etc. to improve vector handling
Commit: c7daab259c3281cf8f649583993bad2536febc02
https://github.com/llvm/llvm-project/commit/c7daab259c3281cf8f649583993bad2536febc02
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M clang/lib/Parse/ParseExpr.cpp
M clang/test/Parser/recovery.cpp
Log Message:
-----------
[Clang] Fix the trailing comma regression (#136273)
925e195 introduced a regression since which we started to accept invalid
trailing commas in many expression lists where they're not allowed by
the grammar. The issue came from the fact that an additional invalid
state - previously handled by ParseExpressionList - was overlooked in
that patch.
Fixes https://github.com/llvm/llvm-project/issues/136254
No release entry because I want to backport it.
Commit: 1db03cab70fd29fe13cb60cc102285d0d0f33957
https://github.com/llvm/llvm-project/commit/1db03cab70fd29fe13cb60cc102285d0d0f33957
Author: Christian Sigg <csigg at google.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] Port 697aa9995c24a977425e672d76a4a434384b16e3
Commit: 31ddaef8d18d643ff4c343d03ddfe2edae7d22a2
https://github.com/llvm/llvm-project/commit/31ddaef8d18d643ff4c343d03ddfe2edae7d22a2
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/include/llvm/CodeGen/UnreachableBlockElim.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/LiveVariables.cpp
M llvm/lib/CodeGen/UnreachableBlockElim.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/test/CodeGen/Hexagon/unreachable-mbb-phi-subreg.mir
M llvm/test/DebugInfo/MIR/X86/unreachable-block-call-site.mir
Log Message:
-----------
[CodeGen][NPM] Port UnreachableMachineBlockElim to NPM (#136127)
Commit: 9bdd9dc895ade41ec24f1a9918f70b23271ac89b
https://github.com/llvm/llvm-project/commit/9bdd9dc895ade41ec24f1a9918f70b23271ac89b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn.cl
M clang/test/CodeGenOpenCL/builtins-r600.cl
M clang/test/Headers/gpuintrin.c
M clang/test/Headers/gpuintrin_lang.c
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/test/CodeGen/AMDGPU/amdgpu-inline.ll
M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.iterative.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id-unsupported-calling-convention.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/v_add_u64_pseudo_sdwa.ll
M llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-for-private.ll
Log Message:
-----------
AMDGPU: Mark workitem ID intrinsics with range attribute (#136196)
This avoids the need to have special handling at every use site.
Unfortunately this means we unnecessarily emit AssertZext in the DAG
(where we already directly understand the range of the intrinsic), andt
we regress in undefined cases as we don't fold out asserts on undef.
Commit: 9b8bc53a0bdc270f6d675ba7a2fe9ca9a855610d
https://github.com/llvm/llvm-project/commit/9b8bc53a0bdc270f6d675ba7a2fe9ca9a855610d
Author: Chengjun <chengjunp at Nvidia.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/include/llvm/Analysis/AliasAnalysis.h
M llvm/lib/Analysis/AliasAnalysis.cpp
M llvm/lib/Transforms/Utils/FlattenCFG.cpp
M llvm/test/Transforms/Util/flatten-cfg.ll
M llvm/unittests/Analysis/AliasAnalysisTest.cpp
Log Message:
-----------
[FlattenCFG] Fix an Imprecise Usage of AA (#128117)
In current `FlattenCFG`, using `isNoAlias` for two instructions is
imprecise. For example, when passing a store instruction and a load
instruction directly into `AA->isNoAlias`, it will always return
`NoAlias`. This happens because when checking the types of the two
Values, the store instruction (which has a `void` type) causes the
analysis to return `NoAlias`.
For instructions, we should use `getModRefInfo` instead of `isNoAlias`,
as aliasing is a concept of memory locations.
In this patch, `AAResults::getModRefInfo` is supported to take in two
instructions. It will check whether two instructions may access the same
memory location or not. And in `FlattenCFG`, we use this new helper
function to do the check instead of `isNoAlias`.
Unit tests and lit tests are also included to this patch.
Commit: 1d190065d92a7cc9fbe322edbfa233c2318c8839
https://github.com/llvm/llvm-project/commit/1d190065d92a7cc9fbe322edbfa233c2318c8839
Author: Zichen Lu <mikaovo2000 at gmail.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M mlir/lib/Target/LLVM/NVVM/Target.cpp
Log Message:
-----------
[mlir][target] RAII wrap moduleToObject timer to ensure call `clear` function (#136142)
As title, we need to call `Timer::clear` to avoid extra log like this:
```
===-------------------------------------------------------------------------===
...
===-------------------------------------------------------------------------===
Total Execution Time: 0.0000 seconds (0.0000 wall clock)
---Wall Time--- --- Name ---
----- ....
----- Total
```
Commit: c5d59723cbf9743f7a0534a6ca87383abb6785a7
https://github.com/llvm/llvm-project/commit/c5d59723cbf9743f7a0534a6ca87383abb6785a7
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/test/CodeGen/p0963r3.cpp
Log Message:
-----------
[clang][bytecode] Reject constexpr-unknown values in CheckStore (#136279)
Commit: c609cd2df981d1fcbdfefa1e2601b965b9670630
https://github.com/llvm/llvm-project/commit/c609cd2df981d1fcbdfefa1e2601b965b9670630
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/test/Misc/warning-flags.c
A clang/test/SemaCXX/uninitialized-no-ctor.cpp
Log Message:
-----------
Give this diagnostic a diagnostic group (#136182)
I put this under -Wunitialized because that's the same group it's under
in GCC.
Fixes #41104
Commit: a8fe21f3f502a49cb05b69b0d6fa74472b93888a
https://github.com/llvm/llvm-project/commit/a8fe21f3f502a49cb05b69b0d6fa74472b93888a
Author: Andrew Savonichev <andrew.savonichev at gmail.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M clang/lib/AST/Decl.cpp
M clang/test/CodeGenCXX/visibility.cpp
Log Message:
-----------
[clang] Handle instantiated members to determine visibility (#136128)
As reported in issue #103477, visibility of instantiated member
functions used to be ignored when calculating visibility of a
specialization.
This patch modifies `getLVForClassMember` to look up for a source
template for an instantiated member, and changes `mergeTemplateLV` to
apply it.
A similar issue was reported in #31462, but it seems that `extern`
declaration with visibility prevents the function from being emitted as
hidden. This behavior seems correct, even though GCC emits it as with
default visibility instead.
Both tests from #103477 and #31462 are added as LIT tests `test72` and
`test73` respectively.
Commit: 6c4caae4495118d680fd08cadca73b8c583719c7
https://github.com/llvm/llvm-project/commit/6c4caae4495118d680fd08cadca73b8c583719c7
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
M llvm/utils/TableGen/DecoderEmitter.cpp
Log Message:
-----------
[LLVM][TableGen] Move DecoderEmitter output to anonymous namespace (#136214)
- Move the code generated by DecoderEmitter to anonymous namespace.
- Move AMDGPU's usage of this code from header file to .cpp file.
Note, we get build errors like "call to function 'decodeInstruction'
that is neither visible in the template definition nor found by
argument-dependent lookup" if we do not change AMDGPU.
Commit: c890b7376fc916c1818dc3c211a080601973aa0b
https://github.com/llvm/llvm-project/commit/c890b7376fc916c1818dc3c211a080601973aa0b
Author: Raul Tambre <raul at tambre.ee>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M lldb/unittests/Core/TelemetryTest.cpp
Log Message:
-----------
[lldb][Telemetry] Fix unit test compile failure with LLVM_ENABLE_TELEMETRY=0 (#136115)
It needs to be `TEST_F` to access `received_entries`.
Disabling also works based on the test not the fixture name.
Build failure:
```
lldb/unittests/Core/TelemetryTest.cpp:110:17: error: use of undeclared identifier 'received_entries'
110 | ASSERT_EQ(1U, received_entries.size());
| ^
lldb/unittests/Core/TelemetryTest.cpp:112:61: error: use of undeclared identifier 'received_entries'
112 | llvm::dyn_cast<lldb_private::FakeTelemetryInfo>(received_entries[0])
| ^
```
Fixes: 159b872b37363511a359c800bcc9230bb09f2457
Commit: 6462fad3d04d1cc6ceda303a6525742c8b911e79
https://github.com/llvm/llvm-project/commit/6462fad3d04d1cc6ceda303a6525742c8b911e79
Author: Vladislav Dzhidzhoev <vdzhidzhoev at accesssoftek.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/lib/IR/DebugInfoMetadata.cpp
A llvm/test/DebugInfo/AArch64/merge-nested-block-loc.ll
A llvm/test/DebugInfo/AArch64/merge-nested-block-loc2.ll
M llvm/unittests/IR/MetadataTest.cpp
Log Message:
-----------
[DebugInfo] getMergedLocation: match scopes based on their location (#132286)
getMergedLocation uses a common parent scope of the two input locations
for an output location.
It doesn't consider the case when the common parent scope is from a file
other than L1's and L2's files. In that case, it produces a merged location
with an erroneous scope (https://github.com/llvm/llvm-project/issues/122846).
In some cases, such as https://github.com/llvm/llvm-project/pull/125780#issuecomment-2651657856,
L1, L2 having a common parent scope from another file indicate that
the code at L1 and L2 is included from the same source location.
With this commit, getMergedLocation detects that L1, L2, or their common parent
scope files are different. If so, it assumes that L1 and L2 were included
from some source location, and tries to attach the output location to a scope
with the nearest common source location with regard to L1 and L2.
If the nearest common location is also from another file, getMergedLocation returns it
as a merged location, assuming that L1 and L2 belong to files that were both included
in the nearest common location.
Fixes https://github.com/llvm/llvm-project/issues/122846.
Commit: e1b14d4e1c8ecca73e13a0629960d530e336a0d8
https://github.com/llvm/llvm-project/commit/e1b14d4e1c8ecca73e13a0629960d530e336a0d8
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M clang/test/Headers/gpuintrin_lang.c
Log Message:
-----------
[Clang][GPU] Fix unit test for NVPTX tid.x intrinsic (#136297)
- llvm.nvvm.read.ptx.sreg.tid.x does not have the result range attribute
yet.
Commit: 3ed83630b263f667bacd1ef1a65f26d8665c282e
https://github.com/llvm/llvm-project/commit/3ed83630b263f667bacd1ef1a65f26d8665c282e
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/utils/TableGen/DecoderEmitter.cpp
Log Message:
-----------
[NFC][LLVM][TableGen] Use `decodeULEB128` for `OPC_SoftFail` emission (#136220)
- Use `decodeULEB128` to decode +ve/-ve mask in OPC_SoftFail case.
- Use current `I`/`E` iterators as inputs to `decodeULEB128`.
Commit: db0f754c5af8e6c96770533520bf8b17fc0dc977
https://github.com/llvm/llvm-project/commit/db0f754c5af8e6c96770533520bf8b17fc0dc977
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/test/Driver/openmp-offload-gpu.c
M offload/DeviceRTL/CMakeLists.txt
R offload/DeviceRTL/src/exports
M offload/test/lit.cfg
Log Message:
-----------
[OpenMP] Remove 'libomptarget.devicertl.a' fatbinary and use static library (#126143)
Summary:
Currently, we build a single `libomptarget.devicertl.a` which is a
fatbinary. It is a host object file that contains the embedded archive
files for both the NVIDIA and AMDGPU targets. This was done primarily as
a convenience due to naming conflicts. Now that the clang driver for the
GPU targets can appropriate link via the per-target runtime-dir, we can
just make two separate static libraries and remove the indirection.
This patch creates two new static libraries that get installed into
```
/lib/amdgcn-amd-amdhsa/libomp.a
/lib/nvptx64-nvidia-cuda/libomp.a
```
for AMDGPU and NVPTX respectively. The link job created by the linker
wrapper now simply needs to do `-lomp` and it will search those
directories and link those static libraries. This requires far less
special handling.
This patch is a precursor to changing the build system entirely to be a
runtimes based one. Soon this target will be a standard `add_library`
and done through the GPU runtime targets.
NOTE that this actually does remove an additional optimization step.
Previously we merged all of the files into a single bitcode object and
forcibly internalized some definitions. This, instead, just treats them
like a normal static library. This may possibly affect performance for
some files, but I think it's better overall to use static library
semantics because it allows us to have an 'include-what-you-use'
relationship with the library.
Performance testing will be required. If we really need the merged blob
then we can simply pack that into a new static library.
Commit: fc1e311966c59368e63b834a42523ce104711a94
https://github.com/llvm/llvm-project/commit/fc1e311966c59368e63b834a42523ce104711a94
Author: Matthias Springer <me at m-sp.org>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M mlir/test/Conversion/MemRefToLLVM/memref-to-llvm.mlir
Log Message:
-----------
[mlir][memref] Fix rollback in test case during `convert-to-llvm` (#135958)
This commit is in preparation of the One-Shot Dialect Conversion
refactoring, which removes the rollback from the dialect conversion
framework.
`GenericAtomicRMWOpLowering` (`generic_atomic_rmw`) triggered a rollback
in two test cases. The lowering pattern adds additional basic blocks to
the enclosing operation, which used to be a `func.func` (now
`llvm.func`). Adding a basic block triggers legalization of the op that
owns the basic block. This fails when running
`--convert-to-llvm="filter-dialects=memref"` because no lowering
patterns for the `func` dialect were populated and only `llvm` ops are
considered "legal" by the `convert-to-llvm` pass, causing a rollback of
the entire `GenericAtomicRMWOpLowering` pattern.
Also add extra `CHECK-INTERFACE` to make sure that all test cases are
correctly lowered with `--convert-to-llvm="filter-dialects=memref"`.
Commit: 622765f976f0a76313aa38d0f549eea9affeebfd
https://github.com/llvm/llvm-project/commit/622765f976f0a76313aa38d0f549eea9affeebfd
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M clang/test/Headers/gpuintrin_lang.c
Log Message:
-----------
[Clang][GPU] Make NVPTX check more permissive in unit test (#136301)
- Seems based on whether NVPTX backend is enabled or not, this call can
have the range() attribute or not. So make this check more permissive.
Commit: 860e88411d94b9e83cf9524d05b30a3d2d221b2c
https://github.com/llvm/llvm-project/commit/860e88411d94b9e83cf9524d05b30a3d2d221b2c
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M libcxx/docs/Contributing.rst
M libcxx/include/CMakeLists.txt
R libcxx/include/module.modulemap
A libcxx/include/module.modulemap.in
A libcxx/test/libcxx/Wnon_modular_include_in_module.compile.pass.cpp
M libcxx/test/libcxx/headers_in_modulemap.sh.py
M libcxx/test/libcxx/lint/lint_headers.sh.py
M libcxx/utils/libcxx/header_information.py
Log Message:
-----------
[libc++] Make __config_site modular (#134699)
This patch makes the __config_site header modular, which solves various
problems with non-modular headers. This requires going back to
generating the modulemap file, since we only know how to make
__config_site modular when we're not using the per-target runtime dir.
The patch also adds a test that we support
-Wnon-modular-include-in-module, which warns about non-modular includes
from modules.
---------
Co-authored-by: Konstantin Varlamov <varconst at apple.com>
Commit: 63b8f1c9482ed0a964980df4aed89bef922b8078
https://github.com/llvm/llvm-project/commit/63b8f1c9482ed0a964980df4aed89bef922b8078
Author: Oleksandr "Alex" Zinenko <git at ozinenko.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M flang/lib/Optimizer/CodeGen/LowerRepackArrays.cpp
M flang/lib/Optimizer/HLFIR/Transforms/InlineElementals.cpp
M flang/lib/Optimizer/HLFIR/Transforms/InlineHLFIRAssign.cpp
M flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
M flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/AssumedRankOpConversion.cpp
M flang/lib/Optimizer/Transforms/ConstantArgumentGlobalisation.cpp
M flang/lib/Optimizer/Transforms/SimplifyFIROperations.cpp
M flang/lib/Optimizer/Transforms/StackArrays.cpp
M mlir/include/mlir/Transforms/GreedyPatternRewriteDriver.h
M mlir/include/mlir/Transforms/Passes.td
M mlir/lib/Dialect/Affine/TransformOps/AffineTransformOps.cpp
M mlir/lib/Dialect/Affine/Transforms/AffineDataCopyGeneration.cpp
M mlir/lib/Dialect/Affine/Transforms/SimplifyAffineStructures.cpp
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/lib/Dialect/Affine/Utils/Utils.cpp
M mlir/lib/Dialect/Arith/Transforms/IntRangeOptimizations.cpp
M mlir/lib/Dialect/Bufferization/Transforms/BufferDeallocationSimplification.cpp
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp
M mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp
M mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
M mlir/lib/Dialect/Transform/IR/TransformOps.cpp
M mlir/lib/Reducer/ReductionTreePass.cpp
M mlir/lib/Transforms/Canonicalizer.cpp
M mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
M mlir/test/lib/Dialect/Affine/TestAffineDataCopy.cpp
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
Log Message:
-----------
[mlir] add a fluent API to GreedyRewriterConfig (#132253)
This is similar to other configuration objects used across MLIR.
Commit: 730773602f8b039a575e3e48cd838174dd996520
https://github.com/llvm/llvm-project/commit/730773602f8b039a575e3e48cd838174dd996520
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/test/tools/llvm-reduce/thinlto-preserve-uselistorder.ll
Log Message:
-----------
llvm-reduce: Avoid using constantdata uselistorder in thinlto test (#136288)
This also demonstrates a bug that's a consequence of the two different
paths for the single and multithreaded cases. The parallel path goes
through bitcode serialization and does preserve the uselistorder. It
therefore survives and we can observe a reduced uselistorder with deleted
instructions. In the CloneModule case, nothing is reduced.
Commit: 35e6ca47c1b565b59a9e9f90b5239804e64819f7
https://github.com/llvm/llvm-project/commit/35e6ca47c1b565b59a9e9f90b5239804e64819f7
Author: amordo <iammorjj at gmail.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/docs/InstCombineContributorGuide.md
Log Message:
-----------
[docs] Add TOC for InstCombine contributor guide (#136293)
Commit: 20a104a7d6423784dab04371a5ca728cc27a15a9
https://github.com/llvm/llvm-project/commit/20a104a7d6423784dab04371a5ca728cc27a15a9
Author: Oleksandr "Alex" Zinenko <git at ozinenko.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td
M mlir/include/mlir/Interfaces/FunctionInterfaces.td
M mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp
M mlir/lib/Dialect/Bufferization/Transforms/BufferResultsToOutParams.cpp
M mlir/lib/Dialect/Bufferization/Transforms/DropEquivalentBufferResults.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
M mlir/lib/Query/Query.cpp
M mlir/lib/Transforms/RemoveDeadValues.cpp
M mlir/test/IR/test-func-erase-result.mlir
M mlir/test/lib/IR/TestFunc.cpp
Log Message:
-----------
[mlir] allow function type cloning to fail (#136300)
`FunctionOpInterface` assumed the fact that the function type (attribute
of the operation) can be cloned with arbirary lists of function
arguments and results to support argument and result list mutation. This
is not always correct, in particular, LLVM dialect functions require
exactly one result making it impossible to erase the result.
Allow function type cloning to fail and propagate this failure through
various APIs that use it. The common assumption is that existing IR has
not been modified.
Fixes #131142.
Commit: b1b065f2bf5d626fee277d67b0014577f7e4e499
https://github.com/llvm/llvm-project/commit/b1b065f2bf5d626fee277d67b0014577f7e4e499
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/Transforms/InstCombine/icmp-dom.ll
Log Message:
-----------
[ValueTracking] Refactor `isKnownNonEqualFromContext` (#127388)
This patch avoids adding RHS for comparisons with two variable operands
(https://github.com/llvm/llvm-project/pull/118493#discussion_r1949397482).
Instead, we iterate over related dominating conditions of both V1 and V2
in `isKnownNonEqualFromContext`, as suggested by goldsteinn
(https://github.com/llvm/llvm-project/pull/117442#discussion_r1944058002).
Compile-time improvement:
https://llvm-compile-time-tracker.com/compare.php?from=c6d95c441a29a45782ff72d6cb82839b86fd0e4a&to=88464baedd7b1731281eaa0ce4438122b4d218a7&stat=instructions:u
Commit: dda4b968e77e1bb2c319bf2d523de3b5c4ccbb23
https://github.com/llvm/llvm-project/commit/dda4b968e77e1bb2c319bf2d523de3b5c4ccbb23
Author: Ivan Butygin <ivan.butygin at gmail.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M mlir/include/mlir/Conversion/LLVMCommon/Pattern.h
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Conversion/LLVMCommon/Pattern.cpp
A mlir/test/Conversion/AMDGPUToROCDL/swizzle.mlir
M mlir/test/Dialect/AMDGPU/invalid.mlir
Log Message:
-----------
[mlir] AMDGPUToROCDL: lower `amdgpu.swizzle_bitmode` (#136223)
Repack `amdgpu.swizzle_bitmode` arguments and lower it to
`rocdl.ds_swizzle`.
Repacking logic is follows:
* `sizeof(arg) < sizeof(i32)`: bitcast to integer and zext to i32 and
then trunc and bitcast back.
* `sizeof(arg) == sizeof(i32)`: just bitcast to i32 and back if not i32
* `sizeof(arg) > sizeof(i32)`: bitcast to `vector<Nxi32>`, extract
individual elements and do a series of `rocdl.ds_swizzle` and then
compose vector and bitcast back.
Added repacking logic to LLVM utils so it can be used elsewhere. I'm
planning to use it for `gpu.shuffle` later.
Commit: f2ecd86e34ed5323f2a8ec2259f11e9f5e9bb078
https://github.com/llvm/llvm-project/commit/f2ecd86e34ed5323f2a8ec2259f11e9f5e9bb078
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/include/llvm/Analysis/MemoryLocation.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/TargetInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
M llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
M llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
Log Message:
-----------
[Analysis] Remove implicit LocationSize conversion from uint64_t (#133342)
This change removes the uint64_t constructor on LocationSize
preventing implicit conversion, and fixes up the using APIs to adapt to
the change. Note that I'm adding a couple of explicit conversion points
on routines where passing in a fixed offset as an integer seems likely
to have well understood semantics.
We had an unfortunate case which arose if you tried to pass a TypeSize
value to a parameter of LocationSize type. We'd find the implicit
conversion path through TypeSize -> uint64_t -> LocationSize which works
just fine for fixed values, but looses information and fails assertions
if the TypeSize was scalable. This change breaks the first link in that
implicit conversion chain since that seemed to be the easier one.
Commit: d0dd6974b8850dbec0237596fedd58db4552f2ec
https://github.com/llvm/llvm-project/commit/d0dd6974b8850dbec0237596fedd58db4552f2ec
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M mlir/lib/Dialect/SPIRV/IR/ControlFlowOps.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVAttributes.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
Log Message:
-----------
[mlir][spirv] Switch to `llvm::interleaved`. NFC. (#136240)
Clean up printing code by switching to `llvm::interleaved` from
https://github.com/llvm/llvm-project/pull/135517.
Commit: 4be84a142e97d25faf7acdd2d279124d0af32b7e
https://github.com/llvm/llvm-project/commit/4be84a142e97d25faf7acdd2d279124d0af32b7e
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/lib/Dialect/GPU/TransformOps/GPUTransformOps.cpp
Log Message:
-----------
[mlir][gpu] Clean up prints in GPU dialect. NFC. (#136250)
Clean up printing code by switching to `llvm::interleaved` from
https://github.com/llvm/llvm-project/pull/135517. Also make some minor
readability & performance fixes.
Commit: c016a65c180c8703d5bdb2a277bb1629df5517b6
https://github.com/llvm/llvm-project/commit/c016a65c180c8703d5bdb2a277bb1629df5517b6
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorUnroll.cpp
M mlir/lib/Dialect/Vector/Utils/VectorUtils.cpp
Log Message:
-----------
[mlir][vector] Switch to `llvm::interleaved` in debug prints. NFC. (#136248)
Clean up printing code by switching to `llvm::interleaved` from
https://github.com/llvm/llvm-project/pull/135517.
Commit: 257b72758424f56103d38e3d016cfb6baa4da613
https://github.com/llvm/llvm-project/commit/257b72758424f56103d38e3d016cfb6baa4da613
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M clang/lib/Sema/SemaDeclAttr.cpp
A clang/test/SemaSYCL/Inputs/vectorcall.hpp
A clang/test/SemaSYCL/sycl-cconv-win.cpp
Log Message:
-----------
[clang][Sema][SYCL] Fix MSVC STL usage on AMDGPU (#135979)
The MSVC STL includes specializations of `_Is_memfunptr` for every
function pointer type, including every calling convention.
The problem is the AMDGPU target doesn't support the x86 `vectorcall`
calling convention so clang sets it to the default CC. This ends up
clashing with the already-existing overload for the default CC, so we
get a duplicate definition error when including `type_traits` (which we
heavily use in the SYCL STL) and compiling for AMDGPU on Windows.
This doesn't happen for pure AMDGPU non-SYCL because it doesn't include
the C++ STL, and it doesn't happen for CUDA/HIP because a similar
workaround was done
[here](https://github.com/llvm/llvm-project/commit/fa49c3a888e816969b5ed68cd5c47efc3eb9419f).
I am not an expert in Sema, so I did a kinda of hardcoded fix, please
let me know if there is a better way to fix this.
As far as I can tell we can't do exactly the same fix that was done for
CUDA because we can't differentiate between device and host code so
easily.
---------
Signed-off-by: Sarnie, Nick <nick.sarnie at intel.com>
Commit: be9f72cf3716bc1de5912a457284a1973112f9a0
https://github.com/llvm/llvm-project/commit/be9f72cf3716bc1de5912a457284a1973112f9a0
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
R llvm/test/Transforms/ConstraintElimination/uadd-usub-sat.ll
Log Message:
-----------
Revert "[ConstraintElim] Simplify cmp after uadd.sat/usub.sat (#135603)"
This reverts commit fe54d1afcca055f464840654dd2ec3fd83aea688.
Causes miscompiles, see #135603.
Commit: 915de1a5889c4dad1ec7b77ac5c41ebabc20a8ca
https://github.com/llvm/llvm-project/commit/915de1a5889c4dad1ec7b77ac5c41ebabc20a8ca
Author: Devon Loehr <DKLoehr at users.noreply.github.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M clang/test/Format/lit.local.cfg
Log Message:
-----------
Generate empty .clang-format-ignore before running tests (#136154)
Followup to #136022, this ensures formatting tests are run with an empty
`.clang-format-ignore` in their root directory, to prevent failures if
the file also exists higher in the tree.
Commit: 273aecdb2008a58593aa1baf175e5e6e2aec1df5
https://github.com/llvm/llvm-project/commit/273aecdb2008a58593aa1baf175e5e6e2aec1df5
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M flang-rt/include/flang-rt/runtime/io-stmt.h
Log Message:
-----------
[flang-rt] Use runtime::memchr instead of std::memchr. (#135298)
Commit: 6c5f50f18694a4d91d7ce53a14188c54ee7c6f3b
https://github.com/llvm/llvm-project/commit/6c5f50f18694a4d91d7ce53a14188c54ee7c6f3b
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M offload/test/lit.cfg
Log Message:
-----------
[Offload] Fix typo on `-Xoffload-linker`
Commit: b3d2dc321c5c78b7204696afe07fe6ef3375acfd
https://github.com/llvm/llvm-project/commit/b3d2dc321c5c78b7204696afe07fe6ef3375acfd
Author: Paul Kirth <paulkirth at google.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
A llvm/test/CodeGen/RISCV/pr135206.ll
Log Message:
-----------
[RISCV] Fix assertion failure when using -fstack-clash-protection (#135248)
We can't assume MBBI is still pointing at MBB if we've already expanded
a probe. We need to re-query the MBB from MBBI. Fixes #135206
Co-authored-by: Craig Topper <craig.topper at sifive.com>
Commit: 711301066c2e5a6842866baea50ea9346b837459
https://github.com/llvm/llvm-project/commit/711301066c2e5a6842866baea50ea9346b837459
Author: Eli Friedman <efriedma at quicinc.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef] Add a description of the semantics of call signatures. (#136189)
This doesn't introduce anything new; it's just a reflection of the
semantics we've already had for many years.
Per discussion on #63484.
Commit: f4a47b4003b6cfbdd445615b044f0911d99a0e44
https://github.com/llvm/llvm-project/commit/f4a47b4003b6cfbdd445615b044f0911d99a0e44
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M lldb/test/API/commands/expression/import-std-module/deque-dbg-info-content/TestDbgInfoContentDequeFromStdModule.py
Log Message:
-----------
Disable test on older compilers. (#136322)
Commit: bc48b3f8b812c755c5e9c42d6b970a9c1b496578
https://github.com/llvm/llvm-project/commit/bc48b3f8b812c755c5e9c42d6b970a9c1b496578
Author: Daniel Bertalan <dani at danielbertalan.dev>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
A lld/test/wasm/lto/thinlto-signature-mismatch-unknown.ll
M lld/wasm/LTO.cpp
Log Message:
-----------
[lld][WebAssembly] Fix spurious signature mismatch under LTO (#136197)
When generating C++ vtables, Clang declares virtual functions as
`void(void)` when their signature is not known (e.g.parameter types are
forward-declared). As WASM type checks imports, this would conflict with
the real definition during linking. Commit 59f959ff introduced a
workaround for this by deferring signature assignment until a definition
or direct call is seen.
When performing LTO, LLD first scans the bitcode files and creates
`DefinedFunction` symbol table entries for their contents. After LTO
codegen, they are replaced with `UndefinedFunction`s (so that the
definitions will be pulled in from the native LTO-d files when they are
added). At this point, if a function is only referenced in bitcode, its
signature remains `nullptr`.
>From here, it should have behaved like in the non-LTO case: the first
direct call sets the signature. However, as the `isCalledDirectly` flag
was set to true, the missing signature was filled in by the type of the
first reference to the function, which could be a `void(void)` vtable
entry, which would then conflict with the real definition.
This commit sets `isCalledDirectly` to false so that the signature will
only be populated when a direct call is found.
See godotengine/godot#104497 and
emscripten-core/emscripten#10831
Commit: ad6c23a7b5ecd5582566a6e51c1aa8105fb3f109
https://github.com/llvm/llvm-project/commit/ad6c23a7b5ecd5582566a6e51c1aa8105fb3f109
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/include/llvm/Support/InterleavedRange.h
M llvm/unittests/Support/InterleavedRangeTest.cpp
Log Message:
-----------
[Support] Allow `llvm::interleaved` with custom ostream types (#136318)
This makes `llvm::interleaved` useable with ostream types that define
custom stream operators that print in a different format from
`raw_ostream`. For example, MLIR's OpAsmPrinter prints values as
operands:
https://github.com/llvm/llvm-project/blob/6c5f50f18694a4d91d7ce53a14188c54ee7c6f3b/mlir/include/mlir/IR/OpImplementation.h#L534-L552
Commit: 4cb9a3700c31357821e192124baeb3a3a35ff93b
https://github.com/llvm/llvm-project/commit/4cb9a3700c31357821e192124baeb3a3a35ff93b
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M flang/lib/Optimizer/CodeGen/LowerRepackArrays.cpp
M flang/lib/Optimizer/HLFIR/Transforms/InlineElementals.cpp
M flang/lib/Optimizer/HLFIR/Transforms/InlineHLFIRAssign.cpp
M flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
M flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/AssumedRankOpConversion.cpp
M flang/lib/Optimizer/Transforms/ConstantArgumentGlobalisation.cpp
M flang/lib/Optimizer/Transforms/SimplifyFIROperations.cpp
M flang/lib/Optimizer/Transforms/StackArrays.cpp
M mlir/include/mlir/Transforms/GreedyPatternRewriteDriver.h
M mlir/include/mlir/Transforms/Passes.td
M mlir/lib/Dialect/Affine/TransformOps/AffineTransformOps.cpp
M mlir/lib/Dialect/Affine/Transforms/AffineDataCopyGeneration.cpp
M mlir/lib/Dialect/Affine/Transforms/SimplifyAffineStructures.cpp
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/lib/Dialect/Affine/Utils/Utils.cpp
M mlir/lib/Dialect/Arith/Transforms/IntRangeOptimizations.cpp
M mlir/lib/Dialect/Bufferization/Transforms/BufferDeallocationSimplification.cpp
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp
M mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp
M mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
M mlir/lib/Dialect/Transform/IR/TransformOps.cpp
M mlir/lib/Reducer/ReductionTreePass.cpp
M mlir/lib/Transforms/Canonicalizer.cpp
M mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
M mlir/test/lib/Dialect/Affine/TestAffineDataCopy.cpp
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
Log Message:
-----------
Revert "[mlir] add a fluent API to GreedyRewriterConfig (#132253)"
This reverts commit 63b8f1c9482ed0a964980df4aed89bef922b8078.
Buildbot failure:
https://lab.llvm.org/buildbot/#/builders/172/builds/12083/steps/5/logs/stdio
I've reproduced the error with a release build (-DCMAKE_BUILD_TYPE=Release).
Commit: 7da385d79729bb7aa1bfc046d3a78e350b7a4f75
https://github.com/llvm/llvm-project/commit/7da385d79729bb7aa1bfc046d3a78e350b7a4f75
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td
M mlir/include/mlir/Interfaces/FunctionInterfaces.td
M mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp
M mlir/lib/Dialect/Bufferization/Transforms/BufferResultsToOutParams.cpp
M mlir/lib/Dialect/Bufferization/Transforms/DropEquivalentBufferResults.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
M mlir/lib/Query/Query.cpp
M mlir/lib/Transforms/RemoveDeadValues.cpp
M mlir/test/IR/test-func-erase-result.mlir
M mlir/test/lib/IR/TestFunc.cpp
Log Message:
-----------
Revert "[mlir] allow function type cloning to fail (#136300)"
This reverts commit 20a104a7d6423784dab04371a5ca728cc27a15a9.
Buildbot failure:
https://lab.llvm.org/buildbot/#/builders/157/builds/25688
I've reproduced the build failure.
Commit: 46d1cb8335e988e2a9e48b46d80c639a2364a8f9
https://github.com/llvm/llvm-project/commit/46d1cb8335e988e2a9e48b46d80c639a2364a8f9
Author: Ivan Butygin <ivan.butygin at gmail.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
R mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-unsupported.mlir
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir
M mlir/test/Dialect/GPU/invalid.mlir
Log Message:
-----------
[mlir] GPUToROCDL: Add support for non-i32/f32 shuffle types (#136320)
Use recently added repacking utilities to support other datatypes.
Also, tighten `gpu.shuffle` verification to reject scalable vectors
Commit: 4c17a5c66346089bf445176c77b36d6ed91d09bd
https://github.com/llvm/llvm-project/commit/4c17a5c66346089bf445176c77b36d6ed91d09bd
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
Log Message:
-----------
[mlir] Fix a warning
This patch fixes:
mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp:140:10:
error: unused variable 'shflType' [-Werror,-Wunused-variable]
Commit: f696508b38d1958aac5992a98a90fe6e773e8709
https://github.com/llvm/llvm-project/commit/f696508b38d1958aac5992a98a90fe6e773e8709
Author: Nikita Popov <nikita.ppv at gmail.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h
Log Message:
-----------
[BFI] Revert use of append_range (NFC)
This is a partial revert of #136066, which introduced a compile-time
regression. SmallVector::insert() computes the PostOrderIterator
twice in order to call reserve().
Commit: 5eabececb0a3c7e761ddda2e49430baa834f2c65
https://github.com/llvm/llvm-project/commit/5eabececb0a3c7e761ddda2e49430baa834f2c65
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M offload/test/jit/empty_kernel.inc
M offload/test/jit/empty_kernel_lvl2.c
Log Message:
-----------
[Offload] Fix JIT test
Commit: d3d9b376c01ac4dff1457a98de81eca5cbb648a1
https://github.com/llvm/llvm-project/commit/d3d9b376c01ac4dff1457a98de81eca5cbb648a1
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/include/llvm/DebugInfo/LogicalView/Core/LVOptions.h
Log Message:
-----------
[DebugInfo] Call std::erase directly (NFC) (#136261)
Commit: 2a692d265bbd84dae807d470caed7be507e4118d
https://github.com/llvm/llvm-project/commit/2a692d265bbd84dae807d470caed7be507e4118d
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/include/llvm/DebugInfo/LogicalView/Core/LVOptions.h
Log Message:
-----------
[DebugInfo] Use std::move (NFC) (#136263)
Commit: c244daec1cbcd221c073fc40284ee23399257684
https://github.com/llvm/llvm-project/commit/c244daec1cbcd221c073fc40284ee23399257684
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/utils/TableGen/DecoderEmitter.cpp
Log Message:
-----------
[LLVM][TableGen] Fix Windows failure in DecoderEmitter (#136310)
- Avoid dereferencing the end() iterator to get the end pointer, instead
calculate it explicitly
- Fixes a regression introduced in
https://github.com/llvm/llvm-project/pull/136220.
- The windows build failure shows the following call stack:
```
| Exception Code: 0x80000003
| #0 0x00007ff74bc05897 std::_Vector_const_iterator<class std::_Vector_val<struct std::_Simple_types<unsigned char>>>::operator*(void) const C:\Program Files\Microsoft Visual Studio\2022\Professional\VC\Tools\MSVC\14.37.32822\include\vector:52:0
| #1 0x00007ff74bbd3d64 `anonymous namespace'::DecoderEmitter::emitTable D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\llvm\utils\TableGen\DecoderEmitter.cpp:852:0
```
Commit: 5e1b0f97735083b6762834b83fdbb35e76002e03
https://github.com/llvm/llvm-project/commit/5e1b0f97735083b6762834b83fdbb35e76002e03
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/tools/llvm-gpu-loader/nvptx.cpp
Log Message:
-----------
[llvm] Use llvm::less_first and llvm::less_second (NFC) (#136272)
Commit: f5947ba5a659d6b3ed62761a7afdf1626435abcb
https://github.com/llvm/llvm-project/commit/f5947ba5a659d6b3ed62761a7afdf1626435abcb
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M clang/lib/AST/Decl.cpp
M clang/test/CodeGenCXX/visibility.cpp
Log Message:
-----------
Revert "[clang] Handle instantiated members to determine visibility" (#136317)
Reverts llvm/llvm-project#136128
See discussion here:
https://github.com/llvm/llvm-project/pull/136128#issuecomment-2815648110
and :
https://github.com/llvm/llvm-project/pull/136128#issuecomment-2815652846
@asavonic can re-submit once the examples provided by @jplehr and/or
@DKLoehr are fixed.
Commit: 61820156980ff20ca6e8a7a43a1e9debb950db85
https://github.com/llvm/llvm-project/commit/61820156980ff20ca6e8a7a43a1e9debb950db85
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/utils/TableGen/DecoderEmitter.cpp
Log Message:
-----------
[NFC][LLVM][TableGen] Adjust pointer increments in DecoderEmitter (#136230)
- In both `emitTable` and the generated `decodeInstruction` function
increment the pointer to the decoder op as a part of the switch
statement instead of later on in each case.
Commit: 23020a8d01a3f58e4903c42eba4b803d5809653e
https://github.com/llvm/llvm-project/commit/23020a8d01a3f58e4903c42eba4b803d5809653e
Author: Nirvedh Meshram <96096277+nirvedhmeshram at users.noreply.github.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M mlir/lib/Dialect/Tensor/IR/TensorTilingInterfaceImpl.cpp
M mlir/test/Dialect/Linalg/matmul-shared-memory-padding.mlir
M mlir/test/Dialect/Linalg/subtensor-of-padtensor.mlir
Log Message:
-----------
[mlir] Add optimization to bubbleUpPadSlice pattern for no pad case (#135859)
In cases where there is no padding on a dim, we do not need to compute
new offsets, lengths and padding, for example the new test case added
can just be lowered to
```
%extracted_slice = tensor.extract_slice %arg0[%arg2, 1, 2] [%arg2, 2, 1] [1, 1, 1] : tensor<3x4x5xf32> to tensor<?x2x1xf32>
```
without this PR we will have affine maps like
```
#map = affine_map<()[s0] -> (3, s0)>
#map1 = affine_map<()[s0, s1] -> (-s0 + 3, s1)>
%0 = affine.min #map()[%arg2]
%1 = affine.min #map1()[%0, %arg2]
%extracted_slice = tensor.extract_slice %arg0[%0, 1, 2] [%1, 2, 1] [1, 1, 1] : tensor<3x4x5xf32> to tensor<?x2x1xf32>
```
which are unnecessary
Signed-off-by: Nirvedh <nirvedh at gmail.com>
Commit: 5ad32fa6973638a091891942939933a41cbb2162
https://github.com/llvm/llvm-project/commit/5ad32fa6973638a091891942939933a41cbb2162
Author: Andrei Safronov <andrei.safronov at espressif.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaFeatures.td
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaSubtarget.h
M llvm/test/CodeGen/Xtensa/callw.ll
M llvm/test/CodeGen/Xtensa/div.ll
M llvm/test/CodeGen/Xtensa/mul.ll
A llvm/test/CodeGen/Xtensa/rem.ll
A llvm/test/MC/Xtensa/div.s
A llvm/test/MC/Xtensa/mul.s
Log Message:
-----------
[Xtensa] Implement Xtensa Mul and Div Options. (#132157)
Implement Xtensa Mul16, Mul32, Mul32High and Div32 Options. Also fix callw test.
Commit: 58774f1b1f98402c8d62cdde01c1adea067aaf96
https://github.com/llvm/llvm-project/commit/58774f1b1f98402c8d62cdde01c1adea067aaf96
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/lib/CodeGen/RegAllocFast.cpp
M llvm/lib/CodeGen/RegisterUsageInfo.cpp
Log Message:
-----------
[CodeGen] Construct SmallVector with iterator ranges (NFC) (#136258)
Commit: b2ba53172e82354e1318ae7e18c637ac2107aeca
https://github.com/llvm/llvm-project/commit/b2ba53172e82354e1318ae7e18c637ac2107aeca
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/lib/Transforms/IPO/ExpandVariadics.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/IndVarSimplify.cpp
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/lib/Transforms/Scalar/LoopSimplifyCFG.cpp
M llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[Transforms] Construct SmallVector with iterator ranges (NFC) (#136259)
Commit: e298f16e895f1c3e5571ec1adb84f29646b84637
https://github.com/llvm/llvm-project/commit/e298f16e895f1c3e5571ec1adb84f29646b84637
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
A clang/include/clang/CIR/Dialect/IR/CIRDataLayout.h
M clang/include/clang/CIR/Dialect/IR/CIRTypes.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenRecordLayoutBuilder.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/test/CIR/CodeGen/struct.c
Log Message:
-----------
[CIR] Upstream support for record packing and padding (#136036)
This change adds support for packing and padding record types in ClangIR
and introduces some infrastructure needed for this computation.
Although union support has not been upstreamed yet, there is no good way
to report unions as NYI in the layout computation, so the code added
here includes layout computation for unions. Unions will be added soon.
Commit: fdcee2dd3687053cf8c69a24178c489d6977e93e
https://github.com/llvm/llvm-project/commit/fdcee2dd3687053cf8c69a24178c489d6977e93e
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/revec.ll
Log Message:
-----------
[SLP]Reorder tree, if the reorder indices are non empty
Need to consider the ordering for all nodes with the specified ordering,
not only loads/store/extracts.
Reviewers: hiraditya, RKSimon
Reviewed By: hiraditya
Pull Request: https://github.com/llvm/llvm-project/pull/136185
Commit: 5d0de16c25ea828fd6f50ece1c705f5ed1653c73
https://github.com/llvm/llvm-project/commit/5d0de16c25ea828fd6f50ece1c705f5ed1653c73
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-04-18 (Fri, 18 Apr 2025)
Changed paths:
M .github/new-prs-labeler.yml
M bolt/lib/Core/BinaryEmitter.cpp
M bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
M bolt/test/AArch64/lite-mode.s
M clang-tools-extra/test/clang-tidy/checkers/abseil/string-find-startswith.cpp
M clang-tools-extra/test/clang-tidy/checkers/bugprone/misplaced-operator-in-strlen-in-alloc.c
M clang-tools-extra/test/clang-tidy/checkers/bugprone/reserved-identifier-c.c
M clang-tools-extra/test/clang-tidy/checkers/bugprone/reserved-identifier.cpp
M clang-tools-extra/test/clang-tidy/checkers/google/explicit-constructor.cpp
M clang-tools-extra/test/clang-tidy/checkers/google/readability-casting.cpp
M clang-tools-extra/test/clang-tidy/checkers/llvm/qualified-auto.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/definitions-in-headers.hpp
M clang-tools-extra/test/clang-tidy/checkers/misc/static-assert.c
M clang-tools-extra/test/clang-tidy/checkers/misc/static-assert.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/unused-alias-decls.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/unused-using-decls.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/make-unique-macros.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/raw-string-literal-delimiter.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/raw-string-literal-replace-shorter.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/shrink-to-fit.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/unary-static-assert.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-bool-literals-ignore-macros.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-override-cxx98.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-transparent-functors.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-using.cpp
M clang/cmake/caches/Fuchsia-stage2.cmake
M clang/docs/ClangOffloadPackager.rst
M clang/docs/LibASTImporter.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/RecordLayout.h
M clang/include/clang/Basic/DiagnosticSemaKinds.td
A clang/include/clang/CIR/Dialect/IR/CIRDataLayout.h
M clang/include/clang/CIR/Dialect/IR/CIRTypes.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/include/clang/Driver/Options.td
M clang/include/clang/Sema/Overload.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/RecordLayoutBuilder.cpp
M clang/lib/CIR/CodeGen/CIRGenRecordLayoutBuilder.cpp
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/SanitizerMetadata.cpp
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/lib/CodeGen/Targets/AArch64.cpp
M clang/lib/Driver/SanitizerArgs.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/XRayArgs.cpp
M clang/lib/Format/FormatToken.h
M clang/lib/Frontend/DiagnosticRenderer.cpp
M clang/lib/Parse/ParseExpr.cpp
M clang/lib/Sema/SemaARM.cpp
M clang/lib/Sema/SemaCodeComplete.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaSYCL.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/test/CIR/CodeGen/struct.c
M clang/test/CXX/temp/temp.constr/temp.constr.atomic/constrant-satisfaction-conversions.cpp
M clang/test/CodeGen/AArch64/args.cpp
M clang/test/CodeGen/aapcs64-align.cpp
M clang/test/CodeGen/arm-vfp16-arguments2.cpp
M clang/test/CodeGen/memtag-globals-asm.cpp
M clang/test/CodeGen/memtag-globals.cpp
M clang/test/CodeGen/p0963r3.cpp
M clang/test/CodeGenCXX/mangle-template.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn.cl
M clang/test/CodeGenOpenCL/builtins-r600.cl
M clang/test/Driver/clang-sycl-linker-test.cpp
M clang/test/Driver/clang-translation.c
M clang/test/Driver/fsanitize.c
M clang/test/Driver/linker-wrapper.c
M clang/test/Driver/openmp-offload-gpu.c
M clang/test/Driver/sanitizer-ld.c
M clang/test/Format/lit.local.cfg
M clang/test/Headers/gpuintrin.c
M clang/test/Headers/gpuintrin_lang.c
M clang/test/Misc/warning-flags.c
A clang/test/Modules/non-modular-decl-use.c
M clang/test/Parser/recovery.cpp
M clang/test/Sema/ptrauth-qualifier.c
M clang/test/Sema/ptrauth.c
M clang/test/SemaCUDA/function-overload.cu
M clang/test/SemaCXX/implicit-member-functions.cpp
A clang/test/SemaCXX/overload-resolution-deferred-templates.cpp
A clang/test/SemaCXX/uninitialized-no-ctor.cpp
M clang/test/SemaObjC/ptrauth-qualifier.m
A clang/test/SemaSYCL/Inputs/vectorcall.hpp
A clang/test/SemaSYCL/sycl-cconv-win.cpp
M clang/test/SemaTemplate/instantiate-function-params.cpp
M clang/test/Templight/templight-empty-entries-fix.cpp
M clang/tools/clang-installapi/ClangInstallAPI.cpp
M clang/tools/clang-installapi/Options.cpp
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M clang/tools/clang-sycl-linker/ClangSYCLLinker.cpp
M clang/unittests/Format/CMakeLists.txt
M clang/unittests/Format/TokenAnnotatorTest.cpp
M compiler-rt/lib/scudo/standalone/CMakeLists.txt
M compiler-rt/lib/scudo/standalone/allocator_config.def
M compiler-rt/lib/scudo/standalone/combined.h
R compiler-rt/lib/scudo/standalone/local_cache.h
M compiler-rt/lib/scudo/standalone/primary32.h
M compiler-rt/lib/scudo/standalone/primary64.h
A compiler-rt/lib/scudo/standalone/size_class_allocator.h
M compiler-rt/lib/scudo/standalone/tests/combined_test.cpp
M compiler-rt/lib/scudo/standalone/tests/primary_test.cpp
M compiler-rt/lib/scudo/standalone/tests/tsd_test.cpp
M compiler-rt/lib/scudo/standalone/tsd.h
M compiler-rt/lib/scudo/standalone/tsd_shared.h
M compiler-rt/lib/scudo/standalone/type_traits.h
M flang-rt/include/flang-rt/runtime/io-stmt.h
M flang/include/flang/Optimizer/Dialect/CUF/CUFOps.td
M flang/lib/Lower/ConvertCall.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Optimizer/CodeGen/Target.cpp
M flang/lib/Optimizer/Dialect/CUF/CUFOps.cpp
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/lib/Optimizer/Transforms/SimplifyIntrinsics.cpp
M flang/test/Fir/CUDA/cuda-launch.fir
M flang/test/Fir/comdat.fir
M flang/test/Fir/target-rewrite-complex.fir
M flang/test/Lower/CUDA/cuda-kernel-calls.cuf
M flang/test/Lower/OpenACC/acc-kernels-loop.f90
M flang/test/Lower/OpenACC/acc-loop.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-private-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-private.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
M flang/test/Transforms/simplifyintrinsics.fir
M libcxx/docs/Contributing.rst
M libcxx/include/CMakeLists.txt
M libcxx/include/__type_traits/is_signed.h
M libcxx/include/__type_traits/is_unsigned.h
R libcxx/include/module.modulemap
A libcxx/include/module.modulemap.in
A libcxx/test/libcxx/Wnon_modular_include_in_module.compile.pass.cpp
M libcxx/test/libcxx/headers_in_modulemap.sh.py
M libcxx/test/libcxx/lint/lint_headers.sh.py
M libcxx/utils/libcxx/header_information.py
M libcxxabi/src/demangle/ItaniumDemangle.h
M libcxxabi/src/demangle/Utility.h
A lld/test/wasm/lto/thinlto-signature-mismatch-unknown.ll
M lld/wasm/LTO.cpp
M lldb/include/lldb/Target/ThreadPlanStepOut.h
M lldb/source/Target/Thread.cpp
M lldb/source/Target/ThreadPlanStepOut.cpp
M lldb/test/API/commands/expression/diagnostics/TestExprDiagnostics.py
M lldb/test/API/commands/expression/import-std-module/deque-dbg-info-content/TestDbgInfoContentDequeFromStdModule.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx-simulators/invalid-vector/TestDataFormatterLibcxxInvalidVectorSimulator.py
M lldb/unittests/Core/TelemetryTest.cpp
M llvm/docs/InstCombineContributorGuide.md
M llvm/docs/LangRef.rst
M llvm/docs/ProgrammersManual.rst
M llvm/docs/SandboxIR.md
M llvm/docs/Vectorizers.rst
M llvm/include/llvm/Analysis/AliasAnalysis.h
M llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h
M llvm/include/llvm/Analysis/MemoryLocation.h
M llvm/include/llvm/CodeGen/CFIInstBuilder.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/CodeGen/UnreachableBlockElim.h
M llvm/include/llvm/DebugInfo/LogicalView/Core/LVOptions.h
M llvm/include/llvm/Demangle/ItaniumDemangle.h
M llvm/include/llvm/Demangle/Utility.h
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/MC/MCFixup.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/SandboxIR/Constant.h
M llvm/include/llvm/SandboxIR/Type.h
M llvm/include/llvm/SandboxIR/Value.h
M llvm/include/llvm/Support/InterleavedRange.h
M llvm/include/llvm/Support/UnicodeCharRanges.h
M llvm/lib/Analysis/AliasAnalysis.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/LiveVariables.cpp
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/RegAllocFast.cpp
M llvm/lib/CodeGen/RegisterUsageInfo.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetInstrInfo.cpp
M llvm/lib/CodeGen/UnreachableBlockElim.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/lib/MC/MCAssembler.cpp
M llvm/lib/Object/OffloadBinary.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/ProfileData/MemProfReader.cpp
M llvm/lib/SandboxIR/Type.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
M llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
M llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
M llvm/lib/Target/MSP430/MSP430FrameLowering.cpp
M llvm/lib/Target/Mips/Mips16HardFloat.cpp
M llvm/lib/Target/Mips/Mips16ISelLowering.cpp
M llvm/lib/Target/Mips/MipsCCState.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.h
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
M llvm/lib/Target/RISCV/RISCVProfiles.td
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/Sparc/SparcISelLowering.h
M llvm/lib/Target/Sparc/SparcInstrVIS.td
M llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/Xtensa/XtensaFeatures.td
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaSubtarget.h
M llvm/lib/Transforms/IPO/ExpandVariadics.cpp
M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/IndVarSimplify.cpp
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/lib/Transforms/Scalar/LoopSimplifyCFG.cpp
M llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
M llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
M llvm/lib/Transforms/Utils/FlattenCFG.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/lib/Transforms/Utils/SimplifyIndVar.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/test/Analysis/CostModel/RISCV/shuffle-permute.ll
M llvm/test/Assembler/auto_upgrade_nvvm_intrinsics.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-inline.ll
M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
A llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.fpmath.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.iterative.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id-unsupported-calling-convention.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/v_add_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/Hexagon/unreachable-mbb-phi-subreg.mir
A llvm/test/CodeGen/LoongArch/lasx/broadcast-load.ll
A llvm/test/CodeGen/LoongArch/lsx/broadcast-load.ll
A llvm/test/CodeGen/NVPTX/fp128-storage-type.ll
M llvm/test/CodeGen/NVPTX/global-variable-big.ll
A llvm/test/CodeGen/RISCV/pr135206.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-binop-splats.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
M llvm/test/CodeGen/RISCV/rvv/fold-scalar-load-crash.ll
M llvm/test/CodeGen/RISCV/rvv/pr125306.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
A llvm/test/CodeGen/SPARC/bitcast.ll
A llvm/test/CodeGen/SPARC/ctlz.ll
M llvm/test/CodeGen/Xtensa/callw.ll
M llvm/test/CodeGen/Xtensa/div.ll
M llvm/test/CodeGen/Xtensa/mul.ll
A llvm/test/CodeGen/Xtensa/rem.ll
A llvm/test/DebugInfo/AArch64/merge-nested-block-loc.ll
A llvm/test/DebugInfo/AArch64/merge-nested-block-loc2.ll
M llvm/test/DebugInfo/MIR/X86/unreachable-block-call-site.mir
M llvm/test/MC/AArch64/tls-relocs.s
M llvm/test/MC/AVR/inst-adiw.s
M llvm/test/MC/AVR/inst-andi.s
M llvm/test/MC/AVR/inst-brbc.s
M llvm/test/MC/AVR/inst-brbs.s
M llvm/test/MC/AVR/inst-brcc.s
M llvm/test/MC/AVR/inst-brcs.s
M llvm/test/MC/AVR/inst-breq.s
M llvm/test/MC/AVR/inst-brge.s
M llvm/test/MC/AVR/inst-brhc.s
M llvm/test/MC/AVR/inst-brhs.s
M llvm/test/MC/AVR/inst-brid.s
M llvm/test/MC/AVR/inst-brie.s
M llvm/test/MC/AVR/inst-brlo.s
M llvm/test/MC/AVR/inst-brlt.s
M llvm/test/MC/AVR/inst-brmi.s
M llvm/test/MC/AVR/inst-brne.s
M llvm/test/MC/AVR/inst-brpl.s
M llvm/test/MC/AVR/inst-brsh.s
M llvm/test/MC/AVR/inst-brtc.s
M llvm/test/MC/AVR/inst-brts.s
M llvm/test/MC/AVR/inst-brvc.s
M llvm/test/MC/AVR/inst-brvs.s
M llvm/test/MC/AVR/inst-call.s
M llvm/test/MC/AVR/inst-cbi.s
M llvm/test/MC/AVR/inst-cpi.s
M llvm/test/MC/AVR/inst-in.s
M llvm/test/MC/AVR/inst-jmp.s
M llvm/test/MC/AVR/inst-ldd.s
M llvm/test/MC/AVR/inst-ldi.s
M llvm/test/MC/AVR/inst-lds-tiny.s
M llvm/test/MC/AVR/inst-lds.s
M llvm/test/MC/AVR/inst-ori.s
M llvm/test/MC/AVR/inst-out.s
M llvm/test/MC/AVR/inst-rcall.s
M llvm/test/MC/AVR/inst-rjmp.s
M llvm/test/MC/AVR/inst-sbci.s
M llvm/test/MC/AVR/inst-sbi.s
M llvm/test/MC/AVR/inst-sbic.s
M llvm/test/MC/AVR/inst-sbis.s
M llvm/test/MC/AVR/inst-sbiw.s
M llvm/test/MC/AVR/inst-sbr.s
M llvm/test/MC/AVR/inst-std.s
M llvm/test/MC/AVR/inst-sts-tiny.s
M llvm/test/MC/AVR/inst-sts.s
M llvm/test/MC/AVR/inst-subi.s
M llvm/test/MC/AVR/modifiers.s
M llvm/test/MC/CSKY/basic-16bit.s
M llvm/test/MC/CSKY/basic.s
M llvm/test/MC/LoongArch/Relocations/relax-tls-le.s
M llvm/test/MC/LoongArch/Relocations/relocations.s
M llvm/test/MC/RISCV/corev/XCVmem-invalid.s
M llvm/test/MC/RISCV/fixups-binary-expression.s
M llvm/test/MC/RISCV/function-call.s
M llvm/test/MC/RISCV/linker-relaxation.s
M llvm/test/MC/RISCV/option-exact.s
M llvm/test/MC/RISCV/pseudo-jump.s
M llvm/test/MC/RISCV/relocations.s
M llvm/test/MC/RISCV/rv32xtheadmempair-invalid.s
M llvm/test/MC/RISCV/rv64xtheadmempair-invalid.s
M llvm/test/MC/RISCV/tail-call.s
M llvm/test/MC/RISCV/xqcilb-relocations.s
M llvm/test/MC/RISCV/xqcili-relocations.s
M llvm/test/MC/Sparc/sparc-assembly-exprs.s
M llvm/test/MC/Sparc/sparc-ctrl-instructions.s
M llvm/test/MC/Sparc/sparc-little-endian.s
M llvm/test/MC/Sparc/sparc-relocations.s
M llvm/test/MC/Sparc/sparc-synthetic-instructions.s
M llvm/test/MC/Sparc/sparc-tls-relocations.s
M llvm/test/MC/Sparc/sparc64-ctrl-instructions.s
M llvm/test/MC/Sparc/sparcv9-synthetic-instructions.s
A llvm/test/MC/Xtensa/div.s
A llvm/test/MC/Xtensa/mul.s
R llvm/test/Transforms/ConstraintElimination/uadd-usub-sat.ll
M llvm/test/Transforms/IndVarSimplify/ARM/code-size.ll
M llvm/test/Transforms/IndVarSimplify/ARM/indvar-unroll-imm-cost.ll
A llvm/test/Transforms/IndVarSimplify/debugloc-rem-subst.ll
M llvm/test/Transforms/IndVarSimplify/exit-count-select.ll
M llvm/test/Transforms/IndVarSimplify/exit_value_test3.ll
M llvm/test/Transforms/IndVarSimplify/finite-exit-comparisons.ll
M llvm/test/Transforms/IndVarSimplify/pr116483.ll
M llvm/test/Transforms/IndVarSimplify/pr63763.ll
M llvm/test/Transforms/IndVarSimplify/replace-loop-exit-folds.ll
M llvm/test/Transforms/IndVarSimplify/sentinel.ll
M llvm/test/Transforms/InstCombine/icmp-dom.ll
M llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-for-private.ll
M llvm/test/Transforms/LoopUnroll/unroll-cleanup.ll
M llvm/test/Transforms/PhaseOrdering/ARM/arm_mean_q7.ll
M llvm/test/Transforms/SLPVectorizer/revec.ll
M llvm/test/Transforms/Util/flatten-cfg.ll
M llvm/test/tools/llvm-reduce/thinlto-preserve-uselistorder.ll
M llvm/tools/llvm-cov/CodeCoverage.cpp
M llvm/tools/llvm-gpu-loader/nvptx.cpp
M llvm/tools/yaml2obj/CMakeLists.txt
M llvm/unittests/Analysis/AliasAnalysisTest.cpp
M llvm/unittests/Demangle/ItaniumDemangleTest.cpp
M llvm/unittests/Demangle/OutputBufferTest.cpp
M llvm/unittests/IR/MetadataTest.cpp
M llvm/unittests/IR/VerifierTest.cpp
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
M llvm/unittests/Support/InterleavedRangeTest.cpp
M llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/TableGen/DecoderEmitter.cpp
M llvm/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp
M llvm/utils/gn/secondary/compiler-rt/lib/scudo/standalone/BUILD.gn
M mlir/include/mlir-c/Dialect/Linalg.h
M mlir/include/mlir/Conversion/LLVMCommon/Pattern.h
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
M mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
M mlir/lib/Bindings/Python/DialectLinalg.cpp
M mlir/lib/CAPI/Dialect/Linalg.cpp
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
M mlir/lib/Conversion/LLVMCommon/Pattern.cpp
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/lib/Dialect/GPU/TransformOps/GPUTransformOps.cpp
M mlir/lib/Dialect/SPIRV/IR/ControlFlowOps.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVAttributes.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
M mlir/lib/Dialect/Tensor/IR/TensorTilingInterfaceImpl.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorUnroll.cpp
M mlir/lib/Dialect/Vector/Utils/VectorUtils.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
M mlir/lib/Target/LLVM/NVVM/Target.cpp
A mlir/test/Conversion/AMDGPUToROCDL/swizzle.mlir
R mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-unsupported.mlir
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir
M mlir/test/Conversion/MemRefToLLVM/memref-to-llvm.mlir
M mlir/test/Dialect/AMDGPU/invalid.mlir
M mlir/test/Dialect/AMDGPU/ops.mlir
M mlir/test/Dialect/GPU/invalid.mlir
M mlir/test/Dialect/Linalg/matmul-shared-memory-padding.mlir
M mlir/test/Dialect/Linalg/subtensor-of-padtensor.mlir
M mlir/test/Dialect/Vector/canonicalize.mlir
M mlir/test/Dialect/XeGPU/invalid.mlir
M mlir/test/Dialect/XeGPU/ops.mlir
M mlir/test/python/dialects/linalg/utils.py
M offload/DeviceRTL/CMakeLists.txt
R offload/DeviceRTL/src/exports
M offload/test/jit/empty_kernel.inc
M offload/test/jit/empty_kernel_lvl2.c
M offload/test/lit.cfg
M openmp/runtime/src/kmp_config.h.cmake
M openmp/runtime/src/z_Linux_util.cpp
M utils/bazel/llvm-project-overlay/libc/libc_build_rules.bzl
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Rebase
Created using spr 1.3.5
Compare: https://github.com/llvm/llvm-project/compare/91aa3f2561be...5d0de16c25ea
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