[all-commits] [llvm/llvm-project] 722d58: [RISCV] Lower e64 vector_deinterleave via ri.vunzi...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 722d5890cc0d6e3879ebe43b43405f102f658e30
      https://github.com/llvm/llvm-project/commit/722d5890cc0d6e3879ebe43b43405f102f658e30
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2025-04-18 (Fri, 18 Apr 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll

  Log Message:
  -----------
  [RISCV] Lower e64 vector_deinterleave via ri.vunzip2{a,b} if available (#136321)

If XRivosVizip is available, the ri.vunzip2a and ri.vunzip2b can be used
to the concatenation and register deinterleave shuffle. This patch only
effects the intrinsic lowering (and thus scalable vectors because the
fixed vectors go through shuffle lowering).

Note that this patch is restricted to e64 for staging purposes only. e64
is obviously profitable (i.e. we remove a vcompress). At e32 and below,
our alternative is a vnsrl instead, and we need a bit more complexity
around lowering with fractional LMUL before the ri.vunzip2a/b versions
becomes always profitable. I'll post the followup change once this
lands.



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