[all-commits] [llvm/llvm-project] 23020a: [mlir] Add optimization to bubbleUpPadSlice patter...

[Nirvedh Meshram via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 23020a8d01a3f58e4903c42eba4b803d5809653e
      https://github.com/llvm/llvm-project/commit/23020a8d01a3f58e4903c42eba4b803d5809653e
  Author: Nirvedh Meshram <96096277+nirvedhmeshram at users.noreply.github.com>
  Date:   2025-04-18 (Fri, 18 Apr 2025)

  Changed paths:
    M mlir/lib/Dialect/Tensor/IR/TensorTilingInterfaceImpl.cpp
    M mlir/test/Dialect/Linalg/matmul-shared-memory-padding.mlir
    M mlir/test/Dialect/Linalg/subtensor-of-padtensor.mlir

  Log Message:
  -----------
  [mlir] Add optimization to bubbleUpPadSlice pattern for no pad case (#135859)

In cases where there is no padding on a dim, we do not need to compute
new offsets, lengths and padding, for example the new test case added
can just be lowered to
```
    %extracted_slice = tensor.extract_slice %arg0[%arg2, 1, 2] [%arg2, 2, 1] [1, 1, 1] : tensor<3x4x5xf32> to tensor<?x2x1xf32>
 ```
without this PR we will have affine maps like
 ```
#map = affine_map<()[s0] -> (3, s0)>
#map1 = affine_map<()[s0, s1] -> (-s0 + 3, s1)>
%0 = affine.min #map()[%arg2]
 %1 = affine.min #map1()[%0, %arg2]
 %extracted_slice = tensor.extract_slice %arg0[%0, 1, 2] [%1, 2, 1] [1, 1, 1] : tensor<3x4x5xf32> to tensor<?x2x1xf32>
 ```
  which are unnecessary

Signed-off-by: Nirvedh <nirvedh at gmail.com>



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications