[all-commits] [llvm/llvm-project] a35456: [RISCV] Strengthen register usage validation for X...

[Iris via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a354564a64c6ab3cafa9e5e2b31f7f14d4e27d45
      https://github.com/llvm/llvm-project/commit/a354564a64c6ab3cafa9e5e2b31f7f14d4e27d45
  Author: Iris <0.0 at owo.li>
  Date:   2025-04-18 (Fri, 18 Apr 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/test/MC/RISCV/rv32xtheadmempair-invalid.s
    M llvm/test/MC/RISCV/rv64xtheadmempair-invalid.s

  Log Message:
  -----------
  [RISCV] Strengthen register usage validation for XTheadMemPair loads (#136241)

Closes #136087


https://github.com/XUANTIE-RV/thead-extension-spec/blob/master/xtheadmempair/lwd.adoc



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