[all-commits] [llvm/llvm-project] b30100: [RISCV] Check that both registers of a CV Reg-Reg ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b30100b87f24847afd6407b4939a184ebcf16ef9
      https://github.com/llvm/llvm-project/commit/b30100b87f24847afd6407b4939a184ebcf16ef9
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-04-17 (Thu, 17 Apr 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
    M llvm/test/MC/RISCV/corev/XCVmem-invalid.s

  Log Message:
  -----------
  [RISCV] Check that both registers of a CV Reg-Reg memory address are GPRs. (#136079)

The assembly parser was checking for any register instead of GPR.

I've removed the custom diagnostic message from the RegReg operand to
give a less confusing error on bad input. The mnemonics are shared with
other encodings that don't use reg-reg memory operand.

I also fixed the parsed operand location, but I'm not sure it matters.



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