[all-commits] [llvm/llvm-project] 7866fc: [RISCV] Rewrite vrgather.vx undef, (vmv.s.x), 0, v...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7866fc2bd9f5e87ffdccecd06f5f877b81218bcd
      https://github.com/llvm/llvm-project/commit/7866fc2bd9f5e87ffdccecd06f5f877b81218bcd
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2025-04-17 (Thu, 17 Apr 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int.ll

  Log Message:
  -----------
  [RISCV] Rewrite vrgather.vx undef, (vmv.s.x), 0, v0 as vmv.v.x (#136010)

This extends the DAG combine introduced in 336b2909 to handle the case
where the prior value is defined by a vmv.s.x instead of a vmv.v.x. If
the vrgather splats the single source element, and has no passthru we
can replace it with a vmv.v.x - which will in turn usually get folded
into a vmerge if a select follows.



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