[all-commits] [llvm/llvm-project] 47f4f3: [MLIR][AMDGPU] Fixing word alignment check for buf...

[Zhuoran Yin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 47f4f39265b31e2249536b74d33d63508cdfb457
      https://github.com/llvm/llvm-project/commit/47f4f39265b31e2249536b74d33d63508cdfb457
  Author: Zhuoran Yin <zhuoryin at amd.com>
  Date:   2025-04-17 (Thu, 17 Apr 2025)

  Changed paths:
    M mlir/lib/Dialect/AMDGPU/Transforms/TransferReadToLoad.cpp
    M mlir/test/Dialect/AMDGPU/transfer-read-to-load.mlir
    M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel

  Log Message:
  -----------
  [MLIR][AMDGPU] Fixing word alignment check for bufferload fastpath (#135982)

`delta_bytes % (32 ceilDiv elementBitwidth) != 0` condition is incorrect
in https://github.com/llvm/llvm-project/pull/135014

For example, last load is issued to load only one last element of fp16.
Then `delta bytes = 2`, `(32 ceildiv 16) = 2`. In this case it will be
judged as word aligned. It will send to fast path but get all zeros for
the fp16 because it cross the word boundary.

In reality the equation should be just `delta_bytes % 4` , since a word
is 4 bytes. This PR fix the bug by amending the mod target to 4.



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