[all-commits] [llvm/llvm-project] 1588aa: [AArch64] Generalize integer FPR lane stores for a...

[Benjamin Maxwell via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1588aab6ed2d02db2ffb23ca7f339d38a4d8c5e9
      https://github.com/llvm/llvm-project/commit/1588aab6ed2d02db2ffb23ca7f339d38a4d8c5e9
  Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
  Date:   2025-04-17 (Thu, 17 Apr 2025)

  Changed paths:
    M llvm/include/llvm/CodeGen/ValueTypes.td
    M llvm/lib/CodeGen/ValueTypes.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/aarch64-sve-ldst-one.ll
    M llvm/test/CodeGen/AArch64/add.ll
    M llvm/test/CodeGen/AArch64/andorxor.ll
    M llvm/test/CodeGen/AArch64/arm64-collect-loh.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll
    M llvm/test/CodeGen/AArch64/arm64-rev.ll
    M llvm/test/CodeGen/AArch64/arm64-st1.ll
    M llvm/test/CodeGen/AArch64/bitcast-v2i8.ll
    M llvm/test/CodeGen/AArch64/concat-vector.ll
    M llvm/test/CodeGen/AArch64/ctlz.ll
    M llvm/test/CodeGen/AArch64/ctpop.ll
    M llvm/test/CodeGen/AArch64/cttz.ll
    M llvm/test/CodeGen/AArch64/dp1.ll
    M llvm/test/CodeGen/AArch64/extract-vector-cmp.ll
    M llvm/test/CodeGen/AArch64/insertextract.ll
    M llvm/test/CodeGen/AArch64/mul.ll
    M llvm/test/CodeGen/AArch64/neon-truncstore.ll
    M llvm/test/CodeGen/AArch64/nontemporal-load.ll
    M llvm/test/CodeGen/AArch64/pr-cf624b2.ll
    M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
    M llvm/test/CodeGen/AArch64/setcc-type-mismatch.ll
    M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
    M llvm/test/CodeGen/AArch64/store.ll
    M llvm/test/CodeGen/AArch64/sub.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-permute-rev.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-gather-scatter.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll
    M llvm/test/CodeGen/AArch64/tbl-loops.ll
    M llvm/test/CodeGen/AArch64/trunc-to-tbl.ll
    M llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
    M llvm/test/CodeGen/AArch64/usub_sat_vec.ll
    M llvm/test/CodeGen/AArch64/vec-combine-compare-truncate-store.ll
    M llvm/test/CodeGen/AArch64/vec3-loads-ext-trunc-stores.ll
    M llvm/test/CodeGen/AArch64/vec_uaddo.ll
    M llvm/test/CodeGen/AArch64/vec_umulo.ll
    M llvm/test/CodeGen/AArch64/vector-compress.ll
    M llvm/test/CodeGen/AArch64/zext-to-tbl.ll

  Log Message:
  -----------
  [AArch64] Generalize integer FPR lane stores for all types (#134117)

This rewrites the fold from #129756 to apply to all types, including
stores of i8s. This required adding a new `aarch64mfp8` MVT to represent
FPR8 types on AArch64, which can be used to extract and store 8-bit
values using b sub-registers.

Follow on from: #129756
Closes: #131793



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