[all-commits] [llvm/llvm-project] c409da: [mlir][ROCDL] Add permlanex16 op to allow subgroup...

[Muzammil via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c409da2223ad910d2a0fb491c19623c679e8aae3
      https://github.com/llvm/llvm-project/commit/c409da2223ad910d2a0fb491c19623c679e8aae3
  Author: Muzammil <55665739+Muzammiluddin-Syed-ECE at users.noreply.github.com>
  Date:   2025-04-16 (Wed, 16 Apr 2025)

  Changed paths:
    M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
    M mlir/test/Dialect/LLVMIR/rocdl.mlir
    M mlir/test/Target/LLVMIR/rocdl.mlir

  Log Message:
  -----------
  [mlir][ROCDL] Add permlanex16 op to allow subgroup reductions on gfx10+ (#135983)

Adding Permlanex16Op to ROCDL dialect to enable subgroup reduce lowering
to DPP ops for gfx 10+ devices.
See [this PR](https://github.com/llvm/llvm-project/pull/133204).

---------

Signed-off-by: Muzammiluddin Syed <muzasyed at amd.com>



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