[all-commits] [llvm/llvm-project] 11857b: [RISCV] Add basic ISel patterns for Xqcisls instru...

[Sudharsan Veeravalli via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 11857bef8a5fdfb8ab65971c3da6593c6076ff62
      https://github.com/llvm/llvm-project/commit/11857bef8a5fdfb8ab65971c3da6593c6076ff62
  Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
  Date:   2025-04-16 (Wed, 16 Apr 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    A llvm/test/CodeGen/RISCV/xqcisls.ll

  Log Message:
  -----------
  [RISCV] Add basic ISel patterns for Xqcisls instructions (#135918)

This patch adds basic instruction selection patterns for generating the
scaled load/store instructions that are a part of the Qualcomm uC
Xqcisls vendor extension.



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