[all-commits] [llvm/llvm-project] 40460a: [RISCV] Add basic ISel patterns for Xqcilo instruc...

[Sudharsan Veeravalli via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 40460a5cf76c973a783fb2f5229e1076398df96e
      https://github.com/llvm/llvm-project/commit/40460a5cf76c973a783fb2f5229e1076398df96e
  Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
  Date:   2025-04-16 (Wed, 16 Apr 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    A llvm/test/CodeGen/RISCV/xqcilo.ll

  Log Message:
  -----------
  [RISCV] Add basic ISel patterns for Xqcilo instructions (#135901)

This patch adds basic instruction selection patterns for generating the
48 bit load/store instructions that are a part of the Qualcomm uC Xqcilo
vendor extension.



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