[all-commits] [llvm/llvm-project] 4c97c5: [RISCV] Add ISel patterns for Xqcilia instructions...

[Sudharsan Veeravalli via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4c97c5131f9ca32ce644a0be6e3586077ee03aa6
      https://github.com/llvm/llvm-project/commit/4c97c5131f9ca32ce644a0be6e3586077ee03aa6
  Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
  Date:   2025-04-16 (Wed, 16 Apr 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    A llvm/test/CodeGen/RISCV/xqcilia.ll

  Log Message:
  -----------
  [RISCV] Add ISel patterns for Xqcilia instructions (#135724)

This patch adds instruction selection patterns for generating the long
immediate arithmetic instructions.

We prefer generating instructions that have a 26 bit immediate to a 32
bit immediate given that both are of the same size but the former might
be easier to register allocate for. Base RISC-V arithmetic instructions
will be preferred, when applicable.



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