[all-commits] [llvm/llvm-project] b4017d: [AArch64][GlobalISel] Improve MULL generation (#11...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b4017d814217160fa776ca05afc711770a13ac13
      https://github.com/llvm/llvm-project/commit/b4017d814217160fa776ca05afc711770a13ac13
  Author: David Green <david.green at arm.com>
  Date:   2025-04-15 (Tue, 15 Apr 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64Combine.td
    M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
    M llvm/test/CodeGen/AArch64/aarch64-smull.ll
    M llvm/test/CodeGen/AArch64/neon-dotreduce.ll
    M llvm/test/CodeGen/AArch64/neon-extmul.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] Improve MULL generation (#112405)

This splits the existing post-legalize lowering of vector umull/smull
into two parts - one to perform the optimization of mul(ext,ext) -> mull
and one to perform the v2i64 mul scalarization. The mull part is moved
to post legalizer combine and has been taught a few extra tricks from
SDAG, using known bits to convert mul(sext, zext) or mul(zext,
zero-upper-bits) into umull. This can be important to prevent v2i64
scalarization of muls.



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