[all-commits] [llvm/llvm-project] 5df965: [RISCV] Refactor register list parsing and improve...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5df9658d4009e500be1421231b48b210e8c2cd69
      https://github.com/llvm/llvm-project/commit/5df9658d4009e500be1421231b48b210e8c2cd69
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-04-14 (Mon, 14 Apr 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/test/MC/RISCV/rv32xqccmp-invalid.s
    M llvm/test/MC/RISCV/rv32zcmp-invalid.s
    M llvm/test/MC/RISCV/rv64xqccmp-invalid.s
    M llvm/test/MC/RISCV/rv64zcmp-invalid.s

  Log Message:
  -----------
  [RISCV] Refactor register list parsing and improve error messages. (#134938)

Structure the code into a loop that parses a series of ranges and gives
an error when there are too many ranges.

Give errors when ABI and non-ABI names are mixed.

Properly diagnose 'x1-` starting a list.

Use a default bool argument to merge parseRegListCommon and
parseRegList.



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