[all-commits] [llvm/llvm-project] ff687a: [clang][CodeGen] Add range metadata for atomic loa...
Oliver Hunt via All-commits
all-commits at lists.llvm.org
Mon Apr 14 15:18:31 PDT 2025
Branch: refs/heads/users/ojhunt/bug135668
Home: https://github.com/llvm/llvm-project
Commit: ff687af04f5b0e85305250587b524cb0b3849aa0
https://github.com/llvm/llvm-project/commit/ff687af04f5b0e85305250587b524cb0b3849aa0
Author: Jan Górski <jan.a.gorski at wp.pl>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M clang/lib/CodeGen/CGAtomic.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CodeGenFunction.h
A clang/test/CodeGen/atomic-ops-load.c
Log Message:
-----------
[clang][CodeGen] Add range metadata for atomic load of boolean type. #131476 (#133546)
Fixes #131476.
For `x86_64` it folds
```
movzbl t1(%rip), %eax
andb $1, %al
```
into
```
movzbl t1(%rip), %eax
```
when run: `clang -S atomic-ops-load.c -o atomic-ops-load.s -O1
--target=x86_64`.
But for riscv replaces:
```
lb a0, %lo(t1)(a0)
andi a0, a0, 1
```
with
```
lb a0, %lo(t1)(a0)
zext.b a0, a0
```
when run: `clang -S atomic-ops-load.c -o atomic-ops-load.s -O1
--target=riscv64`.
Commit: 557e931d958104eb5d11b93ad3a21e4017812fcd
https://github.com/llvm/llvm-project/commit/557e931d958104eb5d11b93ad3a21e4017812fcd
Author: Damien L-G <dalg24 at gmail.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M libcxx/docs/FeatureTestMacroTable.rst
M libcxx/docs/ReleaseNotes/21.rst
M libcxx/docs/Status/Cxx2cPapers.csv
M libcxx/include/CMakeLists.txt
A libcxx/include/__mdspan/aligned_accessor.h
M libcxx/include/__mdspan/mdspan.h
A libcxx/include/__memory/is_sufficiently_aligned.h
M libcxx/include/mdspan
M libcxx/include/memory
M libcxx/include/module.modulemap
M libcxx/include/version
M libcxx/modules/std/mdspan.inc
M libcxx/modules/std/memory.inc
A libcxx/test/libcxx/containers/views/mdspan/aligned_accessor/byte_alignment.verify.cpp
A libcxx/test/libcxx/containers/views/mdspan/aligned_accessor/element_type.verify.cpp
A libcxx/test/std/containers/views/mdspan/aligned_accessor/access.pass.cpp
A libcxx/test/std/containers/views/mdspan/aligned_accessor/ctor.conversion.from.default_accessor.pass.cpp
A libcxx/test/std/containers/views/mdspan/aligned_accessor/ctor.conversion.pass.cpp
A libcxx/test/std/containers/views/mdspan/aligned_accessor/ctor.default.pass.cpp
A libcxx/test/std/containers/views/mdspan/aligned_accessor/offset.pass.cpp
A libcxx/test/std/containers/views/mdspan/aligned_accessor/operator.conversion.to.default_accessor.pass.cpp
A libcxx/test/std/containers/views/mdspan/aligned_accessor/types.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/mdspan.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/memory.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
A libcxx/test/std/utilities/memory/ptr.align/is_sufficiently_aligned.pass.cpp
M libcxx/utils/generate_feature_test_macro_components.py
Log Message:
-----------
[libc++] Implement P2897R7 aligned_accessor: An mdspan accessor expressing pointer over-alignment (#122603)
Closes #118372
Commit: cd7d2c3bf89c9f0e6b7467d9d5ac87ddc829975c
https://github.com/llvm/llvm-project/commit/cd7d2c3bf89c9f0e6b7467d9d5ac87ddc829975c
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRTypes.h
M clang/include/clang/CIR/Dialect/IR/CIRTypes.td
A clang/include/clang/CIR/Dialect/IR/CIRTypesDetails.h
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenDecl.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.h
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
A clang/test/CIR/CodeGen/struct.c
A clang/test/CIR/CodeGen/struct.cpp
A clang/test/CIR/CodeGen/union.c
A clang/test/CIR/IR/struct.cir
Log Message:
-----------
[CIR] Upstream minimal support for structure types (#135105)
This change adds minimal support for structure types. To keep the
initial change small, only incomplete declarations are being supported
in this patch. More complete support will follow.
Commit: 1bcec036e197f6ab7461722502e4393396b46ec3
https://github.com/llvm/llvm-project/commit/1bcec036e197f6ab7461722502e4393396b46ec3
Author: Alex Voicu <alexandru.voicu at amd.com>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
A clang/test/CodeGenHipStdPar/rdc-does-not-enable-hipstdpar.cpp
A clang/test/CodeGenHipStdPar/select-accelerator-code-pass-ordering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
Log Message:
-----------
[HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (#134753)
The `hipstdpar` specific passes were not ordered ideally, especially for
`fgpu-rdc` compilations, which meant that we'd eagerly run accelerator
code selection and remove symbols that might end up used. This change
corrects that aspect by ensuring that accelerator code selection is only
done after linking (this will have to be revisited in the future once
the closed-world assumption no longer holds). Furthermore, we take the
opportunity to move allocation interposition so that it properly gets
printed when print-pipeline-passes is requested. NFC.
Commit: 68806b9c2cf732dc93b17e47e5321394e0fcf8bb
https://github.com/llvm/llvm-project/commit/68806b9c2cf732dc93b17e47e5321394e0fcf8bb
Author: Andrei Safronov <andrei.safronov at espressif.com>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
M llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaFixupKinds.h
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
M llvm/lib/Target/Xtensa/XtensaFeatures.td
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaOperands.td
M llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
M llvm/lib/Target/Xtensa/XtensaSubtarget.h
A llvm/test/CodeGen/Xtensa/minmax.ll
A llvm/test/CodeGen/Xtensa/sext.ll
M llvm/test/MC/Xtensa/Relocations/fixups-diagnostics.s
M llvm/test/MC/Xtensa/Relocations/fixups.s
M llvm/test/MC/Xtensa/Relocations/relocations.s
A llvm/test/MC/Xtensa/loop.s
A llvm/test/MC/Xtensa/minmax.s
A llvm/test/MC/Xtensa/nsau.s
A llvm/test/MC/Xtensa/sext.s
A llvm/test/MC/Xtensa/sext_invalid.s
Log Message:
-----------
[Xtensa] Implement SEXT, NSA, MINMAX and Loop Xtensa Options. (#133818)
Implement basic support of the several simple Xtensa Options with 1-4
instructions for each option. The Sign Extend Option (SEXT). The NSA
Option. The Minimum/Maximum Integer 32-bit Option and Loop Option.
Fixed address operands, added OPERAND_PCREL to operands descriptions.
Commit: eb3ecd158a8aef854f23553f63d118a0c5ef69af
https://github.com/llvm/llvm-project/commit/eb3ecd158a8aef854f23553f63d118a0c5ef69af
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 557e931d9581
Commit: 888b3ed5b4f441b0dea91d7ec2bda1426abeadec
https://github.com/llvm/llvm-project/commit/888b3ed5b4f441b0dea91d7ec2bda1426abeadec
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[Vectorize] Fix a warning
This patch fixes:
llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp:2417:13: error:
unused variable 'ConstStep' [-Werror,-Wunused-variable]
Commit: 2206e15e78bc3d5289fb2c2cf5a80d6f08412a58
https://github.com/llvm/llvm-project/commit/2206e15e78bc3d5289fb2c2cf5a80d6f08412a58
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefCallArgsChecker.cpp
M clang/test/Analysis/Checkers/WebKit/call-args-checked.cpp
M clang/test/Analysis/Checkers/WebKit/mock-types.h
M clang/test/Analysis/Checkers/WebKit/objc-mock-types.h
M clang/test/Analysis/Checkers/WebKit/unretained-call-args.mm
Log Message:
-----------
[alpha.webkit.UnretainedCallArgsChecker] Don't emit a warning for RetainPtr::operator= (#135526)
Generalize the check for operator= so that it works for RetainPtr and
CheckedPtr instead of just RefPtr.
Commit: 292ffa067cca50529ef0d9d7c2ea6934425538c1
https://github.com/llvm/llvm-project/commit/292ffa067cca50529ef0d9d7c2ea6934425538c1
Author: Oliver Hunt <oliver at apple.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRTypes.h
M clang/include/clang/CIR/Dialect/IR/CIRTypes.td
A clang/include/clang/CIR/Dialect/IR/CIRTypesDetails.h
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenDecl.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.h
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/CodeGen/CGAtomic.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefCallArgsChecker.cpp
M clang/test/Analysis/Checkers/WebKit/call-args-checked.cpp
M clang/test/Analysis/Checkers/WebKit/mock-types.h
M clang/test/Analysis/Checkers/WebKit/objc-mock-types.h
M clang/test/Analysis/Checkers/WebKit/unretained-call-args.mm
A clang/test/CIR/CodeGen/struct.c
A clang/test/CIR/CodeGen/struct.cpp
A clang/test/CIR/CodeGen/union.c
A clang/test/CIR/IR/struct.cir
A clang/test/CodeGen/atomic-ops-load.c
A clang/test/CodeGenHipStdPar/rdc-does-not-enable-hipstdpar.cpp
A clang/test/CodeGenHipStdPar/select-accelerator-code-pass-ordering.cpp
M libcxx/docs/FeatureTestMacroTable.rst
M libcxx/docs/ReleaseNotes/21.rst
M libcxx/docs/Status/Cxx2cPapers.csv
M libcxx/include/CMakeLists.txt
A libcxx/include/__mdspan/aligned_accessor.h
M libcxx/include/__mdspan/mdspan.h
A libcxx/include/__memory/is_sufficiently_aligned.h
M libcxx/include/mdspan
M libcxx/include/memory
M libcxx/include/module.modulemap
M libcxx/include/version
M libcxx/modules/std/mdspan.inc
M libcxx/modules/std/memory.inc
A libcxx/test/libcxx/containers/views/mdspan/aligned_accessor/byte_alignment.verify.cpp
A libcxx/test/libcxx/containers/views/mdspan/aligned_accessor/element_type.verify.cpp
A libcxx/test/std/containers/views/mdspan/aligned_accessor/access.pass.cpp
A libcxx/test/std/containers/views/mdspan/aligned_accessor/ctor.conversion.from.default_accessor.pass.cpp
A libcxx/test/std/containers/views/mdspan/aligned_accessor/ctor.conversion.pass.cpp
A libcxx/test/std/containers/views/mdspan/aligned_accessor/ctor.default.pass.cpp
A libcxx/test/std/containers/views/mdspan/aligned_accessor/offset.pass.cpp
A libcxx/test/std/containers/views/mdspan/aligned_accessor/operator.conversion.to.default_accessor.pass.cpp
A libcxx/test/std/containers/views/mdspan/aligned_accessor/types.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/mdspan.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/memory.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
A libcxx/test/std/utilities/memory/ptr.align/is_sufficiently_aligned.pass.cpp
M libcxx/utils/generate_feature_test_macro_components.py
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
M llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaFixupKinds.h
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
M llvm/lib/Target/Xtensa/XtensaFeatures.td
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaOperands.td
M llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
M llvm/lib/Target/Xtensa/XtensaSubtarget.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
A llvm/test/CodeGen/Xtensa/minmax.ll
A llvm/test/CodeGen/Xtensa/sext.ll
M llvm/test/MC/Xtensa/Relocations/fixups-diagnostics.s
M llvm/test/MC/Xtensa/Relocations/fixups.s
M llvm/test/MC/Xtensa/Relocations/relocations.s
A llvm/test/MC/Xtensa/loop.s
A llvm/test/MC/Xtensa/minmax.s
A llvm/test/MC/Xtensa/nsau.s
A llvm/test/MC/Xtensa/sext.s
A llvm/test/MC/Xtensa/sext_invalid.s
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
Merge branch 'main' into users/ojhunt/bug135668
Compare: https://github.com/llvm/llvm-project/compare/62be33b3aa47...292ffa067cca
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