[all-commits] [llvm/llvm-project] 74e8f2: [RegAlloc] Sort CopyHint by IsCSR (#131046)

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 74e8f29f3138431abc9b393579733f3bbd0d85d8
      https://github.com/llvm/llvm-project/commit/74e8f29f3138431abc9b393579733f3bbd0d85d8
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2025-04-14 (Mon, 14 Apr 2025)

  Changed paths:
    M llvm/lib/CodeGen/CalcSpillWeights.cpp
    M llvm/test/CodeGen/AArch64/aarch64-signedreturnaddress.ll
    A llvm/test/CodeGen/AArch64/csr-copy-hint.mir
    M llvm/test/CodeGen/AArch64/ptrauth-ret.ll
    M llvm/test/CodeGen/AVR/calling-conv/c/basic_aggr.ll
    M llvm/test/CodeGen/AVR/calling-conv/c/stack.ll
    M llvm/test/CodeGen/AVR/dynalloca.ll
    M llvm/test/CodeGen/AVR/return.ll
    M llvm/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
    M llvm/test/CodeGen/SPARC/32abi.ll
    M llvm/test/CodeGen/SPARC/64abi.ll
    M llvm/test/CodeGen/SPARC/bigreturn.ll
    M llvm/test/CodeGen/SPARC/fmuladd-soft-float.ll
    M llvm/test/CodeGen/SPARC/leafproc.ll
    M llvm/test/CodeGen/SPARC/parts.ll
    M llvm/test/CodeGen/SPARC/tailcall.ll
    M llvm/test/CodeGen/SPARC/umulo-128-legalisation-lowering.ll
    M llvm/test/CodeGen/X86/base-pointer-and-mwaitx.ll
    M llvm/test/CodeGen/X86/ghc-cc64.ll
    M llvm/test/CodeGen/X86/mwaitx.ll

  Log Message:
  -----------
  [RegAlloc] Sort CopyHint by IsCSR (#131046)

`weightCalcHelper` is responsible for adding hints to MRI. Prior to this
PR, we fell back on register ID as the last tie breaker for sorting
hints. However, there is an opportunity to add an additional sorting
characteristic: whether or not a register is a callee-saved-register.

I thought of this idea because I saw that `AllocationOrder::create`
calls `RegisterClassInfo::getOrder`, which returns a list of registers
such that the registers which alias callee-saved-registers come last.
>From this, I conclude that the register allocator prefers an order such
that callee-saved-registers are allocated after
non-callee-saved-registers to avoid having to spill the CSR.

This sorting characteristic occurs only as a tie breaker to the Weight
calculation. This is a good idea since the weight calculation is pretty
complex and I'm sure it is a pretty stable metric. I think its pretty
reasonable to agree that whether a register is callee-saved or not is a
better tie breaker than register ID. I think this is evident by the test
diff, since the changes all seem to have no impact or improve the
register allocation.



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