[all-commits] [llvm/llvm-project] 63e296: Support '-fmodule-file-home-is-cwd' for C++ module...
Pengcheng Wang via All-commits
all-commits at lists.llvm.org
Mon Apr 14 04:31:56 PDT 2025
Branch: refs/heads/users/wangpc-pp/spr/riscvnfc-use-bitmasks-generated-by-tablegen
Home: https://github.com/llvm/llvm-project
Commit: 63e2963f4a24cb9365d1224e69f64bf643171023
https://github.com/llvm/llvm-project/commit/63e2963f4a24cb9365d1224e69f64bf643171023
Author: Michael Park <mcypark at gmail.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M clang/lib/Serialization/ASTWriter.cpp
A clang/test/Modules/relocatable-modules.cpp
Log Message:
-----------
Support '-fmodule-file-home-is-cwd' for C++ modules. (#135147)
Commit: a3f8359410eb7e14c4a52b47f36e433af40c05e9
https://github.com/llvm/llvm-project/commit/a3f8359410eb7e14c4a52b47f36e433af40c05e9
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M lldb/test/Shell/SymbolFile/NativePDB/inline_sites_live.cpp
Log Message:
-----------
[lldb][test] Fix NativePDB/inline_sites_live.cpp inlined frame format
Adjust after https://github.com/llvm/llvm-project/pull/135343
Commit: 58b5df09dc6f899016fc707bf937b36b36934b6d
https://github.com/llvm/llvm-project/commit/58b5df09dc6f899016fc707bf937b36b36934b6d
Author: YunQiang Su <syq at debian.org>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Builtins.td
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Sema/SemaChecking.cpp
A clang/test/CodeGen/builtin-maxnum-minnum.c
Log Message:
-----------
Clang: Add elementwise minnum/maxnum builtin functions (#129207)
With https://github.com/llvm/llvm-project/pull/112852, we claimed that
llvm.minnum and llvm.maxnum should treat +0.0>-0.0, while libc doesn't
require fmin(3)/fmax(3) for it.
To make llvm.minnum/llvm.maxnum easy to use, we define the builtin
functions for them, include
__builtin_elementwise_minnum
__builtin_elementwise_maxnum
All of them support _Float16, __bf16, float, double, long double.
Commit: 9df153bc146eab7e6c48d5083acb87a6d5c42394
https://github.com/llvm/llvm-project/commit/9df153bc146eab7e6c48d5083acb87a6d5c42394
Author: Mel Chen <mel.chen at sifive.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LV] Remove unused requiresScalarEpilogue function. nfc (#135341)
Commit: ffd5b148941a1146378a247c70c4faface3a1f96
https://github.com/llvm/llvm-project/commit/ffd5b148941a1146378a247c70c4faface3a1f96
Author: Mel Chen <mel.chen at sifive.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse-output.ll
Log Message:
-----------
[LV] Add test cases for reverse accesses involving irregular types. nfc (#135139)
Add a test with irregular type to ensure the vector load/store
instructions are not generated.
Commit: e710a5a9f274162c63e32aa8d88f6a734759b4a5
https://github.com/llvm/llvm-project/commit/e710a5a9f274162c63e32aa8d88f6a734759b4a5
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M llvm/include/llvm/ADT/APFloat.h
M llvm/lib/Support/APFloat.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/test/Transforms/InstCombine/fabs-as-int.ll
M llvm/test/Transforms/InstCombine/fneg-as-int.ll
M llvm/test/Transforms/InstCombine/fneg-fabs-as-int.ll
M llvm/unittests/ADT/APFloatTest.cpp
Log Message:
-----------
[InstCombine] Fold fneg/fabs patterns with ppc_f128 (#130557)
This patch is needed by
https://github.com/llvm/llvm-project/pull/130496.
Commit: 1380a8259e5937d7e871c7a754bbf8a662aaa4da
https://github.com/llvm/llvm-project/commit/1380a8259e5937d7e871c7a754bbf8a662aaa4da
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
Log Message:
-----------
[AMDGPU] Use llvm::find and llvm::find_if (NFC) (#135582)
Commit: 893cd69872ca8e7be8010699aac32c5678a0e2a6
https://github.com/llvm/llvm-project/commit/893cd69872ca8e7be8010699aac32c5678a0e2a6
Author: Shao-Ce SUN <sunshaoce at outlook.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
A llvm/test/CodeGen/RISCV/emit-x8-as-fp.ll
A llvm/test/MC/Disassembler/RISCV/emit-x8-as-fp.txt
A llvm/test/MC/RISCV/emit-x8-as-fp.s
Log Message:
-----------
[RISCV][MC] Emit `x8` as `fp` instead of `s0` (#135500)
When emphasizing `X8`'s functionality related to Frame Pointer, this option can be passed.
Commit: 150e7b14f9474bc4d6891faaae4de6b8c5f6c797
https://github.com/llvm/llvm-project/commit/150e7b14f9474bc4d6891faaae4de6b8c5f6c797
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
A llvm/test/CodeGen/X86/pr134602.ll
Log Message:
-----------
[X86] Add test coverage for #134602
Commit: cf188d650ce26b4ee3e11101d844361fca15ba64
https://github.com/llvm/llvm-project/commit/cf188d650ce26b4ee3e11101d844361fca15ba64
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
A llvm/test/CodeGen/AMDGPU/promote-alloca-non-byte-sizes.ll
Log Message:
-----------
[AMDGPU] Avoid crashes for non-byte-sized types in PromoteAlloca (#134042)
This patch addresses three problems when promoting allocas to vectors:
- Element types with size < 1 byte in allocas with a vector type caused
divisions by zero.
- Element types whose size doesn't match their AllocSize hit an assertion.
- Access types whose size doesn't match their AllocSize hit an assertion.
With this patch, we do not attempt to promote affected allocas to vectors. In
principle, we could handle these cases in PromoteAlloca, e.g., by truncating
and extending elements from/to their allocation size. It's however unclear if
we ever encounter such cases in practice, so that doesn't seem worth the added
complexity.
For SWDEV-511252
Commit: 53cd5cfc675dad1bf6bc820a72e0eaa72a8909e7
https://github.com/llvm/llvm-project/commit/53cd5cfc675dad1bf6bc820a72e0eaa72a8909e7
Author: Jack Styles <jack.styles at arm.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Driver/ToolChains/Arch/ARM.cpp
A clang/test/Driver/arm-fpu-selection.s
A clang/test/Driver/armv7-default-neon.s
A clang/test/Driver/armv7s-default-vfpv4.s
M clang/test/Driver/armv8.1m.main.s
Log Message:
-----------
[Clang][ARM] Ensure FPU Features are parsed when targeting `cc1as` (#134612)
Previously, `cc1as` did not consider the Features that can be included
from a target's FPU. This could lead to a situation where assembly files
could not compile as cc1as did not know if a feature was supported.
With this change, all the features for the FPU will be passed to `cc1as`
as `-target-feature` lines. By making this change, it will enable
`+nosimd` to be functional, worked on in #130623, and fix a regression
introduced in 8fa0f0efce5fb81eb422e6d7eec74c66dafef4a3 so
armv7s-apple-darwin targets can utilise VFPv4 correctly.
---------
Co-authored-by: Martin Storsjö <martin at martin.st>
Commit: 1df4af6cbcc3bda86fa76b9aba01424ab39077a4
https://github.com/llvm/llvm-project/commit/1df4af6cbcc3bda86fa76b9aba01424ab39077a4
Author: Ricardo Jesus <rjj at nvidia.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
A llvm/test/CodeGen/AArch64/aarch64-sve-fill-spill-pair.ll
A llvm/test/CodeGen/AArch64/sve-vls-ldst-opt.mir
Log Message:
-----------
Reapply "[AArch64][SVE] Pair SVE fill/spill into LDP/STP with -msve-vector-bits=128." (#135177)
Reapplies #134068.
The first patch was missing a check to prevent attempts to pair SVE
fill/spill with other Neon load/store instructions, which could happen
specifically if the Neon instruction was unscaled.
Commit: ed96e4642c76fa199cc427129e6d03fba301a301
https://github.com/llvm/llvm-project/commit/ed96e4642c76fa199cc427129e6d03fba301a301
Author: Matthias Braun <matze at braunis.de>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
M llvm/test/CodeGen/AArch64/peephole-orr.mir
Log Message:
-----------
AArch64: Allow ZEXT+COPY -> FMOV peephole for ZPR registers as well (#135436)
Commit: e29f986838bcd0ff60cf33e7ae5ee867bad0de00
https://github.com/llvm/llvm-project/commit/e29f986838bcd0ff60cf33e7ae5ee867bad0de00
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
A llvm/include/llvm/CodeGen/RemoveLoadsIntoFakeUses.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/RemoveLoadsIntoFakeUses.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/test/CodeGen/X86/fake-use-remove-loads.mir
Log Message:
-----------
[CodeGen][NPM] Port RemoveLoadsIntoFakeUses to NPM (#130068)
Commit: 51fe5d2c314619796c29af6bd717c5c212faa811
https://github.com/llvm/llvm-project/commit/51fe5d2c314619796c29af6bd717c5c212faa811
Author: Björn Pettersson <bjorn.a.pettersson at ericsson.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M llvm/test/Transforms/InstCombine/array.ll
Log Message:
-----------
[InstCombine] Pre-commit tests related to ADDLIKE+GEP->GEP+GEP. NFC (#135154)
InstCombine can transform ADD+GEP into GEP+GEP. But those rewrites does
not currently trigger when the ADD is a disjoint OR (which happens to be
the canonical form for certain ADD operations). Add lit tests to show
that we are lacking such rewrites.
Also add a test case showing that we do not preserve "inbounds nuw",
"nusw nuw" and "nuw" when doing such transforms and the ADD/OR is
known to be NUW.
Commit: 97bc9137e545423334b00d60ab64855ccc434c3a
https://github.com/llvm/llvm-project/commit/97bc9137e545423334b00d60ab64855ccc434c3a
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M .github/workflows/premerge.yaml
Log Message:
-----------
[Github][CI] Upload artifacts directory for premerge workflow
The premerge pipeline currently creates an artifacts directory with some
statistics that gets uploaded on the buildkite side for later
inspection. This patch adds support for this on the Github side by using
the upload artifacts action.
Reviewers: Keenuts, lnihlen, mizvekov, tstellar, Endilll
Reviewed By: mizvekov
Pull Request: https://github.com/llvm/llvm-project/pull/135538
Commit: ebd1667059e7b2865a8e419a21df4d4c9735869c
https://github.com/llvm/llvm-project/commit/ebd1667059e7b2865a8e419a21df4d4c9735869c
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/MachineBlockPlacement.cpp
Log Message:
-----------
[CodeGen] Avoid repeated hash lookups (NFC) (#135584)
Commit: d792094c26dc6b40136f1e6c2e393c041062e371
https://github.com/llvm/llvm-project/commit/d792094c26dc6b40136f1e6c2e393c041062e371
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M lldb/include/lldb/Host/ProcessRunLock.h
M lldb/source/Host/common/ProcessRunLock.cpp
M lldb/source/Host/windows/ProcessRunLock.cpp
M lldb/source/Target/Process.cpp
Log Message:
-----------
[lldb] Remove ProcessRunLock::TrySetRunning (#135455)
I traced the issue reported by Caroline and Pavel in #134757 back to the
call to ProcessRunLock::TrySetRunning. When that fails, we get a
somewhat misleading error message:
> process resume at entry point failed: Resume request failed - process
still running.
This is incorrect: the problem was not that the process was in a running
state, but rather that the RunLock was being held by another thread
(i.e. the Statusline). TrySetRunning would return false in both cases
and the call site only accounted for the former.
Besides the odd semantics, the current implementation is inherently
race-y and I believe incorrect. If someone is holding the RunLock, the
resume call should block, rather than give up, and with the lock held,
switch the running state and report the old running state.
This patch removes ProcessRunLock::TrySetRunning and updates all callers
to use ProcessRunLock::SetRunning instead. To support that,
ProcessRunLock::SetRunning (and ProcessRunLock::SetStopped, for
consistency) now report whether the process was stopped or running
respectively. Previously, both methods returned true unconditionally.
The old code has been around pretty much pretty much forever, there's
nothing in the git history to indicate that this was done purposely to
solve a particular issue. I've tested this on both Linux and macOS and
confirmed that this solves the statusline issue.
A big thank you to Jim for reviewing my proposed solution offline and
trying to poke holes in it.
Commit: 73b554d7a0a666e252f3c837510a55ee1acb1df5
https://github.com/llvm/llvm-project/commit/73b554d7a0a666e252f3c837510a55ee1acb1df5
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M lldb/source/Core/Statusline.cpp
Log Message:
-----------
[lldb] Make sure the process is stopped when computing the symbol context (#135458)
Make sure the process is stopped when computing the symbol context. Both
Adrian and Felipe reported a handful of crashes in GetSymbolContext
called from Statusline::Redraw on the default event thread.
Given that we're handling a StackFrameSP, it's not clear to me how that
could have gotten invalidated, but Jim points out that it doesn't make
sense to compute the symbol context for the frame when the process isn't
stopped.
Depends on #135455
Commit: 931a78a1db3da210a1ed5681778e37fa011cdf23
https://github.com/llvm/llvm-project/commit/931a78a1db3da210a1ed5681778e37fa011cdf23
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCombine.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-sext.mir
Log Message:
-----------
[AMDGPU] Add sext_trunc in RegBankCombiner (#131623)
Commit: 95d526f7f587cc7a3db785169967f8dad0ba3978
https://github.com/llvm/llvm-project/commit/95d526f7f587cc7a3db785169967f8dad0ba3978
Author: Thomas Preud'homme <thomas.preudhomme at arm.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
Log Message:
-----------
[MLIR][Tosa] Fix argmax NaN propagate lowering (#133074)
In the propagate mode, NaN compare equal to each other so in case of
several NaNs the index of the first one needs to be returned. This
commit changes the index update condition to check that the current
index is not that of a NaN.
The commit also simplifies argmax NaN ignore lowering to only use OGT.
This prevent any update in case of NaN. The only case where the index of
a NaN is returned is when all values are NaN and this is covered by the
fact that the initial index value is 0 so no update will result in 0
being returned.
Commit: bcd7f54d340c54630a63659e439540891f7efb09
https://github.com/llvm/llvm-project/commit/bcd7f54d340c54630a63659e439540891f7efb09
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M .mailmap
Log Message:
-----------
[mailmap] Update my name
Commit: 29555ad5efea20308c7a5ee851a4cba9093a607d
https://github.com/llvm/llvm-project/commit/29555ad5efea20308c7a5ee851a4cba9093a607d
Author: Björn Pettersson <bjorn.a.pettersson at ericsson.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/test/Transforms/InstCombine/array.ll
Log Message:
-----------
[InstCombine] Improve inbounds preservation for ADD+GEP -> GEP+GEP (#135155)
Given that we have a "add nuw" and a "getelementptr inbounds nuw" like
this:
%idx = add nuw i64 %idx1, %idx2
%gep = getelementptr inbounds nuw i32, ptr %ptr, i64 %idx
Then we can preserve the "inbounds nuw" flag when transforming that into
two getelementptr instructions:
%gep1 = getelementptr inbounds nuw i32, ptr %ptr, i64 %idx1
%gep = getelementptr inbounds nuw i32, ptr %ptr, i64 %idx2
Similarly for just having "nuw", and "nusw nuw" instead of "inbounds nuw"
on the getelementptr.
Proof: https://alive2.llvm.org/ce/z/QSweWW
Commit: dffef041d568e945efbd78c8eb1a3881b67cd405
https://github.com/llvm/llvm-project/commit/dffef041d568e945efbd78c8eb1a3881b67cd405
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M llvm/include/llvm/ADT/APFloat.h
M llvm/include/llvm/IR/Type.h
M llvm/include/llvm/SandboxIR/Type.h
M llvm/lib/IR/Type.cpp
M llvm/unittests/SandboxIR/TypesTest.cpp
Log Message:
-----------
[IR][ADT] Remove `APFloat/Type::isIEEE` (#130496)
Address comment
https://github.com/llvm/llvm-project/pull/130477#issuecomment-2708801892.
Commit: cbda72a5474112e6bc62d5c5978ada7581e80dad
https://github.com/llvm/llvm-project/commit/cbda72a5474112e6bc62d5c5978ada7581e80dad
Author: Wenju He <wenju.he at intel.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
R libclc/generic/include/clc/atom_decl_int32.inc
R libclc/generic/include/clc/atom_decl_int64.inc
A libclc/generic/include/clc/atomic/atom_add.h
A libclc/generic/include/clc/atomic/atom_and.h
A libclc/generic/include/clc/atomic/atom_cmpxchg.h
A libclc/generic/include/clc/atomic/atom_dec.h
A libclc/generic/include/clc/atomic/atom_decl_int32.inc
A libclc/generic/include/clc/atomic/atom_decl_int64.inc
A libclc/generic/include/clc/atomic/atom_inc.h
A libclc/generic/include/clc/atomic/atom_max.h
A libclc/generic/include/clc/atomic/atom_min.h
A libclc/generic/include/clc/atomic/atom_or.h
A libclc/generic/include/clc/atomic/atom_sub.h
A libclc/generic/include/clc/atomic/atom_xchg.h
A libclc/generic/include/clc/atomic/atom_xor.h
R libclc/generic/include/clc/cl_khr_global_int32_base_atomics/atom_add.h
R libclc/generic/include/clc/cl_khr_global_int32_base_atomics/atom_cmpxchg.h
R libclc/generic/include/clc/cl_khr_global_int32_base_atomics/atom_dec.h
R libclc/generic/include/clc/cl_khr_global_int32_base_atomics/atom_inc.h
R libclc/generic/include/clc/cl_khr_global_int32_base_atomics/atom_sub.h
R libclc/generic/include/clc/cl_khr_global_int32_base_atomics/atom_xchg.h
R libclc/generic/include/clc/cl_khr_global_int32_extended_atomics/atom_and.h
R libclc/generic/include/clc/cl_khr_global_int32_extended_atomics/atom_max.h
R libclc/generic/include/clc/cl_khr_global_int32_extended_atomics/atom_min.h
R libclc/generic/include/clc/cl_khr_global_int32_extended_atomics/atom_or.h
R libclc/generic/include/clc/cl_khr_global_int32_extended_atomics/atom_xor.h
R libclc/generic/include/clc/cl_khr_int64_base_atomics/atom_add.h
R libclc/generic/include/clc/cl_khr_int64_base_atomics/atom_cmpxchg.h
R libclc/generic/include/clc/cl_khr_int64_base_atomics/atom_dec.h
R libclc/generic/include/clc/cl_khr_int64_base_atomics/atom_inc.h
R libclc/generic/include/clc/cl_khr_int64_base_atomics/atom_sub.h
R libclc/generic/include/clc/cl_khr_int64_base_atomics/atom_xchg.h
R libclc/generic/include/clc/cl_khr_int64_extended_atomics/atom_and.h
R libclc/generic/include/clc/cl_khr_int64_extended_atomics/atom_max.h
R libclc/generic/include/clc/cl_khr_int64_extended_atomics/atom_min.h
R libclc/generic/include/clc/cl_khr_int64_extended_atomics/atom_or.h
R libclc/generic/include/clc/cl_khr_int64_extended_atomics/atom_xor.h
R libclc/generic/include/clc/cl_khr_local_int32_base_atomics/atom_add.h
R libclc/generic/include/clc/cl_khr_local_int32_base_atomics/atom_cmpxchg.h
R libclc/generic/include/clc/cl_khr_local_int32_base_atomics/atom_dec.h
R libclc/generic/include/clc/cl_khr_local_int32_base_atomics/atom_inc.h
R libclc/generic/include/clc/cl_khr_local_int32_base_atomics/atom_sub.h
R libclc/generic/include/clc/cl_khr_local_int32_base_atomics/atom_xchg.h
R libclc/generic/include/clc/cl_khr_local_int32_extended_atomics/atom_and.h
R libclc/generic/include/clc/cl_khr_local_int32_extended_atomics/atom_max.h
R libclc/generic/include/clc/cl_khr_local_int32_extended_atomics/atom_min.h
R libclc/generic/include/clc/cl_khr_local_int32_extended_atomics/atom_or.h
R libclc/generic/include/clc/cl_khr_local_int32_extended_atomics/atom_xor.h
M libclc/generic/include/clc/clc.h
M libclc/generic/lib/SOURCES
R libclc/generic/lib/atom_int32_binary.inc
A libclc/generic/lib/atomic/atom_add.cl
A libclc/generic/lib/atomic/atom_and.cl
A libclc/generic/lib/atomic/atom_cmpxchg.cl
A libclc/generic/lib/atomic/atom_dec.cl
A libclc/generic/lib/atomic/atom_inc.cl
A libclc/generic/lib/atomic/atom_int32_binary.inc
A libclc/generic/lib/atomic/atom_max.cl
A libclc/generic/lib/atomic/atom_min.cl
A libclc/generic/lib/atomic/atom_or.cl
A libclc/generic/lib/atomic/atom_sub.cl
A libclc/generic/lib/atomic/atom_xchg.cl
A libclc/generic/lib/atomic/atom_xor.cl
R libclc/generic/lib/cl_khr_global_int32_base_atomics/atom_add.cl
R libclc/generic/lib/cl_khr_global_int32_base_atomics/atom_cmpxchg.cl
R libclc/generic/lib/cl_khr_global_int32_base_atomics/atom_dec.cl
R libclc/generic/lib/cl_khr_global_int32_base_atomics/atom_inc.cl
R libclc/generic/lib/cl_khr_global_int32_base_atomics/atom_sub.cl
R libclc/generic/lib/cl_khr_global_int32_base_atomics/atom_xchg.cl
R libclc/generic/lib/cl_khr_global_int32_extended_atomics/atom_and.cl
R libclc/generic/lib/cl_khr_global_int32_extended_atomics/atom_max.cl
R libclc/generic/lib/cl_khr_global_int32_extended_atomics/atom_min.cl
R libclc/generic/lib/cl_khr_global_int32_extended_atomics/atom_or.cl
R libclc/generic/lib/cl_khr_global_int32_extended_atomics/atom_xor.cl
R libclc/generic/lib/cl_khr_int64_base_atomics/atom_add.cl
R libclc/generic/lib/cl_khr_int64_base_atomics/atom_cmpxchg.cl
R libclc/generic/lib/cl_khr_int64_base_atomics/atom_dec.cl
R libclc/generic/lib/cl_khr_int64_base_atomics/atom_inc.cl
R libclc/generic/lib/cl_khr_int64_base_atomics/atom_sub.cl
R libclc/generic/lib/cl_khr_int64_base_atomics/atom_xchg.cl
R libclc/generic/lib/cl_khr_int64_extended_atomics/atom_and.cl
R libclc/generic/lib/cl_khr_int64_extended_atomics/atom_max.cl
R libclc/generic/lib/cl_khr_int64_extended_atomics/atom_min.cl
R libclc/generic/lib/cl_khr_int64_extended_atomics/atom_or.cl
R libclc/generic/lib/cl_khr_int64_extended_atomics/atom_xor.cl
R libclc/generic/lib/cl_khr_local_int32_base_atomics/atom_add.cl
R libclc/generic/lib/cl_khr_local_int32_base_atomics/atom_cmpxchg.cl
R libclc/generic/lib/cl_khr_local_int32_base_atomics/atom_dec.cl
R libclc/generic/lib/cl_khr_local_int32_base_atomics/atom_inc.cl
R libclc/generic/lib/cl_khr_local_int32_base_atomics/atom_sub.cl
R libclc/generic/lib/cl_khr_local_int32_base_atomics/atom_xchg.cl
R libclc/generic/lib/cl_khr_local_int32_extended_atomics/atom_and.cl
R libclc/generic/lib/cl_khr_local_int32_extended_atomics/atom_max.cl
R libclc/generic/lib/cl_khr_local_int32_extended_atomics/atom_min.cl
R libclc/generic/lib/cl_khr_local_int32_extended_atomics/atom_or.cl
R libclc/generic/lib/cl_khr_local_int32_extended_atomics/atom_xor.cl
Log Message:
-----------
[NFC][libclc] Merge atomic extension built-ins with identical name into a single file (#134489)
llvm-diff shows there is no change to amdgcn--amdhsa.bc.
Similar to how cl_khr_fp64 and cl_khr_fp16 implementations are put in a
same file for math built-ins, this PR do the same to atom_* built-ins.
The main motivation is to prevent that two files with same base name
implementats different built-ins. In a follow-up PR, I'd like to relax
libclc_configure_lib_source to only compare filename instead of path for
overriding, since in our downstream the same category of built-ins, e.g.
math, are organized in several different folders.
Commit: 77341388a77b1442b3a54d745fc269dabb175f0c
https://github.com/llvm/llvm-project/commit/77341388a77b1442b3a54d745fc269dabb175f0c
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
Log Message:
-----------
[mlir][OpenMP] allow cancellation to not be directly nested (#134084)
omp.cancel and omp.cancellationpoint contain an attribute describing the
type of parent construct which should be cancelled. e.g.
```
!$omp cancel do
```
Must be inside of a wsloop. Previously the verifer required the
immediate parent to be this operation. This is not quite right because
something like the following is valid:
```
!$omp parallel do
do i = 1, N
if (cond) then
!$omp cancel do
endif
enddo
```
This patch relaxes the verifier to only require that some parent
operation matches (not necessarily the immediate parent).
Commit: c9eebc7af440dc012c94d25351eaba92e6a57910
https://github.com/llvm/llvm-project/commit/c9eebc7af440dc012c94d25351eaba92e6a57910
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp
A llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-sext-inreg.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-trunc-sextinreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
Log Message:
-----------
[GlobalISel] Combine redundant sext_inreg (#131624)
Commit: a9474191e059edbb9b25c769afbe52c7a823f359
https://github.com/llvm/llvm-project/commit/a9474191e059edbb9b25c769afbe52c7a823f359
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/test/Transforms/SROA/non-capturing-call-readonly.ll
M llvm/test/Transforms/SROA/readonlynocapture.ll
Log Message:
-----------
[SROA] Improve handling of lifetimes in load-only promotion (#135382)
The propagateStoredValuesToLoads() transform currently bails out if
there is a lifetime intrinsic spanning the whole alloca, but the
individual loads/stores operate on some smaller part, because the slice
/ partition size does not match.
Fix this by ignoring assume-like slices early, regardless of which range
they cover.
I've changed the overall code structure here a bit because I was getting
confused by the different iterators.
Commit: 1e2dc5b0873d990473bba4a52d5085a805f56845
https://github.com/llvm/llvm-project/commit/1e2dc5b0873d990473bba4a52d5085a805f56845
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M llvm/test/Transforms/SROA/readonlynocapture.ll
Log Message:
-----------
[SROA] Add load-only promotion tests with dynamic offset load
Commit: e4a672bc17a2a7dc39e51c9f5e656d705312a12b
https://github.com/llvm/llvm-project/commit/e4a672bc17a2a7dc39e51c9f5e656d705312a12b
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M lldb/include/lldb/Core/Mangled.h
M lldb/include/lldb/Core/RichManglingContext.h
M lldb/include/lldb/Target/Language.h
M lldb/source/Core/CMakeLists.txt
M lldb/source/Core/Mangled.cpp
M lldb/source/Core/Module.cpp
M lldb/source/Core/RichManglingContext.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionDeclMap.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.h
M lldb/source/Plugins/Language/ObjC/ObjCLanguage.cpp
M lldb/source/Plugins/Language/ObjC/ObjCLanguage.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.h
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/PDB/SymbolFilePDB.cpp
M lldb/unittests/Core/CMakeLists.txt
M lldb/unittests/Core/RichManglingContextTest.cpp
M lldb/unittests/Language/CPlusPlus/CPlusPlusLanguageTest.cpp
M lldb/unittests/Language/ObjC/ObjCLanguageTest.cpp
Log Message:
-----------
[LLDB] Reapply refactored CPlusPlusLanguage::MethodName to break lldb-server dependencies (#135033)
The original PR is #132274.
Co-authored-by: @bulbazord Alex Langford
Commit: 90c01f4bad3132fcff4a73fb39efb64fe4c524b6
https://github.com/llvm/llvm-project/commit/90c01f4bad3132fcff4a73fb39efb64fe4c524b6
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/utils/TableGen/Basic/RISCVTargetDefEmitter.cpp
Log Message:
-----------
[RISCV] Add missing bitmask for some extensions (#135599)
According to:
https://github.com/riscv-non-isa/riscv-c-api-doc/blob/main/src/c-api.adoc#extension-bitmask-definitions
And we sort the bitmask by group id and then bit position.
Commit: 123993fd974629ca0a094918db4c21ad1c2624d0
https://github.com/llvm/llvm-project/commit/123993fd974629ca0a094918db4c21ad1c2624d0
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reversed-strided-node-with-external-ptr.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll
A llvm/test/Transforms/SLPVectorizer/X86/BinOpSameOpcodeHelper.ll
M llvm/test/Transforms/SLPVectorizer/X86/barriercall.ll
M llvm/test/Transforms/SLPVectorizer/X86/bottom-to-top-reorder.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-postpone-for-dependency.ll
M llvm/test/Transforms/SLPVectorizer/X86/bv-shuffle-mask.ll
M llvm/test/Transforms/SLPVectorizer/X86/extract-scalar-from-undef.ll
M llvm/test/Transforms/SLPVectorizer/X86/extractcost.ll
M llvm/test/Transforms/SLPVectorizer/X86/gathered-delayed-nodes-with-reused-user.ll
M llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-drop-wrapping-flags.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi-extracts-bv-combined.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-scheduled-inst-reused-as-last-inst.ll
M llvm/test/Transforms/SLPVectorizer/X86/propagate_ir_flags.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduced-val-vectorized-in-transform.ll
M llvm/test/Transforms/SLPVectorizer/X86/reorder_diamond_match.ll
M llvm/test/Transforms/SLPVectorizer/X86/shuffle-mask-emission.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll
M llvm/test/Transforms/SLPVectorizer/alternate-opcode-sindle-bv.ll
A llvm/test/Transforms/SLPVectorizer/isOpcodeOrAlt.ll
M llvm/test/Transforms/SLPVectorizer/resized-alt-shuffle-after-minbw.ll
M llvm/test/Transforms/SLPVectorizer/shuffle-mask-resized.ll
Log Message:
-----------
[SLP] Make getSameOpcode support interchangeable instructions. (#133888)
We use the term "interchangeable instructions" to refer to different
operators that have the same meaning (e.g., `add x, 0` is equivalent to
`mul x, 1`).
Non-constant values are not supported, as they may incur high costs with
little benefit.
---------
Co-authored-by: Alexey Bataev <a.bataev at gmx.com>
Commit: 76fec7dc0b0280c0eb321daac9f09161316c1259
https://github.com/llvm/llvm-project/commit/76fec7dc0b0280c0eb321daac9f09161316c1259
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M .github/workflows/premerge.yaml
M .mailmap
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Builtins.td
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Driver/ToolChains/Arch/ARM.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Serialization/ASTWriter.cpp
A clang/test/CodeGen/builtin-maxnum-minnum.c
A clang/test/Driver/arm-fpu-selection.s
A clang/test/Driver/armv7-default-neon.s
A clang/test/Driver/armv7s-default-vfpv4.s
M clang/test/Driver/armv8.1m.main.s
A clang/test/Modules/relocatable-modules.cpp
R libclc/generic/include/clc/atom_decl_int32.inc
R libclc/generic/include/clc/atom_decl_int64.inc
A libclc/generic/include/clc/atomic/atom_add.h
A libclc/generic/include/clc/atomic/atom_and.h
A libclc/generic/include/clc/atomic/atom_cmpxchg.h
A libclc/generic/include/clc/atomic/atom_dec.h
A libclc/generic/include/clc/atomic/atom_decl_int32.inc
A libclc/generic/include/clc/atomic/atom_decl_int64.inc
A libclc/generic/include/clc/atomic/atom_inc.h
A libclc/generic/include/clc/atomic/atom_max.h
A libclc/generic/include/clc/atomic/atom_min.h
A libclc/generic/include/clc/atomic/atom_or.h
A libclc/generic/include/clc/atomic/atom_sub.h
A libclc/generic/include/clc/atomic/atom_xchg.h
A libclc/generic/include/clc/atomic/atom_xor.h
R libclc/generic/include/clc/cl_khr_global_int32_base_atomics/atom_add.h
R libclc/generic/include/clc/cl_khr_global_int32_base_atomics/atom_cmpxchg.h
R libclc/generic/include/clc/cl_khr_global_int32_base_atomics/atom_dec.h
R libclc/generic/include/clc/cl_khr_global_int32_base_atomics/atom_inc.h
R libclc/generic/include/clc/cl_khr_global_int32_base_atomics/atom_sub.h
R libclc/generic/include/clc/cl_khr_global_int32_base_atomics/atom_xchg.h
R libclc/generic/include/clc/cl_khr_global_int32_extended_atomics/atom_and.h
R libclc/generic/include/clc/cl_khr_global_int32_extended_atomics/atom_max.h
R libclc/generic/include/clc/cl_khr_global_int32_extended_atomics/atom_min.h
R libclc/generic/include/clc/cl_khr_global_int32_extended_atomics/atom_or.h
R libclc/generic/include/clc/cl_khr_global_int32_extended_atomics/atom_xor.h
R libclc/generic/include/clc/cl_khr_int64_base_atomics/atom_add.h
R libclc/generic/include/clc/cl_khr_int64_base_atomics/atom_cmpxchg.h
R libclc/generic/include/clc/cl_khr_int64_base_atomics/atom_dec.h
R libclc/generic/include/clc/cl_khr_int64_base_atomics/atom_inc.h
R libclc/generic/include/clc/cl_khr_int64_base_atomics/atom_sub.h
R libclc/generic/include/clc/cl_khr_int64_base_atomics/atom_xchg.h
R libclc/generic/include/clc/cl_khr_int64_extended_atomics/atom_and.h
R libclc/generic/include/clc/cl_khr_int64_extended_atomics/atom_max.h
R libclc/generic/include/clc/cl_khr_int64_extended_atomics/atom_min.h
R libclc/generic/include/clc/cl_khr_int64_extended_atomics/atom_or.h
R libclc/generic/include/clc/cl_khr_int64_extended_atomics/atom_xor.h
R libclc/generic/include/clc/cl_khr_local_int32_base_atomics/atom_add.h
R libclc/generic/include/clc/cl_khr_local_int32_base_atomics/atom_cmpxchg.h
R libclc/generic/include/clc/cl_khr_local_int32_base_atomics/atom_dec.h
R libclc/generic/include/clc/cl_khr_local_int32_base_atomics/atom_inc.h
R libclc/generic/include/clc/cl_khr_local_int32_base_atomics/atom_sub.h
R libclc/generic/include/clc/cl_khr_local_int32_base_atomics/atom_xchg.h
R libclc/generic/include/clc/cl_khr_local_int32_extended_atomics/atom_and.h
R libclc/generic/include/clc/cl_khr_local_int32_extended_atomics/atom_max.h
R libclc/generic/include/clc/cl_khr_local_int32_extended_atomics/atom_min.h
R libclc/generic/include/clc/cl_khr_local_int32_extended_atomics/atom_or.h
R libclc/generic/include/clc/cl_khr_local_int32_extended_atomics/atom_xor.h
M libclc/generic/include/clc/clc.h
M libclc/generic/lib/SOURCES
R libclc/generic/lib/atom_int32_binary.inc
A libclc/generic/lib/atomic/atom_add.cl
A libclc/generic/lib/atomic/atom_and.cl
A libclc/generic/lib/atomic/atom_cmpxchg.cl
A libclc/generic/lib/atomic/atom_dec.cl
A libclc/generic/lib/atomic/atom_inc.cl
A libclc/generic/lib/atomic/atom_int32_binary.inc
A libclc/generic/lib/atomic/atom_max.cl
A libclc/generic/lib/atomic/atom_min.cl
A libclc/generic/lib/atomic/atom_or.cl
A libclc/generic/lib/atomic/atom_sub.cl
A libclc/generic/lib/atomic/atom_xchg.cl
A libclc/generic/lib/atomic/atom_xor.cl
R libclc/generic/lib/cl_khr_global_int32_base_atomics/atom_add.cl
R libclc/generic/lib/cl_khr_global_int32_base_atomics/atom_cmpxchg.cl
R libclc/generic/lib/cl_khr_global_int32_base_atomics/atom_dec.cl
R libclc/generic/lib/cl_khr_global_int32_base_atomics/atom_inc.cl
R libclc/generic/lib/cl_khr_global_int32_base_atomics/atom_sub.cl
R libclc/generic/lib/cl_khr_global_int32_base_atomics/atom_xchg.cl
R libclc/generic/lib/cl_khr_global_int32_extended_atomics/atom_and.cl
R libclc/generic/lib/cl_khr_global_int32_extended_atomics/atom_max.cl
R libclc/generic/lib/cl_khr_global_int32_extended_atomics/atom_min.cl
R libclc/generic/lib/cl_khr_global_int32_extended_atomics/atom_or.cl
R libclc/generic/lib/cl_khr_global_int32_extended_atomics/atom_xor.cl
R libclc/generic/lib/cl_khr_int64_base_atomics/atom_add.cl
R libclc/generic/lib/cl_khr_int64_base_atomics/atom_cmpxchg.cl
R libclc/generic/lib/cl_khr_int64_base_atomics/atom_dec.cl
R libclc/generic/lib/cl_khr_int64_base_atomics/atom_inc.cl
R libclc/generic/lib/cl_khr_int64_base_atomics/atom_sub.cl
R libclc/generic/lib/cl_khr_int64_base_atomics/atom_xchg.cl
R libclc/generic/lib/cl_khr_int64_extended_atomics/atom_and.cl
R libclc/generic/lib/cl_khr_int64_extended_atomics/atom_max.cl
R libclc/generic/lib/cl_khr_int64_extended_atomics/atom_min.cl
R libclc/generic/lib/cl_khr_int64_extended_atomics/atom_or.cl
R libclc/generic/lib/cl_khr_int64_extended_atomics/atom_xor.cl
R libclc/generic/lib/cl_khr_local_int32_base_atomics/atom_add.cl
R libclc/generic/lib/cl_khr_local_int32_base_atomics/atom_cmpxchg.cl
R libclc/generic/lib/cl_khr_local_int32_base_atomics/atom_dec.cl
R libclc/generic/lib/cl_khr_local_int32_base_atomics/atom_inc.cl
R libclc/generic/lib/cl_khr_local_int32_base_atomics/atom_sub.cl
R libclc/generic/lib/cl_khr_local_int32_base_atomics/atom_xchg.cl
R libclc/generic/lib/cl_khr_local_int32_extended_atomics/atom_and.cl
R libclc/generic/lib/cl_khr_local_int32_extended_atomics/atom_max.cl
R libclc/generic/lib/cl_khr_local_int32_extended_atomics/atom_min.cl
R libclc/generic/lib/cl_khr_local_int32_extended_atomics/atom_or.cl
R libclc/generic/lib/cl_khr_local_int32_extended_atomics/atom_xor.cl
M lldb/include/lldb/Core/Mangled.h
M lldb/include/lldb/Core/RichManglingContext.h
M lldb/include/lldb/Host/ProcessRunLock.h
M lldb/include/lldb/Target/Language.h
M lldb/source/Core/CMakeLists.txt
M lldb/source/Core/Mangled.cpp
M lldb/source/Core/Module.cpp
M lldb/source/Core/RichManglingContext.cpp
M lldb/source/Core/Statusline.cpp
M lldb/source/Host/common/ProcessRunLock.cpp
M lldb/source/Host/windows/ProcessRunLock.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionDeclMap.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.h
M lldb/source/Plugins/Language/ObjC/ObjCLanguage.cpp
M lldb/source/Plugins/Language/ObjC/ObjCLanguage.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.h
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/PDB/SymbolFilePDB.cpp
M lldb/source/Target/Process.cpp
M lldb/test/Shell/SymbolFile/NativePDB/inline_sites_live.cpp
M lldb/unittests/Core/CMakeLists.txt
M lldb/unittests/Core/RichManglingContextTest.cpp
M lldb/unittests/Language/CPlusPlus/CPlusPlusLanguageTest.cpp
M lldb/unittests/Language/ObjC/ObjCLanguageTest.cpp
M llvm/include/llvm/ADT/APFloat.h
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
A llvm/include/llvm/CodeGen/RemoveLoadsIntoFakeUses.h
M llvm/include/llvm/IR/Type.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/SandboxIR/Type.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp
M llvm/lib/CodeGen/MachineBlockPlacement.cpp
M llvm/lib/CodeGen/RemoveLoadsIntoFakeUses.cpp
M llvm/lib/IR/Type.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Support/APFloat.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCombine.td
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/CodeGen/AArch64/aarch64-sve-fill-spill-pair.ll
M llvm/test/CodeGen/AArch64/peephole-orr.mir
A llvm/test/CodeGen/AArch64/sve-vls-ldst-opt.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-sext-inreg.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-trunc-sextinreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
A llvm/test/CodeGen/AMDGPU/promote-alloca-non-byte-sizes.ll
A llvm/test/CodeGen/RISCV/emit-x8-as-fp.ll
M llvm/test/CodeGen/X86/fake-use-remove-loads.mir
A llvm/test/CodeGen/X86/pr134602.ll
A llvm/test/MC/Disassembler/RISCV/emit-x8-as-fp.txt
A llvm/test/MC/RISCV/emit-x8-as-fp.s
M llvm/test/Transforms/InstCombine/array.ll
M llvm/test/Transforms/InstCombine/fabs-as-int.ll
M llvm/test/Transforms/InstCombine/fneg-as-int.ll
M llvm/test/Transforms/InstCombine/fneg-fabs-as-int.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse-output.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reversed-strided-node-with-external-ptr.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll
A llvm/test/Transforms/SLPVectorizer/X86/BinOpSameOpcodeHelper.ll
M llvm/test/Transforms/SLPVectorizer/X86/barriercall.ll
M llvm/test/Transforms/SLPVectorizer/X86/bottom-to-top-reorder.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-postpone-for-dependency.ll
M llvm/test/Transforms/SLPVectorizer/X86/bv-shuffle-mask.ll
M llvm/test/Transforms/SLPVectorizer/X86/extract-scalar-from-undef.ll
M llvm/test/Transforms/SLPVectorizer/X86/extractcost.ll
M llvm/test/Transforms/SLPVectorizer/X86/gathered-delayed-nodes-with-reused-user.ll
M llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-drop-wrapping-flags.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi-extracts-bv-combined.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-scheduled-inst-reused-as-last-inst.ll
M llvm/test/Transforms/SLPVectorizer/X86/propagate_ir_flags.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduced-val-vectorized-in-transform.ll
M llvm/test/Transforms/SLPVectorizer/X86/reorder_diamond_match.ll
M llvm/test/Transforms/SLPVectorizer/X86/shuffle-mask-emission.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll
M llvm/test/Transforms/SLPVectorizer/alternate-opcode-sindle-bv.ll
A llvm/test/Transforms/SLPVectorizer/isOpcodeOrAlt.ll
M llvm/test/Transforms/SLPVectorizer/resized-alt-shuffle-after-minbw.ll
M llvm/test/Transforms/SLPVectorizer/shuffle-mask-resized.ll
M llvm/test/Transforms/SROA/non-capturing-call-readonly.ll
M llvm/test/Transforms/SROA/readonlynocapture.ll
M llvm/unittests/ADT/APFloatTest.cpp
M llvm/unittests/SandboxIR/TypesTest.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6-beta.1
[skip ci]
Commit: 06e2c7d017eb7db3d7de1e9435b0fbdc1733df33
https://github.com/llvm/llvm-project/commit/06e2c7d017eb7db3d7de1e9435b0fbdc1733df33
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M .github/workflows/premerge.yaml
M .mailmap
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Builtins.td
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Driver/ToolChains/Arch/ARM.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Serialization/ASTWriter.cpp
A clang/test/CodeGen/builtin-maxnum-minnum.c
A clang/test/Driver/arm-fpu-selection.s
A clang/test/Driver/armv7-default-neon.s
A clang/test/Driver/armv7s-default-vfpv4.s
M clang/test/Driver/armv8.1m.main.s
A clang/test/Modules/relocatable-modules.cpp
R libclc/generic/include/clc/atom_decl_int32.inc
R libclc/generic/include/clc/atom_decl_int64.inc
A libclc/generic/include/clc/atomic/atom_add.h
A libclc/generic/include/clc/atomic/atom_and.h
A libclc/generic/include/clc/atomic/atom_cmpxchg.h
A libclc/generic/include/clc/atomic/atom_dec.h
A libclc/generic/include/clc/atomic/atom_decl_int32.inc
A libclc/generic/include/clc/atomic/atom_decl_int64.inc
A libclc/generic/include/clc/atomic/atom_inc.h
A libclc/generic/include/clc/atomic/atom_max.h
A libclc/generic/include/clc/atomic/atom_min.h
A libclc/generic/include/clc/atomic/atom_or.h
A libclc/generic/include/clc/atomic/atom_sub.h
A libclc/generic/include/clc/atomic/atom_xchg.h
A libclc/generic/include/clc/atomic/atom_xor.h
R libclc/generic/include/clc/cl_khr_global_int32_base_atomics/atom_add.h
R libclc/generic/include/clc/cl_khr_global_int32_base_atomics/atom_cmpxchg.h
R libclc/generic/include/clc/cl_khr_global_int32_base_atomics/atom_dec.h
R libclc/generic/include/clc/cl_khr_global_int32_base_atomics/atom_inc.h
R libclc/generic/include/clc/cl_khr_global_int32_base_atomics/atom_sub.h
R libclc/generic/include/clc/cl_khr_global_int32_base_atomics/atom_xchg.h
R libclc/generic/include/clc/cl_khr_global_int32_extended_atomics/atom_and.h
R libclc/generic/include/clc/cl_khr_global_int32_extended_atomics/atom_max.h
R libclc/generic/include/clc/cl_khr_global_int32_extended_atomics/atom_min.h
R libclc/generic/include/clc/cl_khr_global_int32_extended_atomics/atom_or.h
R libclc/generic/include/clc/cl_khr_global_int32_extended_atomics/atom_xor.h
R libclc/generic/include/clc/cl_khr_int64_base_atomics/atom_add.h
R libclc/generic/include/clc/cl_khr_int64_base_atomics/atom_cmpxchg.h
R libclc/generic/include/clc/cl_khr_int64_base_atomics/atom_dec.h
R libclc/generic/include/clc/cl_khr_int64_base_atomics/atom_inc.h
R libclc/generic/include/clc/cl_khr_int64_base_atomics/atom_sub.h
R libclc/generic/include/clc/cl_khr_int64_base_atomics/atom_xchg.h
R libclc/generic/include/clc/cl_khr_int64_extended_atomics/atom_and.h
R libclc/generic/include/clc/cl_khr_int64_extended_atomics/atom_max.h
R libclc/generic/include/clc/cl_khr_int64_extended_atomics/atom_min.h
R libclc/generic/include/clc/cl_khr_int64_extended_atomics/atom_or.h
R libclc/generic/include/clc/cl_khr_int64_extended_atomics/atom_xor.h
R libclc/generic/include/clc/cl_khr_local_int32_base_atomics/atom_add.h
R libclc/generic/include/clc/cl_khr_local_int32_base_atomics/atom_cmpxchg.h
R libclc/generic/include/clc/cl_khr_local_int32_base_atomics/atom_dec.h
R libclc/generic/include/clc/cl_khr_local_int32_base_atomics/atom_inc.h
R libclc/generic/include/clc/cl_khr_local_int32_base_atomics/atom_sub.h
R libclc/generic/include/clc/cl_khr_local_int32_base_atomics/atom_xchg.h
R libclc/generic/include/clc/cl_khr_local_int32_extended_atomics/atom_and.h
R libclc/generic/include/clc/cl_khr_local_int32_extended_atomics/atom_max.h
R libclc/generic/include/clc/cl_khr_local_int32_extended_atomics/atom_min.h
R libclc/generic/include/clc/cl_khr_local_int32_extended_atomics/atom_or.h
R libclc/generic/include/clc/cl_khr_local_int32_extended_atomics/atom_xor.h
M libclc/generic/include/clc/clc.h
M libclc/generic/lib/SOURCES
R libclc/generic/lib/atom_int32_binary.inc
A libclc/generic/lib/atomic/atom_add.cl
A libclc/generic/lib/atomic/atom_and.cl
A libclc/generic/lib/atomic/atom_cmpxchg.cl
A libclc/generic/lib/atomic/atom_dec.cl
A libclc/generic/lib/atomic/atom_inc.cl
A libclc/generic/lib/atomic/atom_int32_binary.inc
A libclc/generic/lib/atomic/atom_max.cl
A libclc/generic/lib/atomic/atom_min.cl
A libclc/generic/lib/atomic/atom_or.cl
A libclc/generic/lib/atomic/atom_sub.cl
A libclc/generic/lib/atomic/atom_xchg.cl
A libclc/generic/lib/atomic/atom_xor.cl
R libclc/generic/lib/cl_khr_global_int32_base_atomics/atom_add.cl
R libclc/generic/lib/cl_khr_global_int32_base_atomics/atom_cmpxchg.cl
R libclc/generic/lib/cl_khr_global_int32_base_atomics/atom_dec.cl
R libclc/generic/lib/cl_khr_global_int32_base_atomics/atom_inc.cl
R libclc/generic/lib/cl_khr_global_int32_base_atomics/atom_sub.cl
R libclc/generic/lib/cl_khr_global_int32_base_atomics/atom_xchg.cl
R libclc/generic/lib/cl_khr_global_int32_extended_atomics/atom_and.cl
R libclc/generic/lib/cl_khr_global_int32_extended_atomics/atom_max.cl
R libclc/generic/lib/cl_khr_global_int32_extended_atomics/atom_min.cl
R libclc/generic/lib/cl_khr_global_int32_extended_atomics/atom_or.cl
R libclc/generic/lib/cl_khr_global_int32_extended_atomics/atom_xor.cl
R libclc/generic/lib/cl_khr_int64_base_atomics/atom_add.cl
R libclc/generic/lib/cl_khr_int64_base_atomics/atom_cmpxchg.cl
R libclc/generic/lib/cl_khr_int64_base_atomics/atom_dec.cl
R libclc/generic/lib/cl_khr_int64_base_atomics/atom_inc.cl
R libclc/generic/lib/cl_khr_int64_base_atomics/atom_sub.cl
R libclc/generic/lib/cl_khr_int64_base_atomics/atom_xchg.cl
R libclc/generic/lib/cl_khr_int64_extended_atomics/atom_and.cl
R libclc/generic/lib/cl_khr_int64_extended_atomics/atom_max.cl
R libclc/generic/lib/cl_khr_int64_extended_atomics/atom_min.cl
R libclc/generic/lib/cl_khr_int64_extended_atomics/atom_or.cl
R libclc/generic/lib/cl_khr_int64_extended_atomics/atom_xor.cl
R libclc/generic/lib/cl_khr_local_int32_base_atomics/atom_add.cl
R libclc/generic/lib/cl_khr_local_int32_base_atomics/atom_cmpxchg.cl
R libclc/generic/lib/cl_khr_local_int32_base_atomics/atom_dec.cl
R libclc/generic/lib/cl_khr_local_int32_base_atomics/atom_inc.cl
R libclc/generic/lib/cl_khr_local_int32_base_atomics/atom_sub.cl
R libclc/generic/lib/cl_khr_local_int32_base_atomics/atom_xchg.cl
R libclc/generic/lib/cl_khr_local_int32_extended_atomics/atom_and.cl
R libclc/generic/lib/cl_khr_local_int32_extended_atomics/atom_max.cl
R libclc/generic/lib/cl_khr_local_int32_extended_atomics/atom_min.cl
R libclc/generic/lib/cl_khr_local_int32_extended_atomics/atom_or.cl
R libclc/generic/lib/cl_khr_local_int32_extended_atomics/atom_xor.cl
M lldb/include/lldb/Core/Mangled.h
M lldb/include/lldb/Core/RichManglingContext.h
M lldb/include/lldb/Host/ProcessRunLock.h
M lldb/include/lldb/Target/Language.h
M lldb/source/Core/CMakeLists.txt
M lldb/source/Core/Mangled.cpp
M lldb/source/Core/Module.cpp
M lldb/source/Core/RichManglingContext.cpp
M lldb/source/Core/Statusline.cpp
M lldb/source/Host/common/ProcessRunLock.cpp
M lldb/source/Host/windows/ProcessRunLock.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionDeclMap.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.h
M lldb/source/Plugins/Language/ObjC/ObjCLanguage.cpp
M lldb/source/Plugins/Language/ObjC/ObjCLanguage.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.h
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/PDB/SymbolFilePDB.cpp
M lldb/source/Target/Process.cpp
M lldb/test/Shell/SymbolFile/NativePDB/inline_sites_live.cpp
M lldb/unittests/Core/CMakeLists.txt
M lldb/unittests/Core/RichManglingContextTest.cpp
M lldb/unittests/Language/CPlusPlus/CPlusPlusLanguageTest.cpp
M lldb/unittests/Language/ObjC/ObjCLanguageTest.cpp
M llvm/include/llvm/ADT/APFloat.h
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
A llvm/include/llvm/CodeGen/RemoveLoadsIntoFakeUses.h
M llvm/include/llvm/IR/Type.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/SandboxIR/Type.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp
M llvm/lib/CodeGen/MachineBlockPlacement.cpp
M llvm/lib/CodeGen/RemoveLoadsIntoFakeUses.cpp
M llvm/lib/IR/Type.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Support/APFloat.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCombine.td
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/CodeGen/AArch64/aarch64-sve-fill-spill-pair.ll
M llvm/test/CodeGen/AArch64/peephole-orr.mir
A llvm/test/CodeGen/AArch64/sve-vls-ldst-opt.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-sext-inreg.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-trunc-sextinreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
A llvm/test/CodeGen/AMDGPU/promote-alloca-non-byte-sizes.ll
A llvm/test/CodeGen/RISCV/emit-x8-as-fp.ll
M llvm/test/CodeGen/X86/fake-use-remove-loads.mir
A llvm/test/CodeGen/X86/pr134602.ll
A llvm/test/MC/Disassembler/RISCV/emit-x8-as-fp.txt
A llvm/test/MC/RISCV/emit-x8-as-fp.s
M llvm/test/Transforms/InstCombine/array.ll
M llvm/test/Transforms/InstCombine/fabs-as-int.ll
M llvm/test/Transforms/InstCombine/fneg-as-int.ll
M llvm/test/Transforms/InstCombine/fneg-fabs-as-int.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse-output.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reversed-strided-node-with-external-ptr.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll
A llvm/test/Transforms/SLPVectorizer/X86/BinOpSameOpcodeHelper.ll
M llvm/test/Transforms/SLPVectorizer/X86/barriercall.ll
M llvm/test/Transforms/SLPVectorizer/X86/bottom-to-top-reorder.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-postpone-for-dependency.ll
M llvm/test/Transforms/SLPVectorizer/X86/bv-shuffle-mask.ll
M llvm/test/Transforms/SLPVectorizer/X86/extract-scalar-from-undef.ll
M llvm/test/Transforms/SLPVectorizer/X86/extractcost.ll
M llvm/test/Transforms/SLPVectorizer/X86/gathered-delayed-nodes-with-reused-user.ll
M llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-drop-wrapping-flags.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi-extracts-bv-combined.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-scheduled-inst-reused-as-last-inst.ll
M llvm/test/Transforms/SLPVectorizer/X86/propagate_ir_flags.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduced-val-vectorized-in-transform.ll
M llvm/test/Transforms/SLPVectorizer/X86/reorder_diamond_match.ll
M llvm/test/Transforms/SLPVectorizer/X86/shuffle-mask-emission.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll
M llvm/test/Transforms/SLPVectorizer/alternate-opcode-sindle-bv.ll
A llvm/test/Transforms/SLPVectorizer/isOpcodeOrAlt.ll
M llvm/test/Transforms/SLPVectorizer/resized-alt-shuffle-after-minbw.ll
M llvm/test/Transforms/SLPVectorizer/shuffle-mask-resized.ll
M llvm/test/Transforms/SROA/non-capturing-call-readonly.ll
M llvm/test/Transforms/SROA/readonlynocapture.ll
M llvm/unittests/ADT/APFloatTest.cpp
M llvm/unittests/SandboxIR/TypesTest.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
Log Message:
-----------
Rebase
Created using spr 1.3.6-beta.1
Compare: https://github.com/llvm/llvm-project/compare/3cde4664e547...06e2c7d017eb
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