[all-commits] [llvm/llvm-project] 13a26c: [GlobalISel] Combine redundant sext_inreg

[Pierre van Houtryve via All-commits]

  Branch: refs/heads/users/pierre-vh/combine-redundant-sext-inreg
  Home:   https://github.com/llvm/llvm-project
  Commit: 13a26c209ae46f3fc49542783679ce9b4b19a27c
      https://github.com/llvm/llvm-project/commit/13a26c209ae46f3fc49542783679ce9b4b19a27c
  Author: pvanhout <pierre.vanhoutryve at amd.com>
  Date:   2025-04-14 (Mon, 14 Apr 2025)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
    M llvm/include/llvm/Target/GlobalISel/Combine.td
    M llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp
    A llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-sext-inreg.mir
    A llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-trunc-sextinreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll

  Log Message:
  -----------
  [GlobalISel] Combine redundant sext_inreg


  Commit: e0333cfa5553ae7906d724ec277e763ac81aaa9a
      https://github.com/llvm/llvm-project/commit/e0333cfa5553ae7906d724ec277e763ac81aaa9a
  Author: pvanhout <pierre.vanhoutryve at amd.com>
  Date:   2025-04-14 (Mon, 14 Apr 2025)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
    M llvm/include/llvm/Target/GlobalISel/Combine.td
    M llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp

  Log Message:
  -----------
  check canReplaceReg


  Commit: 4051ceeadf74029f45a9b461bfc67195839c7e98
      https://github.com/llvm/llvm-project/commit/4051ceeadf74029f45a9b461bfc67195839c7e98
  Author: pvanhout <pierre.vanhoutryve at amd.com>
  Date:   2025-04-14 (Mon, 14 Apr 2025)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp

  Log Message:
  -----------
  add missing return


  Commit: afc49f1d51c929cc65e0c9e6d496fa7c6aa05684
      https://github.com/llvm/llvm-project/commit/afc49f1d51c929cc65e0c9e6d496fa7c6aa05684
  Author: pvanhout <pierre.vanhoutryve at amd.com>
  Date:   2025-04-14 (Mon, 14 Apr 2025)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-sext-inreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-trunc-sextinreg.mir

  Log Message:
  -----------
  drop -verify-machineinstrs


Compare: https://github.com/llvm/llvm-project/compare/5a8230e35741...afc49f1d51c9

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