[all-commits] [llvm/llvm-project] 0f607f: [VPlan] Simplify 'or x, true' -> true.
Aiden Grossman via All-commits
all-commits at lists.llvm.org
Mon Apr 14 00:38:26 PDT 2025
Branch: refs/heads/users/boomanaiden154/githubci-upload-ninja_log-as-an-artifact
Home: https://github.com/llvm/llvm-project
Commit: 0f607f3df54e22896b484510f0c1ccfb718de67a
https://github.com/llvm/llvm-project/commit/0f607f3df54e22896b484510f0c1ccfb718de67a
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/SystemZ/pr47665.ll
M llvm/test/Transforms/LoopVectorize/X86/constant-fold.ll
Log Message:
-----------
[VPlan] Simplify 'or x, true' -> true.
Add additional OR simplification to fix a divergence between legacy and
VPlan-based cost model.
This adds a new m_AllOnes matcher by generalizing specific_intval to
int_pred_ty, which takes a predicate to check to support matching both
specific APInts and other APInt predices, like isAllOnes.
Fixes https://github.com/llvm/llvm-project/issues/131359.
Commit: ed43207306f7351f2b4f8284710b028df973d74e
https://github.com/llvm/llvm-project/commit/ed43207306f7351f2b4f8284710b028df973d74e
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll
M llvm/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table_big.ll
M llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest.ll
Log Message:
-----------
[SimplifyCFG] Handle trunc condition in foldBranchToCommonDest. (#135490)
proof: https://alive2.llvm.org/ce/z/v32Aof
Commit: 77fcdb9f26d2d9da04767894b23b71e52e5ac7ce
https://github.com/llvm/llvm-project/commit/77fcdb9f26d2d9da04767894b23b71e52e5ac7ce
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
Log Message:
-----------
[Scalar] Avoid repeated hash lookups (NFC) (#132660)
Commit: bb9580a02b393683ff0b6c360df684f33c715a1f
https://github.com/llvm/llvm-project/commit/bb9580a02b393683ff0b6c360df684f33c715a1f
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
A llvm/test/Analysis/ScalarEvolution/pr135531.ll
Log Message:
-----------
[SCEV] Use ashr to adjust constant multipliers (#135534)
SCEV converts "-2 *nsw (i32 V)" into "2148473647 *nsw (i32 V)". But we
cannot preserve the nsw flag when the constant multiplier is negative.
This patch changes lshr to ashr so that we can preserve both nsw and nuw
flags.
Alive2 proof: https://alive2.llvm.org/ce/z/LZVSEa
Closes https://github.com/llvm/llvm-project/issues/135531.
Commit: 5550d302288f95fc9bb91d0ba35e5ca459ffd9b1
https://github.com/llvm/llvm-project/commit/5550d302288f95fc9bb91d0ba35e5ca459ffd9b1
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/SystemZ/pr47665.ll
M llvm/test/Transforms/LoopVectorize/X86/constant-fold.ll
Log Message:
-----------
[VPlan] Check captured operand when simplifying redundant OR.
Follow-up to 0f607f to actually use the captured operand X instead of Y.
Commit: 703cfe745b96751c1204bcffe4e56038c809247f
https://github.com/llvm/llvm-project/commit/703cfe745b96751c1204bcffe4e56038c809247f
Author: Peng Liu <winner245 at hotmail.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M libcxx/include/__bit/popcount.h
M libcxx/include/__stop_token/atomic_unique_lock.h
Log Message:
-----------
[libc++] Replace __libcpp_popcount by __builtin_popcountg (#133937)
`__libcpp_popcount` was previously used as a fallback for `__builtin_popcountg` to ensure compatibility with older compilers (Clang 18 and earlier), as `__builtin_popcountg` became available in Clang 19. Now that support for Clang 18 has been officially dropped in #130142, we can now safely replace all instances of `__libcpp_popcount` with `__builtin_popcountg` and eliminate the fallback logic.
Commit: 62d2cc84ac57afa47c2b1de599f9fd6e40adaacd
https://github.com/llvm/llvm-project/commit/62d2cc84ac57afa47c2b1de599f9fd6e40adaacd
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
Log Message:
-----------
[CodeGen] Avoid repeated hash lookups (NFC) (#135540)
Commit: 4b4cd645a829b8e510bdb008f449969d7bf53c30
https://github.com/llvm/llvm-project/commit/4b4cd645a829b8e510bdb008f449969d7bf53c30
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/DebugObjectManagerPlugin.cpp
Log Message:
-----------
[ExecutionEngine] Avoid repeated map lookups (NFC) (#135541)
Commit: d1d5f00a8eb43aaa22274c06b58d567f19e284fe
https://github.com/llvm/llvm-project/commit/d1d5f00a8eb43aaa22274c06b58d567f19e284fe
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M llvm/lib/Passes/StandardInstrumentations.cpp
Log Message:
-----------
[Passes] Avoid repeated hash lookups (NFC) (#135542)
Commit: ccfb97b42174eab118a4e4222c25e986db876563
https://github.com/llvm/llvm-project/commit/ccfb97b42174eab118a4e4222c25e986db876563
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/ROCm.h
M clang/test/Driver/amdgpu-openmp-toolchain.c
M clang/test/Driver/hip-device-libs.hip
M clang/test/Driver/rocm-device-libs.cl
M flang/test/Driver/omp-driver-offload.f90
Log Message:
-----------
Revert "clang/AMDGPU: Stop looking for oclc_daz_opt_* control libraries (#134805)"
This reverts commit 028429ac452acde227ae0bfafbfe8579c127e1ea and
1004fae222efeee215780c4bb4e64eb82b07fb4f.
These really need to be part of the compiler distribution. Bots are
relying on a nearly year old version to provide bitcode.
Commit: 1264d7a53a4de3094672be2a248db57b213f33ac
https://github.com/llvm/llvm-project/commit/1264d7a53a4de3094672be2a248db57b213f33ac
Author: Daniel Chen <cdchen at ca.ibm.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/include/clang/Driver/ToolChain.h
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/AIX.cpp
M clang/lib/Driver/ToolChains/AIX.h
M clang/lib/Driver/ToolChains/PPCLinux.cpp
M clang/lib/Driver/ToolChains/PPCLinux.h
M flang/test/Driver/flang-ld-powerpc.f90
M flang/test/Driver/linker-flags.f90
Log Message:
-----------
[driver] Generalize the code that adds the path of libflang_rt.runtime.a. (#134362)
The PR is to generalize the re-use of the `compilerRT` code of adding
the path of `libflang_rt.runtime.a (so)` from AIX and LoP only to all
platforms via a new function `addFlangRTLibPath`.
It also added `-static-libflangrt` and `-shared-libflangrt` compiler
options to allow users choosing which `flang-rt` to link to. It defaults
to shared `flang-rt`, which is consistent with the linker behavior,
except on AIX, it defaults to static.
Also, PR #134320 exposed an issue in PR #131041 that the the overriding
`addFortranRuntimeLibs` is missing the link to `libquadmath`. This PR
also fixed that and restored the test case that PR #131041 broke.
Commit: 578ca5e469ef1c91a79aa15bc186921ee7faa855
https://github.com/llvm/llvm-project/commit/578ca5e469ef1c91a79aa15bc186921ee7faa855
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/utils/TableGen/ClangOpcodesEmitter.cpp
Log Message:
-----------
[clang][bytecode] Print jump lines in Function::dump() (#135482)
E.g. for
```c++
constexpr int foo(int b) {
int a = 1+1;
for (int i = 0; i < b; ++i) {
++a;
}
return a;
}
```
we now print:
```
foo 0x7cc8d4bf0580
frame size: 128
arg size: 8
rvo: 0
this arg: 0
0 InitScope 0
16 ConstSint32 1
32 ConstSint32 1
48 AddSint32
56 SetLocalSint32 40
72 ConstSint32 0
88 SetLocalSint32 104
104 GetPtrLocal 104 <-+
120 LoadPopSint32 |
128 GetPtrParam 0 |
144 LoadPopSint32 |
152 LTSint32 |
160 Jf 80 --+ |
176 GetPtrLocal 40 | |
192 IncPopSint32 1 | |
208 GetPtrLocal 104 | |
224 IncPopSint32 1 | |
240 Jmp -152 | --+
256 GetPtrLocal 40 <-+
272 LoadPopSint32
280 Destroy 0
296 RetSint32
304 Destroy 0
320 NoRet
```
Commit: ce01e4e2f6cb2a1c37e3acceeac931b2031a02e8
https://github.com/llvm/llvm-project/commit/ce01e4e2f6cb2a1c37e3acceeac931b2031a02e8
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M clang/lib/CodeGen/Targets/AMDGPU.cpp
M clang/test/CodeGenOpenCL/addr-space-struct-arg.cl
M clang/test/CodeGenOpenCL/amdgpu-abi-struct-arg-byref.cl
M clang/test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl
M clang/test/CodeGenOpenCL/opencl-kernel-call.cl
Log Message:
-----------
[Clang][OpenCL][AMDGPU] Use `byref` for aggregate OpenCL kernel arguments (#134892)
Due to a previous workaround allowing kernels to be called from other
functions,
Clang currently doesn't use the `byref` attribute for aggregate kernel
arguments. The issue was recently resolved in
https://github.com/llvm/llvm-project/pull/115821. With that fix, we can
now
enable the use of `byref` consistently across all languages.
Co-authored-by: Matt Arsenault <Matthew.Arsenault at amd.com>
Fixes SWDEV-247226.
Co-authored-by: Matt Arsenault <Matthew.Arsenault at amd.com>
Commit: db20b0d4ec96e4dee0b5ca6e7ddd616eafd88d40
https://github.com/llvm/llvm-project/commit/db20b0d4ec96e4dee0b5ca6e7ddd616eafd88d40
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M llvm/test/Transforms/ObjCARC/contract.ll
Log Message:
-----------
ObjCARC: Add regressed testcase from #134275
Commit: a24ef4b07ee798b14fe0f3daa23cc3ec09410bc6
https://github.com/llvm/llvm-project/commit/a24ef4b07ee798b14fe0f3daa23cc3ec09410bc6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/test/Transforms/InstCombine/sincospi.ll
Log Message:
-----------
SimplifyLibCalls: Skip sincospi optimization for ConstantData (#134688)
Avoids looking at the uselist, and it would probably be more
productive to constant fold this.
Commit: b37476f99c37a9edf48684d82dde745d9e0df957
https://github.com/llvm/llvm-project/commit/b37476f99c37a9edf48684d82dde745d9e0df957
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M llvm/lib/Analysis/PHITransAddr.cpp
M llvm/test/Transforms/GVN/pr65447.ll
Log Message:
-----------
PHITransAddr: Avoid looking at constant use lists (#134689)
Avoids asserts in GVN
Commit: 393c783a10052b14d2b76b3ee930b3d83e7f1a16
https://github.com/llvm/llvm-project/commit/393c783a10052b14d2b76b3ee930b3d83e7f1a16
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/test/CodeGen/AMDGPU/swdev380865.ll
M llvm/test/CodeGen/PowerPC/pr43527.ll
M llvm/test/CodeGen/PowerPC/pr48519.ll
M llvm/test/CodeGen/PowerPC/sms-grp-order.ll
M llvm/test/Transforms/LICM/pr50367.ll
M llvm/test/Transforms/LICM/pr59324.ll
Log Message:
-----------
LICM: Avoid looking at use list of constant data (#134690)
The codegen test changes seem incidental. Either way,
sms-grp-order.ll seems to already not hit the original issue.
Commit: 30ae47eeefaeb2c78ae7f234621b8bb0444b7844
https://github.com/llvm/llvm-project/commit/30ae47eeefaeb2c78ae7f234621b8bb0444b7844
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
Log Message:
-----------
SCEVExpander: Don't look at uses of constants (#134691)
This could be more relaxed, and look for uses of globals in
the same function but no tests apparently depend on that.
Commit: 0a27c4e318e778b520306a9e2102e03023cfaa33
https://github.com/llvm/llvm-project/commit/0a27c4e318e778b520306a9e2102e03023cfaa33
Author: Reid Kleckner <rnk at google.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M llvm/cmake/modules/TableGen.cmake
M llvm/include/llvm/TableGen/Main.h
M llvm/include/llvm/TableGen/StringToOffsetTable.h
M llvm/lib/TableGen/CMakeLists.txt
M llvm/lib/TableGen/Main.cpp
A llvm/lib/TableGen/StringToOffsetTable.cpp
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
M llvm/utils/TableGen/Basic/SequenceToOffsetTable.h
M llvm/utils/TableGen/Basic/TableGen.cpp
M llvm/utils/TableGen/SDNodeInfoEmitter.cpp
M llvm/utils/gn/secondary/llvm/lib/TableGen/BUILD.gn
Log Message:
-----------
[StrTable] Use string literal emission for intrinsics on non-MSVC platforms (#124856)
This mainly transitions the LLVM intrinsic string table from character
emission to string literal emission, which I confirmed happens for me
locally.
I moved the guts of StringToOffsetTable to a cpp file so I could move
the `EmitLongStrLiterals` cl::opt global to a non-vague linkage home in
the `TableGen` library. I had to add missing FormatVariadic.h includes
to account for moving other includes to a cpp file.
Commit: 5f11d64cfb44fc0adf3d3235b0e480d930379e9d
https://github.com/llvm/llvm-project/commit/5f11d64cfb44fc0adf3d3235b0e480d930379e9d
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M clang/lib/Format/WhitespaceManager.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Fix a bug in AlignConsecutiveDeclarations (#135516)
Fix #109768
Commit: c41ef751f85ee42f40380d064f44cfd347fb6215
https://github.com/llvm/llvm-project/commit/c41ef751f85ee42f40380d064f44cfd347fb6215
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Treat lambda in braced init as inline (#135520)
Fix #125430
Commit: dd107b20daedbc49dc3003ae2cb2e846267c308c
https://github.com/llvm/llvm-project/commit/dd107b20daedbc49dc3003ae2cb2e846267c308c
Author: Firas Khalil Khana <firasuke at gmail.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M libunwind/docs/BuildingLibunwind.rst
Log Message:
-----------
Update LIBUNWIND_ENABLE_WERROR default value in BuildingLibunwind.rst (#135546)
`LIBUNWIND_ENABLE_WERROR` defaults to `OFF` according to
[CMakeLists.txt](https://github.com/llvm/llvm-project/blob/main/libunwind/CMakeLists.txt#L43).
Commit: 974bda8f61e056f90b17baa6db686c91d20ebe9d
https://github.com/llvm/llvm-project/commit/974bda8f61e056f90b17baa6db686c91d20ebe9d
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/test/AST/ByteCode/codegen.cpp
Log Message:
-----------
[clang][bytecode] Reject constexpr-unknown pointers from Inc ops (#135548)
We used to accept c++ as a known value here, causing wrong codegen.
Commit: c0afb77c2ab92d244d66f2e9bfcf7da92af6091c
https://github.com/llvm/llvm-project/commit/c0afb77c2ab92d244d66f2e9bfcf7da92af6091c
Author: Fangrui Song <i at maskray.me>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/test/MC/RISCV/function-call-invalid.s
M llvm/test/MC/RISCV/tail-call-invalid.s
Log Message:
-----------
RISCVAsmParser: Reject call foo at invalid
... instead of silently parsing and ignoring it without leaving an error
message.
While here, remove an unreachable `@plt`.
Pull Request: https://github.com/llvm/llvm-project/pull/135509
Commit: d893d129e6ee8b4dead1532cd8420750908acca6
https://github.com/llvm/llvm-project/commit/d893d129e6ee8b4dead1532cd8420750908acca6
Author: Ivan Butygin <ivan.butygin at gmail.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
M mlir/lib/Dialect/GPU/Transforms/ShuffleRewriter.cpp
A mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-unsupported.mlir
M mlir/test/Dialect/GPU/shuffle-rewrite.mlir
Log Message:
-----------
[mlir] GPUToROCDL: Fix crashes with unsupported shuffle datatypes (#135504)
Calling `getIntOrFloatBitWidth` on non-int/float types (`gpu.shuffle`
also accepts vectors) will crash.
Commit: e555ccaa4da77b5d3065ed7d002e7073db995199
https://github.com/llvm/llvm-project/commit/e555ccaa4da77b5d3065ed7d002e7073db995199
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M llvm/include/llvm/DebugInfo/LogicalView/Readers/LVDWARFReader.h
M llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
M llvm/lib/Target/Hexagon/HexagonTfrCleanup.cpp
M llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
Log Message:
-----------
[llvm] Call *Map::erase directly (NFC) (#135545)
Commit: 91a205653e8fa5a338c985b9a9dbaaaec62e3475
https://github.com/llvm/llvm-project/commit/91a205653e8fa5a338c985b9a9dbaaaec62e3475
Author: Matthew Devereau <matthew.devereau at arm.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M clang/test/CodeGen/AArch64/sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-abs-srshl.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-all-active-lanes-cvt.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-loadstore.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-cmpne.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-strictfp.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsics-combine-to-u-forms.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsics-ptest.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsics-rdffr-predication.ll
Log Message:
-----------
[AArch64][SVE] Instcombine ptrue(all) to splat(i1) (#135016)
SVE Operations such as predicated loads become canonicalized to LLVM
masked loads, and doing the same for ptrue(all) to splat(1) creates
further optimization opportunities from generic LLVM IR passes.
Commit: 543351babff4144675ee8259eeddafc7b441bf0c
https://github.com/llvm/llvm-project/commit/543351babff4144675ee8259eeddafc7b441bf0c
Author: Sayan Saha <sayans at mathworks.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/test/Dialect/Tosa/canonicalize.mlir
Log Message:
-----------
[tosa] : Re-enable PR #135429 with ASAN fix (#135560)
Removed the calls to `sizeOp` after replacing `SliceOp`:
```
// Remove const_shape size op when it no longer has use point.
Operation *sizeConstShape = sliceOp.getSize().getDefiningOp();
```
Turns out as part of canonicalization, trivially dead ops are removed
anyway, so the above piece of code isn't actually needed.
Commit: 87322c903976b4b24b96f460719181cbebde1547
https://github.com/llvm/llvm-project/commit/87322c903976b4b24b96f460719181cbebde1547
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M llvm/lib/ObjCopy/ELF/ELFObjcopy.cpp
Log Message:
-----------
[ObjCopy] Use llvm::reverse (NFC) (#135559)
Commit: 99df442df1f88c1078c433618c75ee62f3dd8512
https://github.com/llvm/llvm-project/commit/99df442df1f88c1078c433618c75ee62f3dd8512
Author: Adrian Prantl <aprantl at apple.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M lldb/test/API/python_api/target/read-instructions-flavor/TestTargetReadInstructionsFlavor.py
Log Message:
-----------
Skip test on Darwin
Commit: 3de93015386f17d3430c6534b9fa3e2a9adfaa1a
https://github.com/llvm/llvm-project/commit/3de93015386f17d3430c6534b9fa3e2a9adfaa1a
Author: Yoann Congal <yoann.congal at smile.fr>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M clang-tools-extra/clangd/CMakeLists.txt
M clang-tools-extra/clangd/test/CMakeLists.txt
M clang-tools-extra/clangd/test/lit.site.cfg.py.in
Log Message:
-----------
[clangd] Add a build option to disable building dexp (#133124)
Building dexp on Debian 11 currently causes intermittent failures [0] [1].
Adding the CLANGD_BUILD_DEXP option to disable dexp from the build
allows Debian 11 users to build clang (albeit without the dexp tool).
This option is set to "Build Dexp" by default so, no change is expected
without manual setting.
[0]: https://bugzilla.yoctoproject.org/show_bug.cgi?id=15803
[1]: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1101322
Commit: 425ccd50dc6dd154c448fba8dbcbb4d2f726b331
https://github.com/llvm/llvm-project/commit/425ccd50dc6dd154c448fba8dbcbb4d2f726b331
Author: Nico Weber <thakis at chromium.org>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M llvm/utils/gn/secondary/clang-tools-extra/clangd/test/BUILD.gn
Log Message:
-----------
[gn] port 3de93015386f
Commit: cbe8f3ad7621e402b050e768f400ff0d19c3aedd
https://github.com/llvm/llvm-project/commit/cbe8f3ad7621e402b050e768f400ff0d19c3aedd
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop2.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop2.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop2.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp8.s
Log Message:
-----------
[AMDGPU][True16][MC] fix fmac_f16_t16 vop3 format (#135464)
add fmac_f16_t16_e64 to isfmac check to fix the vop3 format of
fmac_f16_t16 instruction
Commit: 52e45a79ad24f8a2347a5566e6abaa207918df62
https://github.com/llvm/llvm-project/commit/52e45a79ad24f8a2347a5566e6abaa207918df62
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M lldb/include/lldb/Target/Language.h
M lldb/source/Core/FormatEntity.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.h
M lldb/source/Target/Language.cpp
Log Message:
-----------
[lldb][Language] Change GetFunctionDisplayName to take SymbolContext by reference (#135536)
Both the `CPlusPlusLanguage` plugins and the Swift language plugin
already assume the `sc != nullptr`. And all `FormatEntity` callsites of
`GetFunctionDisplayName` already check for nullptr before passing `sc`.
This patch makes this pre-condition explicit by changing the parameter
to `const SymbolContext &`. This will help with some upcoming changes in
this area.
Commit: 5710759eb390c0d5274c2a4d43967282d7df1993
https://github.com/llvm/llvm-project/commit/5710759eb390c0d5274c2a4d43967282d7df1993
Author: Fangrui Song <i at maskray.me>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M llvm/include/llvm/MC/MCAsmBackend.h
M llvm/lib/MC/MCAsmBackend.cpp
M llvm/lib/MC/MCAssembler.cpp
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
Log Message:
-----------
MCAsmBackend,X86: Pass MCValue to fixupNeedsRelaxationAdvanced. NFC
This parameter eliminates a redundant computation for VK_ABS8 in X86 and
reduces reliance on shouldForceRelocation in relaxation decisions.
Note: `local: jmp local at plt` relaxes JMP. This behavior depends on
fixupNeedsRelaxation calling shouldForceRelocation, which might change
in the future.
Commit: 1e153b782ea3054c02dd0016314fca11a5d781da
https://github.com/llvm/llvm-project/commit/1e153b782ea3054c02dd0016314fca11a5d781da
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M lldb/include/lldb/Symbol/SymbolContext.h
M lldb/source/Core/FormatEntity.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Symbol/SymbolContext.cpp
M lldb/test/API/functionalities/param_entry_vals/basic_entry_values/main.cpp
M lldb/test/API/functionalities/tail_call_frames/inlining_and_tail_calls/main.cpp
M lldb/test/Shell/Recognizer/verbose_trap-in-stl-max-depth.test
M lldb/test/Shell/Settings/TestFrameFormatName.test
Log Message:
-----------
[lldb][Format] Display only the inlined frame name in backtraces if available (#135343)
When a frame is inlined, LLDB will display its name in backtraces as
follows:
```
* thread #1, queue = 'com.apple.main-thread', stop reason = breakpoint 1.3
* frame #0: 0x0000000100000398 a.out`func() [inlined] baz(x=10) at inline.cpp:1:42
frame #1: 0x0000000100000398 a.out`func() [inlined] bar() at inline.cpp:2:37
frame #2: 0x0000000100000398 a.out`func() at inline.cpp:4:15
frame #3: 0x00000001000003c0 a.out`main at inline.cpp:7:5
frame #4: 0x000000026eb29ab8 dyld`start + 6812
```
The longer the names get the more confusing this gets because the first
function name that appears is the parent frame. My assumption (which may
need some more surveying) is that for the majority of cases we only care
about the actual frame name (not the parent). So this patch removes all
the special logic that prints the parent frame.
Another quirk of the current format is that the inlined frame name does
not abide by the `${function.name-XXX}` format variables. We always just
print the raw demangled name. With this patch, we would format the
inlined frame name according to the `frame-format` setting (see the
test-cases).
If we really want to have the `parentFrame [inlined] inlinedFrame`
format, we could expose it through a new `frame-format` variable (e..g.,
`${function.inlined-at-name}` and let the user decide where to place
things.
Commit: 634f9a981571eae000c1adc311014c5c64486187
https://github.com/llvm/llvm-project/commit/634f9a981571eae000c1adc311014c5c64486187
Author: Fangrui Song <i at maskray.me>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
Log Message:
-----------
ARMAsmBackend: Use fixupNeedsRelaxationAdvanced. NFC
This prepares for the upcoming change to simplify relocation recording
in MCAssembler.
While both MCAssembler::fixupNeedsRelaxation and
MCAssembler::handleFixup call evaluateFixup and use
shouldForceRelocation, the shouldForceRelocation logic is not supposed
to be needed by MCAssembler::fixupNeedsRelaxation.
The ARM special cases for interworking branches
(https://reviews.llvm.org/D33436 and https://reviews.llvm.org/D33898)
break the assumption. Switch to fixupNeedsRelaxationAdvanced and
explicitly test the conditions.
Commit: af7a7ba4aadea3600e78a5f522b72e5413c8e595
https://github.com/llvm/llvm-project/commit/af7a7ba4aadea3600e78a5f522b72e5413c8e595
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M lldb/source/Core/FormatEntity.cpp
Log Message:
-----------
[lldb][Format][NFC] Factor FunctionNameWithArgs case out into helper function
Commit: 5d87ebf3ade73d43b2dc334e4d23bc86ddc47879
https://github.com/llvm/llvm-project/commit/5d87ebf3ade73d43b2dc334e4d23bc86ddc47879
Author: Fangrui Song <i at maskray.me>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M llvm/include/llvm/MC/MCAsmBackend.h
M llvm/include/llvm/MC/MCAssembler.h
M llvm/lib/MC/MCAsmBackend.cpp
M llvm/lib/MC/MCAssembler.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
Log Message:
-----------
[MC] Refactor fixup evaluation and relocation generation
Follow-up to commits 5710759eb390c0d5274c2a4d43967282d7df1993
and 634f9a981571eae000c1adc311014c5c64486187
- Integrate `evaluateFixup` into `recordRelocation` and inline code
within `MCAssembler::layout`, removing `handleFixup`.
- Update `fixupNeedsRelaxation` to bypass `shouldForceRelocation` when
calling `evaluateFixup`, eliminating the `WasForced` workaround for
RISC-V linker relaxation (https://reviews.llvm.org/D46350 ).
Commit: 20d35fe5a58c3d90613dd50ec91aca700e111726
https://github.com/llvm/llvm-project/commit/20d35fe5a58c3d90613dd50ec91aca700e111726
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
M llvm/lib/CodeGen/WindowScheduler.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/ObjectFormats.cpp
M llvm/lib/Target/NVPTX/NVPTXMachineFunctionInfo.h
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
Log Message:
-----------
[llvm] Use llvm::is_contained (NFC) (#135566)
Commit: dc5178cc41d876b4e3d8ace9545f6e9898ef654b
https://github.com/llvm/llvm-project/commit/dc5178cc41d876b4e3d8ace9545f6e9898ef654b
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/WinException.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Log Message:
-----------
[CodeGen] Use llvm::append_range (NFC) (#135567)
Commit: f1ba4bb805b918bc464aa7232cb446cca10ef5a3
https://github.com/llvm/llvm-project/commit/f1ba4bb805b918bc464aa7232cb446cca10ef5a3
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.h
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.cpp
Log Message:
-----------
[Target] Use llvm::append_range (NFC) (#135568)
Commit: 1f195afa57942db3f616e0595eb5816d1359dd2e
https://github.com/llvm/llvm-project/commit/1f195afa57942db3f616e0595eb5816d1359dd2e
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/TreeTransform.h
Log Message:
-----------
[Sema] Use llvm::erase_if (NFC) (#135574)
Commit: ebba554a3211b0b98d3ae33ba70f9d6ceaab6ad4
https://github.com/llvm/llvm-project/commit/ebba554a3211b0b98d3ae33ba70f9d6ceaab6ad4
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M clang/test/CodeGen/attr-target-x86.c
M llvm/lib/Target/X86/X86.td
M llvm/lib/TargetParser/X86TargetParser.cpp
Log Message:
-----------
[X86][AVX10] Remove VAES and VPCLMULQDQ feature from AVX10.1 (#135489)
According to SDM, they require both VAES/VPCLMULQDQ and AVX10.1 CPUID
bits.
Fixes: #135394
Commit: a32d4917c82840179a9ff5686567834922fc4e6d
https://github.com/llvm/llvm-project/commit/a32d4917c82840179a9ff5686567834922fc4e6d
Author: Jim Lin <jim at andestech.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
Log Message:
-----------
[RISCV] Clean up the code for isBareSimmNLsb0. NFC.
Commit: 7778a197e65ad1b0cae794318870d41d8c59a3fb
https://github.com/llvm/llvm-project/commit/7778a197e65ad1b0cae794318870d41d8c59a3fb
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M llvm/include/llvm/MC/MCAsmBackend.h
M llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
Log Message:
-----------
[MC] Remove unused `MCAsmBackend::isMicroMips()` method (NFC) (#135581)
The only use was removed by 4c892770.
Commit: e038c5401c99ca1f19a873a5c88ad7db4645a26a
https://github.com/llvm/llvm-project/commit/e038c5401c99ca1f19a873a5c88ad7db4645a26a
Author: Tianle Liu <tianle.l.liu at intel.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M llvm/lib/Passes/PassBuilderPipelines.cpp
A llvm/test/Other/new-pm-lto-prelink-samplepgo-inline-threshold.ll
R llvm/test/Other/new-pm-thinlto-prelink-samplepgo-inline-threshold.ll
Log Message:
-----------
[LTO][Pipelines] Add 0 hot-caller threshold for SamplePGO + FullLTO (#135152)
If a hot callsite function is not inlined in the 1st build, inlining the
hot callsite in pre-link stage of SPGO 2nd build may lead to Function
Sample not found in profile file in link stage. It will miss some
profile info.
ThinLTO has already considered and dealed with it by setting
HotCallSiteThreshold to 0 to stop the inline. This patch just adds the
same processing for FullLTO.
Commit: 5ecc0ef6b01fe9dcca8fcaa8b306cd94c2239db4
https://github.com/llvm/llvm-project/commit/5ecc0ef6b01fe9dcca8fcaa8b306cd94c2239db4
Author: Krzysztof Drewniak <krzysdrewniak at gmail.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M mlir/docs/DefiningDialects/Operations.md
M mlir/include/mlir/Dialect/LLVMIR/LLVMEnums.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/IR/EnumAttr.td
M mlir/include/mlir/IR/Properties.td
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/test/IR/enum-attr-invalid.mlir
M mlir/test/IR/enum-attr-roundtrip.mlir
M mlir/test/lib/Dialect/Test/TestOps.td
Log Message:
-----------
[mlir] Improve EnumProp, making it take an EnumInfo (#132349)
This commit improves the `EnumProp` class, causing it to wrap around an
`EnumInfo` just like` EnumAttr` does. This EnumProp also has logic for
converting to/from an integer attribute and for being read and written
as bitcode.
The following variants of `EnumProp` are provided:
- `EnumPropWithAttrForm` - an EnumProp that can be constructed from (and
will be converted to, if `storeInCustomAttribute` is true) a custom
attribute, like an `EnumAttr`, instead of a plain integer. This is meant
for backwards compatibility with code that uses enum attributes.
`NamedEnumProp` adds a "`mnemonic` `<` $enum `>`" syntax around the
enum, replicating a common pattern seen in MLIR printers and allowing
for reduced ambiguity.
`NamedEnumPropWithAttrForm` combines both of these extensions.
(Sadly, bytecode auto-upgrade is hampered by the lack of the ability to
optionally parse an attribute.)
Depends on #132148
Commit: d0cf5cd5f9790dc21396936d076389c3be1a9599
https://github.com/llvm/llvm-project/commit/d0cf5cd5f9790dc21396936d076389c3be1a9599
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M clang/include/clang/Support/RISCVVIntrinsicUtils.h
M clang/lib/Sema/SemaRISCV.cpp
M clang/lib/Support/RISCVVIntrinsicUtils.cpp
M clang/utils/TableGen/RISCVVEmitter.cpp
Log Message:
-----------
[RISCV][NFC] Make generated intrinsic records more human-readable (#133710)
We add comment markers and print enum names instead of numbers.
For required extensions, we print the feature list instead of raw
bits.
Commit: 47cbc8706cb5d73f2db101165bf213d558f8b0cb
https://github.com/llvm/llvm-project/commit/47cbc8706cb5d73f2db101165bf213d558f8b0cb
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
Log Message:
-----------
[Scalar] Avoid repeated hash lookups (NFC) (#135585)
Commit: 2ff226ae2c9bdafc686d698b69b4a8519213f325
https://github.com/llvm/llvm-project/commit/2ff226ae2c9bdafc686d698b69b4a8519213f325
Author: Fangrui Song <i at maskray.me>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M llvm/include/llvm/MC/MCAsmBackend.h
M llvm/lib/MC/MCAsmBackend.cpp
M llvm/lib/MC/MCAssembler.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
Log Message:
-----------
MCAsmBackend,Hexagon: Remove MCRelaxableFragment from fixupNeedsRelaxationAdvanced
Among fixupNeedsRelaxationAdvanced (introduced by
https://reviews.llvm.org/D8217) targets, only Hexagon needs the
`MCRelaxableFragment` parameter (commit
86f218e7ec5d941b7785eaebcb8f4cad76db8a64) to get the instruction packet
(MCInst with sub-instruction operands).
As fixupNeedsRelaxationAdvanced follows mayNeedRelaxation, we can store
the MCInst in mayNeedRelaxation and eliminate the MCRelaxableFragment
parameter.
Follow-up to 7c83b7ef1796210451b839f4c58f2815f4aedfe5 that eliminates
the MCRelaxableFragment parameter from fixupNeedsRelaxation.
Commit: b283ff7eb1d7558594063528af7a94cfe2390e98
https://github.com/llvm/llvm-project/commit/b283ff7eb1d7558594063528af7a94cfe2390e98
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
A llvm/include/llvm/CodeGen/BranchRelaxation.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/BranchRelaxation.cpp
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/test/CodeGen/AArch64/branch-relax-block-size.mir
M llvm/test/CodeGen/AArch64/branch-relax-cross-section.mir
M llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
Log Message:
-----------
[CodeGen][NPM] Port BranchRelaxation to NPM (#130067)
This completes the PreEmitPasses.
Commit: 21ff45dea1601d6d12438b5201ff09b8726899be
https://github.com/llvm/llvm-project/commit/21ff45dea1601d6d12438b5201ff09b8726899be
Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M clang/include/clang/Support/RISCVVIntrinsicUtils.h
M clang/lib/Sema/SemaRISCV.cpp
M clang/lib/Support/RISCVVIntrinsicUtils.cpp
M clang/utils/TableGen/RISCVVEmitter.cpp
Log Message:
-----------
Revert "[RISCV][NFC] Make generated intrinsic records more human-readable (#133710)"
This reverts commit d0cf5cd5f9790dc21396936d076389c3be1a9599.
Error: "declaration of ‘clang::RISCV::RequiredExtensions
{anonymous}::SemaRecord::RequiredExtensions’ changes meaning of
‘RequiredExtensions’ [-fpermissive]"
Commit: e57f4e8969db32f075d8f3e554506ec8b187a2f1
https://github.com/llvm/llvm-project/commit/e57f4e8969db32f075d8f3e554506ec8b187a2f1
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M clang/include/clang/Support/RISCVVIntrinsicUtils.h
M clang/lib/Sema/SemaRISCV.cpp
M clang/lib/Support/RISCVVIntrinsicUtils.cpp
M clang/utils/TableGen/RISCVVEmitter.cpp
Log Message:
-----------
[RISCV][NFC] Make generated intrinsic records more human-readable (#133710)
We add comment markers and print enum names instead of numbers.
For required extensions, we print the feature list instead of raw
bits.
This recommits d0cf5cd which was reverted by 21ff45d.
Commit: 63e2963f4a24cb9365d1224e69f64bf643171023
https://github.com/llvm/llvm-project/commit/63e2963f4a24cb9365d1224e69f64bf643171023
Author: Michael Park <mcypark at gmail.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M clang/lib/Serialization/ASTWriter.cpp
A clang/test/Modules/relocatable-modules.cpp
Log Message:
-----------
Support '-fmodule-file-home-is-cwd' for C++ modules. (#135147)
Commit: a3f8359410eb7e14c4a52b47f36e433af40c05e9
https://github.com/llvm/llvm-project/commit/a3f8359410eb7e14c4a52b47f36e433af40c05e9
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M lldb/test/Shell/SymbolFile/NativePDB/inline_sites_live.cpp
Log Message:
-----------
[lldb][test] Fix NativePDB/inline_sites_live.cpp inlined frame format
Adjust after https://github.com/llvm/llvm-project/pull/135343
Commit: 58b5df09dc6f899016fc707bf937b36b36934b6d
https://github.com/llvm/llvm-project/commit/58b5df09dc6f899016fc707bf937b36b36934b6d
Author: YunQiang Su <syq at debian.org>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Builtins.td
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Sema/SemaChecking.cpp
A clang/test/CodeGen/builtin-maxnum-minnum.c
Log Message:
-----------
Clang: Add elementwise minnum/maxnum builtin functions (#129207)
With https://github.com/llvm/llvm-project/pull/112852, we claimed that
llvm.minnum and llvm.maxnum should treat +0.0>-0.0, while libc doesn't
require fmin(3)/fmax(3) for it.
To make llvm.minnum/llvm.maxnum easy to use, we define the builtin
functions for them, include
__builtin_elementwise_minnum
__builtin_elementwise_maxnum
All of them support _Float16, __bf16, float, double, long double.
Commit: 9df153bc146eab7e6c48d5083acb87a6d5c42394
https://github.com/llvm/llvm-project/commit/9df153bc146eab7e6c48d5083acb87a6d5c42394
Author: Mel Chen <mel.chen at sifive.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LV] Remove unused requiresScalarEpilogue function. nfc (#135341)
Commit: ffd5b148941a1146378a247c70c4faface3a1f96
https://github.com/llvm/llvm-project/commit/ffd5b148941a1146378a247c70c4faface3a1f96
Author: Mel Chen <mel.chen at sifive.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse-output.ll
Log Message:
-----------
[LV] Add test cases for reverse accesses involving irregular types. nfc (#135139)
Add a test with irregular type to ensure the vector load/store
instructions are not generated.
Commit: e710a5a9f274162c63e32aa8d88f6a734759b4a5
https://github.com/llvm/llvm-project/commit/e710a5a9f274162c63e32aa8d88f6a734759b4a5
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M llvm/include/llvm/ADT/APFloat.h
M llvm/lib/Support/APFloat.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/test/Transforms/InstCombine/fabs-as-int.ll
M llvm/test/Transforms/InstCombine/fneg-as-int.ll
M llvm/test/Transforms/InstCombine/fneg-fabs-as-int.ll
M llvm/unittests/ADT/APFloatTest.cpp
Log Message:
-----------
[InstCombine] Fold fneg/fabs patterns with ppc_f128 (#130557)
This patch is needed by
https://github.com/llvm/llvm-project/pull/130496.
Commit: 1380a8259e5937d7e871c7a754bbf8a662aaa4da
https://github.com/llvm/llvm-project/commit/1380a8259e5937d7e871c7a754bbf8a662aaa4da
Author: Kazu Hirata <kazu at google.com>
Date: 2025-04-13 (Sun, 13 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
Log Message:
-----------
[AMDGPU] Use llvm::find and llvm::find_if (NFC) (#135582)
Commit: 893cd69872ca8e7be8010699aac32c5678a0e2a6
https://github.com/llvm/llvm-project/commit/893cd69872ca8e7be8010699aac32c5678a0e2a6
Author: Shao-Ce SUN <sunshaoce at outlook.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
A llvm/test/CodeGen/RISCV/emit-x8-as-fp.ll
A llvm/test/MC/Disassembler/RISCV/emit-x8-as-fp.txt
A llvm/test/MC/RISCV/emit-x8-as-fp.s
Log Message:
-----------
[RISCV][MC] Emit `x8` as `fp` instead of `s0` (#135500)
When emphasizing `X8`'s functionality related to Frame Pointer, this option can be passed.
Commit: 150e7b14f9474bc4d6891faaae4de6b8c5f6c797
https://github.com/llvm/llvm-project/commit/150e7b14f9474bc4d6891faaae4de6b8c5f6c797
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
A llvm/test/CodeGen/X86/pr134602.ll
Log Message:
-----------
[X86] Add test coverage for #134602
Commit: cf188d650ce26b4ee3e11101d844361fca15ba64
https://github.com/llvm/llvm-project/commit/cf188d650ce26b4ee3e11101d844361fca15ba64
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
A llvm/test/CodeGen/AMDGPU/promote-alloca-non-byte-sizes.ll
Log Message:
-----------
[AMDGPU] Avoid crashes for non-byte-sized types in PromoteAlloca (#134042)
This patch addresses three problems when promoting allocas to vectors:
- Element types with size < 1 byte in allocas with a vector type caused
divisions by zero.
- Element types whose size doesn't match their AllocSize hit an assertion.
- Access types whose size doesn't match their AllocSize hit an assertion.
With this patch, we do not attempt to promote affected allocas to vectors. In
principle, we could handle these cases in PromoteAlloca, e.g., by truncating
and extending elements from/to their allocation size. It's however unclear if
we ever encounter such cases in practice, so that doesn't seem worth the added
complexity.
For SWDEV-511252
Commit: 53cd5cfc675dad1bf6bc820a72e0eaa72a8909e7
https://github.com/llvm/llvm-project/commit/53cd5cfc675dad1bf6bc820a72e0eaa72a8909e7
Author: Jack Styles <jack.styles at arm.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Driver/ToolChains/Arch/ARM.cpp
A clang/test/Driver/arm-fpu-selection.s
A clang/test/Driver/armv7-default-neon.s
A clang/test/Driver/armv7s-default-vfpv4.s
M clang/test/Driver/armv8.1m.main.s
Log Message:
-----------
[Clang][ARM] Ensure FPU Features are parsed when targeting `cc1as` (#134612)
Previously, `cc1as` did not consider the Features that can be included
from a target's FPU. This could lead to a situation where assembly files
could not compile as cc1as did not know if a feature was supported.
With this change, all the features for the FPU will be passed to `cc1as`
as `-target-feature` lines. By making this change, it will enable
`+nosimd` to be functional, worked on in #130623, and fix a regression
introduced in 8fa0f0efce5fb81eb422e6d7eec74c66dafef4a3 so
armv7s-apple-darwin targets can utilise VFPv4 correctly.
---------
Co-authored-by: Martin Storsjö <martin at martin.st>
Commit: 1df4af6cbcc3bda86fa76b9aba01424ab39077a4
https://github.com/llvm/llvm-project/commit/1df4af6cbcc3bda86fa76b9aba01424ab39077a4
Author: Ricardo Jesus <rjj at nvidia.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
A llvm/test/CodeGen/AArch64/aarch64-sve-fill-spill-pair.ll
A llvm/test/CodeGen/AArch64/sve-vls-ldst-opt.mir
Log Message:
-----------
Reapply "[AArch64][SVE] Pair SVE fill/spill into LDP/STP with -msve-vector-bits=128." (#135177)
Reapplies #134068.
The first patch was missing a check to prevent attempts to pair SVE
fill/spill with other Neon load/store instructions, which could happen
specifically if the Neon instruction was unscaled.
Commit: ed96e4642c76fa199cc427129e6d03fba301a301
https://github.com/llvm/llvm-project/commit/ed96e4642c76fa199cc427129e6d03fba301a301
Author: Matthias Braun <matze at braunis.de>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
M llvm/test/CodeGen/AArch64/peephole-orr.mir
Log Message:
-----------
AArch64: Allow ZEXT+COPY -> FMOV peephole for ZPR registers as well (#135436)
Commit: e29f986838bcd0ff60cf33e7ae5ee867bad0de00
https://github.com/llvm/llvm-project/commit/e29f986838bcd0ff60cf33e7ae5ee867bad0de00
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
A llvm/include/llvm/CodeGen/RemoveLoadsIntoFakeUses.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/RemoveLoadsIntoFakeUses.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/test/CodeGen/X86/fake-use-remove-loads.mir
Log Message:
-----------
[CodeGen][NPM] Port RemoveLoadsIntoFakeUses to NPM (#130068)
Commit: 51fe5d2c314619796c29af6bd717c5c212faa811
https://github.com/llvm/llvm-project/commit/51fe5d2c314619796c29af6bd717c5c212faa811
Author: Björn Pettersson <bjorn.a.pettersson at ericsson.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M llvm/test/Transforms/InstCombine/array.ll
Log Message:
-----------
[InstCombine] Pre-commit tests related to ADDLIKE+GEP->GEP+GEP. NFC (#135154)
InstCombine can transform ADD+GEP into GEP+GEP. But those rewrites does
not currently trigger when the ADD is a disjoint OR (which happens to be
the canonical form for certain ADD operations). Add lit tests to show
that we are lacking such rewrites.
Also add a test case showing that we do not preserve "inbounds nuw",
"nusw nuw" and "nuw" when doing such transforms and the ADD/OR is
known to be NUW.
Commit: 97bc9137e545423334b00d60ab64855ccc434c3a
https://github.com/llvm/llvm-project/commit/97bc9137e545423334b00d60ab64855ccc434c3a
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M .github/workflows/premerge.yaml
Log Message:
-----------
[Github][CI] Upload artifacts directory for premerge workflow
The premerge pipeline currently creates an artifacts directory with some
statistics that gets uploaded on the buildkite side for later
inspection. This patch adds support for this on the Github side by using
the upload artifacts action.
Reviewers: Keenuts, lnihlen, mizvekov, tstellar, Endilll
Reviewed By: mizvekov
Pull Request: https://github.com/llvm/llvm-project/pull/135538
Commit: 0b43a0423bbaa22384d522050a295eb564116d95
https://github.com/llvm/llvm-project/commit/0b43a0423bbaa22384d522050a295eb564116d95
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M clang-tools-extra/clangd/CMakeLists.txt
M clang-tools-extra/clangd/test/CMakeLists.txt
M clang-tools-extra/clangd/test/lit.site.cfg.py.in
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Driver/Options.td
M clang/include/clang/Driver/ToolChain.h
M clang/include/clang/Support/RISCVVIntrinsicUtils.h
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/Targets/AMDGPU.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/AIX.cpp
M clang/lib/Driver/ToolChains/AIX.h
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/Arch/ARM.cpp
M clang/lib/Driver/ToolChains/PPCLinux.cpp
M clang/lib/Driver/ToolChains/PPCLinux.h
M clang/lib/Driver/ToolChains/ROCm.h
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Format/WhitespaceManager.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaRISCV.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Support/RISCVVIntrinsicUtils.cpp
M clang/test/AST/ByteCode/codegen.cpp
M clang/test/CodeGen/AArch64/sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c
M clang/test/CodeGen/attr-target-x86.c
A clang/test/CodeGen/builtin-maxnum-minnum.c
M clang/test/CodeGenOpenCL/addr-space-struct-arg.cl
M clang/test/CodeGenOpenCL/amdgpu-abi-struct-arg-byref.cl
M clang/test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl
M clang/test/CodeGenOpenCL/opencl-kernel-call.cl
M clang/test/Driver/amdgpu-openmp-toolchain.c
A clang/test/Driver/arm-fpu-selection.s
A clang/test/Driver/armv7-default-neon.s
A clang/test/Driver/armv7s-default-vfpv4.s
M clang/test/Driver/armv8.1m.main.s
M clang/test/Driver/hip-device-libs.hip
M clang/test/Driver/rocm-device-libs.cl
A clang/test/Modules/relocatable-modules.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/utils/TableGen/ClangOpcodesEmitter.cpp
M clang/utils/TableGen/RISCVVEmitter.cpp
M flang/test/Driver/flang-ld-powerpc.f90
M flang/test/Driver/linker-flags.f90
M flang/test/Driver/omp-driver-offload.f90
M libcxx/include/__bit/popcount.h
M libcxx/include/__stop_token/atomic_unique_lock.h
M libunwind/docs/BuildingLibunwind.rst
M lldb/include/lldb/Symbol/SymbolContext.h
M lldb/include/lldb/Target/Language.h
M lldb/source/Core/FormatEntity.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.h
M lldb/source/Symbol/SymbolContext.cpp
M lldb/source/Target/Language.cpp
M lldb/test/API/functionalities/param_entry_vals/basic_entry_values/main.cpp
M lldb/test/API/functionalities/tail_call_frames/inlining_and_tail_calls/main.cpp
M lldb/test/API/python_api/target/read-instructions-flavor/TestTargetReadInstructionsFlavor.py
M lldb/test/Shell/Recognizer/verbose_trap-in-stl-max-depth.test
M lldb/test/Shell/Settings/TestFrameFormatName.test
M lldb/test/Shell/SymbolFile/NativePDB/inline_sites_live.cpp
M llvm/cmake/modules/TableGen.cmake
M llvm/include/llvm/ADT/APFloat.h
A llvm/include/llvm/CodeGen/BranchRelaxation.h
A llvm/include/llvm/CodeGen/RemoveLoadsIntoFakeUses.h
M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
M llvm/include/llvm/DebugInfo/LogicalView/Readers/LVDWARFReader.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/MC/MCAsmBackend.h
M llvm/include/llvm/MC/MCAssembler.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/TableGen/Main.h
M llvm/include/llvm/TableGen/StringToOffsetTable.h
M llvm/lib/Analysis/PHITransAddr.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/CodeGen/AsmPrinter/WinException.cpp
M llvm/lib/CodeGen/BranchRelaxation.cpp
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/CodeGen/RemoveLoadsIntoFakeUses.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/CodeGen/WindowScheduler.cpp
M llvm/lib/ExecutionEngine/Orc/DebugObjectManagerPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/ObjectFormats.cpp
M llvm/lib/MC/MCAsmBackend.cpp
M llvm/lib/MC/MCAssembler.cpp
M llvm/lib/ObjCopy/ELF/ELFObjcopy.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Passes/StandardInstrumentations.cpp
M llvm/lib/Support/APFloat.cpp
M llvm/lib/TableGen/CMakeLists.txt
M llvm/lib/TableGen/Main.cpp
A llvm/lib/TableGen/StringToOffsetTable.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
M llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.h
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h
M llvm/lib/Target/Hexagon/HexagonTfrCleanup.cpp
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
M llvm/lib/Target/NVPTX/NVPTXMachineFunctionInfo.h
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
M llvm/lib/Target/X86/X86.td
M llvm/lib/TargetParser/X86TargetParser.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
M llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
A llvm/test/Analysis/ScalarEvolution/pr135531.ll
A llvm/test/CodeGen/AArch64/aarch64-sve-fill-spill-pair.ll
M llvm/test/CodeGen/AArch64/branch-relax-block-size.mir
M llvm/test/CodeGen/AArch64/branch-relax-cross-section.mir
M llvm/test/CodeGen/AArch64/peephole-orr.mir
A llvm/test/CodeGen/AArch64/sve-vls-ldst-opt.mir
M llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
A llvm/test/CodeGen/AMDGPU/promote-alloca-non-byte-sizes.ll
M llvm/test/CodeGen/AMDGPU/swdev380865.ll
M llvm/test/CodeGen/PowerPC/pr43527.ll
M llvm/test/CodeGen/PowerPC/pr48519.ll
M llvm/test/CodeGen/PowerPC/sms-grp-order.ll
A llvm/test/CodeGen/RISCV/emit-x8-as-fp.ll
M llvm/test/CodeGen/X86/fake-use-remove-loads.mir
A llvm/test/CodeGen/X86/pr134602.ll
M llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop2.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop2.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop2.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp8.s
A llvm/test/MC/Disassembler/RISCV/emit-x8-as-fp.txt
A llvm/test/MC/RISCV/emit-x8-as-fp.s
M llvm/test/MC/RISCV/function-call-invalid.s
M llvm/test/MC/RISCV/tail-call-invalid.s
A llvm/test/Other/new-pm-lto-prelink-samplepgo-inline-threshold.ll
R llvm/test/Other/new-pm-thinlto-prelink-samplepgo-inline-threshold.ll
M llvm/test/Transforms/GVN/pr65447.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-abs-srshl.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-all-active-lanes-cvt.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-loadstore.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-cmpne.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-strictfp.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsics-combine-to-u-forms.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsics-ptest.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsics-rdffr-predication.ll
M llvm/test/Transforms/InstCombine/array.ll
M llvm/test/Transforms/InstCombine/fabs-as-int.ll
M llvm/test/Transforms/InstCombine/fneg-as-int.ll
M llvm/test/Transforms/InstCombine/fneg-fabs-as-int.ll
M llvm/test/Transforms/InstCombine/sincospi.ll
M llvm/test/Transforms/LICM/pr50367.ll
M llvm/test/Transforms/LICM/pr59324.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse-output.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/pr47665.ll
M llvm/test/Transforms/LoopVectorize/X86/constant-fold.ll
M llvm/test/Transforms/ObjCARC/contract.ll
M llvm/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll
M llvm/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table_big.ll
M llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest.ll
M llvm/unittests/ADT/APFloatTest.cpp
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
M llvm/utils/TableGen/Basic/SequenceToOffsetTable.h
M llvm/utils/TableGen/Basic/TableGen.cpp
M llvm/utils/TableGen/SDNodeInfoEmitter.cpp
M llvm/utils/gn/secondary/clang-tools-extra/clangd/test/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/TableGen/BUILD.gn
M mlir/docs/DefiningDialects/Operations.md
M mlir/include/mlir/Dialect/LLVMIR/LLVMEnums.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/IR/EnumAttr.td
M mlir/include/mlir/IR/Properties.td
M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
M mlir/lib/Dialect/GPU/Transforms/ShuffleRewriter.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
A mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-unsupported.mlir
M mlir/test/Dialect/GPU/shuffle-rewrite.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/IR/enum-attr-invalid.mlir
M mlir/test/IR/enum-attr-roundtrip.mlir
M mlir/test/lib/Dialect/Test/TestOps.td
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.4
[skip ci]
Commit: 9555e5b88eb76957d9e34f5f2e8b94389535a9cd
https://github.com/llvm/llvm-project/commit/9555e5b88eb76957d9e34f5f2e8b94389535a9cd
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-04-14 (Mon, 14 Apr 2025)
Changed paths:
M clang-tools-extra/clangd/CMakeLists.txt
M clang-tools-extra/clangd/test/CMakeLists.txt
M clang-tools-extra/clangd/test/lit.site.cfg.py.in
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Driver/Options.td
M clang/include/clang/Driver/ToolChain.h
M clang/include/clang/Support/RISCVVIntrinsicUtils.h
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/Targets/AMDGPU.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/AIX.cpp
M clang/lib/Driver/ToolChains/AIX.h
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/Arch/ARM.cpp
M clang/lib/Driver/ToolChains/PPCLinux.cpp
M clang/lib/Driver/ToolChains/PPCLinux.h
M clang/lib/Driver/ToolChains/ROCm.h
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Format/WhitespaceManager.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaRISCV.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Support/RISCVVIntrinsicUtils.cpp
M clang/test/AST/ByteCode/codegen.cpp
M clang/test/CodeGen/AArch64/sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c
M clang/test/CodeGen/attr-target-x86.c
A clang/test/CodeGen/builtin-maxnum-minnum.c
M clang/test/CodeGenOpenCL/addr-space-struct-arg.cl
M clang/test/CodeGenOpenCL/amdgpu-abi-struct-arg-byref.cl
M clang/test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl
M clang/test/CodeGenOpenCL/opencl-kernel-call.cl
M clang/test/Driver/amdgpu-openmp-toolchain.c
A clang/test/Driver/arm-fpu-selection.s
A clang/test/Driver/armv7-default-neon.s
A clang/test/Driver/armv7s-default-vfpv4.s
M clang/test/Driver/armv8.1m.main.s
M clang/test/Driver/hip-device-libs.hip
M clang/test/Driver/rocm-device-libs.cl
A clang/test/Modules/relocatable-modules.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/utils/TableGen/ClangOpcodesEmitter.cpp
M clang/utils/TableGen/RISCVVEmitter.cpp
M flang/test/Driver/flang-ld-powerpc.f90
M flang/test/Driver/linker-flags.f90
M flang/test/Driver/omp-driver-offload.f90
M libcxx/include/__bit/popcount.h
M libcxx/include/__stop_token/atomic_unique_lock.h
M libunwind/docs/BuildingLibunwind.rst
M lldb/include/lldb/Symbol/SymbolContext.h
M lldb/include/lldb/Target/Language.h
M lldb/source/Core/FormatEntity.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.h
M lldb/source/Symbol/SymbolContext.cpp
M lldb/source/Target/Language.cpp
M lldb/test/API/functionalities/param_entry_vals/basic_entry_values/main.cpp
M lldb/test/API/functionalities/tail_call_frames/inlining_and_tail_calls/main.cpp
M lldb/test/API/python_api/target/read-instructions-flavor/TestTargetReadInstructionsFlavor.py
M lldb/test/Shell/Recognizer/verbose_trap-in-stl-max-depth.test
M lldb/test/Shell/Settings/TestFrameFormatName.test
M lldb/test/Shell/SymbolFile/NativePDB/inline_sites_live.cpp
M llvm/cmake/modules/TableGen.cmake
M llvm/include/llvm/ADT/APFloat.h
A llvm/include/llvm/CodeGen/BranchRelaxation.h
A llvm/include/llvm/CodeGen/RemoveLoadsIntoFakeUses.h
M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
M llvm/include/llvm/DebugInfo/LogicalView/Readers/LVDWARFReader.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/MC/MCAsmBackend.h
M llvm/include/llvm/MC/MCAssembler.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/TableGen/Main.h
M llvm/include/llvm/TableGen/StringToOffsetTable.h
M llvm/lib/Analysis/PHITransAddr.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/CodeGen/AsmPrinter/WinException.cpp
M llvm/lib/CodeGen/BranchRelaxation.cpp
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/CodeGen/RemoveLoadsIntoFakeUses.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/CodeGen/WindowScheduler.cpp
M llvm/lib/ExecutionEngine/Orc/DebugObjectManagerPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/ObjectFormats.cpp
M llvm/lib/MC/MCAsmBackend.cpp
M llvm/lib/MC/MCAssembler.cpp
M llvm/lib/ObjCopy/ELF/ELFObjcopy.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Passes/StandardInstrumentations.cpp
M llvm/lib/Support/APFloat.cpp
M llvm/lib/TableGen/CMakeLists.txt
M llvm/lib/TableGen/Main.cpp
A llvm/lib/TableGen/StringToOffsetTable.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
M llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.h
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h
M llvm/lib/Target/Hexagon/HexagonTfrCleanup.cpp
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
M llvm/lib/Target/NVPTX/NVPTXMachineFunctionInfo.h
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
M llvm/lib/Target/X86/X86.td
M llvm/lib/TargetParser/X86TargetParser.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
M llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
A llvm/test/Analysis/ScalarEvolution/pr135531.ll
A llvm/test/CodeGen/AArch64/aarch64-sve-fill-spill-pair.ll
M llvm/test/CodeGen/AArch64/branch-relax-block-size.mir
M llvm/test/CodeGen/AArch64/branch-relax-cross-section.mir
M llvm/test/CodeGen/AArch64/peephole-orr.mir
A llvm/test/CodeGen/AArch64/sve-vls-ldst-opt.mir
M llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
A llvm/test/CodeGen/AMDGPU/promote-alloca-non-byte-sizes.ll
M llvm/test/CodeGen/AMDGPU/swdev380865.ll
M llvm/test/CodeGen/PowerPC/pr43527.ll
M llvm/test/CodeGen/PowerPC/pr48519.ll
M llvm/test/CodeGen/PowerPC/sms-grp-order.ll
A llvm/test/CodeGen/RISCV/emit-x8-as-fp.ll
M llvm/test/CodeGen/X86/fake-use-remove-loads.mir
A llvm/test/CodeGen/X86/pr134602.ll
M llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop2.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop2.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop2.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp8.s
A llvm/test/MC/Disassembler/RISCV/emit-x8-as-fp.txt
A llvm/test/MC/RISCV/emit-x8-as-fp.s
M llvm/test/MC/RISCV/function-call-invalid.s
M llvm/test/MC/RISCV/tail-call-invalid.s
A llvm/test/Other/new-pm-lto-prelink-samplepgo-inline-threshold.ll
R llvm/test/Other/new-pm-thinlto-prelink-samplepgo-inline-threshold.ll
M llvm/test/Transforms/GVN/pr65447.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-abs-srshl.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-all-active-lanes-cvt.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-loadstore.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-cmpne.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-strictfp.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsics-combine-to-u-forms.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsics-ptest.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsics-rdffr-predication.ll
M llvm/test/Transforms/InstCombine/array.ll
M llvm/test/Transforms/InstCombine/fabs-as-int.ll
M llvm/test/Transforms/InstCombine/fneg-as-int.ll
M llvm/test/Transforms/InstCombine/fneg-fabs-as-int.ll
M llvm/test/Transforms/InstCombine/sincospi.ll
M llvm/test/Transforms/LICM/pr50367.ll
M llvm/test/Transforms/LICM/pr59324.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse-output.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/pr47665.ll
M llvm/test/Transforms/LoopVectorize/X86/constant-fold.ll
M llvm/test/Transforms/ObjCARC/contract.ll
M llvm/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll
M llvm/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table_big.ll
M llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest.ll
M llvm/unittests/ADT/APFloatTest.cpp
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
M llvm/utils/TableGen/Basic/SequenceToOffsetTable.h
M llvm/utils/TableGen/Basic/TableGen.cpp
M llvm/utils/TableGen/SDNodeInfoEmitter.cpp
M llvm/utils/gn/secondary/clang-tools-extra/clangd/test/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/TableGen/BUILD.gn
M mlir/docs/DefiningDialects/Operations.md
M mlir/include/mlir/Dialect/LLVMIR/LLVMEnums.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/IR/EnumAttr.td
M mlir/include/mlir/IR/Properties.td
M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
M mlir/lib/Dialect/GPU/Transforms/ShuffleRewriter.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
A mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-unsupported.mlir
M mlir/test/Dialect/GPU/shuffle-rewrite.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/IR/enum-attr-invalid.mlir
M mlir/test/IR/enum-attr-roundtrip.mlir
M mlir/test/lib/Dialect/Test/TestOps.td
Log Message:
-----------
rebase
Created using spr 1.3.4
Compare: https://github.com/llvm/llvm-project/compare/cb1924f997f4...9555e5b88eb7
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