[all-commits] [llvm/llvm-project] ffd5b1: [LV] Add test cases for reverse accesses involving...

[Mel Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ffd5b148941a1146378a247c70c4faface3a1f96
      https://github.com/llvm/llvm-project/commit/ffd5b148941a1146378a247c70c4faface3a1f96
  Author: Mel Chen <mel.chen at sifive.com>
  Date:   2025-04-14 (Mon, 14 Apr 2025)

  Changed paths:
    M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse-output.ll

  Log Message:
  -----------
  [LV] Add test cases for reverse accesses involving irregular types. nfc (#135139)

Add a test with irregular type to ensure the vector load/store
instructions are not generated.



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