[all-commits] [llvm/llvm-project] 9c3115: TableGen: Optimize super-register class computatio...

[Nicolai Hähnle via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9c31155ead6e68450b8c2de38f5bec8f5c5db810
      https://github.com/llvm/llvm-project/commit/9c31155ead6e68450b8c2de38f5bec8f5c5db810
  Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
  Date:   2025-04-10 (Thu, 10 Apr 2025)

  Changed paths:
    M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
    M llvm/utils/TableGen/Common/CodeGenRegisters.h
    M llvm/utils/TableGen/RegisterBankEmitter.cpp

  Log Message:
  -----------
  TableGen: Optimize super-register class computation (#134865)

Inferring super-register classes naively requires checking every
register class against every other register class and sub-register
index.
Each of those checks is itself a non-trivial operation on register sets.

Culling as many (RC, RC, SubIdx) triples as possible is important for
the running time of TableGen for architectures with complex sub-register
relations.

Use transitivity to cull many (RC, RC, SubIdx) triples. This
unfortunately requires us to complete the transitive closure of
super-register classes explicitly, but it still cuts down the running
time on AMDGPU substantially -- in some upcoming work in the
backend by more than half (in very rough measurements).

This changes the names of some of the inferred register classes, since
the order in which they are inferred changes. The names of the inferred
register classes become shorter, which reduces the size of the generated
files.

Replacing some uses of SmallPtrSet by DenseSet shaves off a few more
percent; there are hundreds of register classes in AMDGPU.

Tweaking the topological signature check to skip reigsters without
super-registers further helps skip register classes that have "pseudo"
registers in them whose sub- and super-register structure is trivial.



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