[all-commits] [llvm/llvm-project] c80080: [AArch64][SVE] Pair SVE fill/spill into LDP/STP wi...

[Ricardo Jesus via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c80080ff7e105eb42d486ed473fa9c82fb518b0a
      https://github.com/llvm/llvm-project/commit/c80080ff7e105eb42d486ed473fa9c82fb518b0a
  Author: Ricardo Jesus <rjj at nvidia.com>
  Date:   2025-04-09 (Wed, 09 Apr 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
    A llvm/test/CodeGen/AArch64/aarch64-sve-fill-spill-pair.ll

  Log Message:
  -----------
  [AArch64][SVE] Pair SVE fill/spill into LDP/STP with -msve-vector-bits=128. (#134068)

When compiling with -msve-vector-bits=128 or vscale_range(1, 1) and when
the offsets allow it, we can pair SVE LDR/STR instructions into Neon
LDP/STP.

For example, given:
```cpp
#include <arm_sve.h>

void foo(double const *ldp, double *stp) {
  svbool_t pg = svptrue_b64();
  svfloat64_t ld1 = svld1_f64(pg, ldp);
  svfloat64_t ld2 = svld1_f64(pg, ldp+svcntd());
  svst1_f64(pg, stp, ld1);
  svst1_f64(pg, stp+svcntd(), ld2);
}
```

When compiled with `-msve-vector-bits=128`, we currently generate:
```gas
foo:
        ldr     z0, [x0]
        ldr     z1, [x0, #1, mul vl]
        str     z0, [x1]
        str     z1, [x1, #1, mul vl]
        ret
```

With this patch, we instead generate:
```gas
foo:
        ldp     q0, q1, [x0]
        stp     q0, q1, [x1]
        ret
```

This is an alternative, more targetted approach to #127500.



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